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Analog-to-Digital ConvertersEMK310

ContentsArticles

Analog-to-digital converter 1Flash ADC 13Successive approximation ADC 15Integrating ADC 17

ReferencesArticle Sources and Contributors 26Image Sources, Licenses and Contributors 27

Article LicensesLicense 28

Analog-to-digital converter 1

Analog-to-digital converter

4-channel stereo multiplexed analog-to-digital converterWM8775SEDS made by Wolfson Microelectronics placed on a X-Fi

Fatal1ty Pro sound card.

An analog-to-digital converter (abbreviated ADC,A/D or A to D) is a device that converts a continuousquantity to a discrete digital number. The reverseoperation is performed by a digital-to-analog converter(DAC).

Typically, an ADC is an electronic device that convertsan input analog voltage (or current) to a digital numberproportional to the magnitude of the voltage or current.However, some non-electronic or only partiallyelectronic devices, such as rotary encoders, can also beconsidered ADCs.

The digital output may use different coding schemes.Typically the digital output will be a two's complementbinary number that is proportional to the input, butthere are other possibilities. An encoder, for example,might output a Gray code.

An ADC might be used to make an isolated measurement. ADCs are also used to quantize time-varying signals byturning them into a sequence of digital samples. The result is quantized in both time and value.

Concepts

Resolution

Fig. 1. An 8-level ADC coding scheme.

The resolution of the converter indicates the number ofdiscrete values it can produce over the range of analogvalues. The values are usually stored electronically inbinary form, so the resolution is usually expressed inbits. In consequence, the number of discrete valuesavailable, or "levels", is usually a power of two. Forexample, an ADC with a resolution of 8 bits canencode an analog input to one in 256 different levels,since 28=256. The values can represent the rangesfrom 0 to 255 (i.e. unsigned integer) or from 128 to127 (i.e. signed integer), depending on the application.

Resolution can also be defined electrically, andexpressed in volts. The minimum change in voltagerequired to guarantee a change in the output code levelis called the LSB (least significant bit, since this is the voltage represented by a change in the LSB). The resolution Qof the ADC is equal to the LSB voltage. The voltage resolution of an ADC is equal to its overall voltagemeasurement range divided by the number of discrete voltage intervals:

Analog-to-digital converter 2

Fig. 2. An 8-level ADC coding scheme. As in figure 1 but withmid-tread coding.

Fig. 3. An 8-level ADC mid-tread coding scheme. As in figure 2 butwith equal half-LSB intervals at the highest and lowest codes. Note

that LSB is now slightly larger than in figures 1 and 2.

where N is the number of voltage intervals and EFSR is the full scale voltage range. EFSR is given by

where VRefHi and VRefLow are the upper and lower extremes, respectively, of the voltages that can be coded.Normally, the number of voltage intervals is given by

where M is the ADC's resolution in bits.That is, one voltage interval is assigned per code level. However, figure 3 shows a situation where

Some examples: Example 1

Coding scheme as in figure 1

Analog-to-digital converter 3

Full scale measurement range = 0 to 10 volts ADC resolution is 12 bits: 212 = 4096 quantization levels (codes) ADC voltage resolution, Q = (10V 0V) / 4096 = 10V / 4096 0.00244 V 2.44 mV.

Example 2 Coding scheme as in figure 2 Full scale measurement range = -10 to +10 volts ADC resolution is 14 bits: 214 = 16384 quantization levels (codes) ADC voltage resolution is, Q = (10V (10V)) / 16384 = 20V / 16384 0.00122 V 1.22 mV.

Example 3 Coding scheme as in figure 3 Full scale measurement range = 0 to 7 volts ADC resolution is 3 bits: 23 = 8 quantization levels (codes) ADC voltage resolution is, Q = (7 V 0 V)/7 = 7 V/7 = 1 V = 1000 mV

In most ADCs, the smallest output code ("0" in an unsigned system) represents a voltage range which is 0.5Q, that is,half the ADC voltage resolution (Q). The largest code represents a range of 1.5Q as in figure 2 (if this were 0.5Qalso, the result would be as figure 3). The other N 2 codes are all equal in width and represent the ADC voltageresolution (Q) calculated above. Doing this centers the code on an input voltage that represents the M th division ofthe input voltage range. This practice is called "mid-tread" operation. This type of ADC can be modeledmathematically as:

The exception to this convention seems to be the Microchip PIC processor, where all M steps are equal width, asshown in figure 1. This practice is called "Mid-Rise with Offset" operation.

In practice, the useful resolution of a converter is limited by the best signal-to-noise ratio (SNR) that can be achievedfor a digitized signal. An ADC can resolve a signal to only a certain number of bits of resolution, called the effectivenumber of bits (ENOB). One effective bit of resolution changes the signal-to-noise ratio of the digitized signal by 6dB, if the resolution is limited by the ADC. If a preamplifier has been used prior to A/D conversion, the noiseintroduced by the amplifier can be an important contributing factor towards the overall SNR.

Response type

Linear ADCs

Most ADCs are of a type known as linear[1] The term linear as used here means that the range of the input valuesthat map to each output value has a linear relationship with the output value, i.e., that the output value k is used forthe range of input values from

m(k + b)to

m(k + 1 + b),where m and b are constants. Here b is typically 0 or 0.5. When b = 0, the ADC is referred to as mid-rise, and whenb = 0.5 it is referred to as mid-tread.

Analog-to-digital converter 4

Non-linear ADCs

If the probability density function of a signal being digitized is uniform, then the signal-to-noise ratio relative to thequantization noise is the best possible. Because this is often not the case, it is usual to pass the signal through itscumulative distribution function (CDF) before the quantization. This is good because the regions that are moreimportant get quantized with a better resolution. In the dequantization process, the inverse CDF is needed.This is the same principle behind the companders used in some tape-recorders and other communication systems,and is related to entropy maximization.For example, a voice signal has a Laplacian distribution. This means that the region around the lowest levels, near 0,carries more information than the regions with higher amplitudes. Because of this, logarithmic ADCs are verycommon in voice communication systems to increase the dynamic range of the representable values while retainingfine-granular fidelity in the low-amplitude region.An eight-bit A-law or the -law logarithmic ADC covers the wide dynamic range and has a high resolution in thecritical low-amplitude region, that would otherwise require a 12-bit linear ADC.

AccuracyAn ADC has several sources of errors. Quantization error and (assuming the ADC is intended to be linear)non-linearity are intrinsic to any analog-to-digital conversion. There is also a so-called aperture error which is dueto a clock jitter and is revealed when digitizing a time-variant signal (not a constant value).These errors are measured in a unit called the LSB, which is an abbreviation for least significant bit. In the aboveexample of an eight-bit ADC, an error of one LSB is 1/256 of the full signal range, or about 0.4%.

Quantization error

Quantization error (or quantization noise) is the difference between the original signal and the digitized signal.Hence, The magnitude of the quantization error at the sampling instant is between zero and half of one LSB.Quantization error is due to the finite resolution of the digital representation of the signal, and is an unavoidableimperfection in all types of ADCs.

Non-linearity

All ADCs suffer from non-linearity errors caused by their physical imperfections, causing their output to deviatefrom a linear function (or some other function, in the case of a deliberately non-linear ADC) of their input. Theseerrors can sometimes be mitigated by calibration, or prevented by testing.Important parameters for linearity are integral non-linearity (INL) and differential non-linearity (DNL). Thesenon-linearities reduce the dynamic range of the signals that can be digitized by the ADC, also reducing the effectiveresolution of the ADC.

Aperture error

Imagine that we are digitizing a sine wave . Provided that the actual sampling timeuncertainty due to the clock jitter is , the error caused by this phenomenon can be estimated as

.The error is zero for DC, small at low frequencies, but significant when high frequencies have high amplitudes. Thiseffect can be ignored if it is drowned out by the quantizing error. Jitter requirements can be calculated using the

following formula: , where q is a number of ADC bits.

Analog-to-digital converter 5

ADCresolution

in bit

input frequency

1Hz 44.1kHz 192kHz 1MHz 10MHz 100MHz 1GHz

8 1243 s 28.2 ns 6.48 ns 1.24 ns 124 ps 12.4 ps 1.24 ps

10 311 s 7.05 ns 1.62 ns 311 ps 31.1 ps 3.11 ps 0.31 ps

12 77.7 s 1.76 ns 405 ps 77.7 ps 7.77 ps 0.78 ps 0.08 ps

14 19.4 s 441 ps 101 ps 19.4 ps 1.94 ps 0.19 ps 0.02 ps

16 4.86 s 110 ps 25.3 ps 4.86 ps 0.49 ps 0.05 ps

18 1.21 s 27.5 ps 6.32 ps 1.21 ps 0.12 ps

20 304 ns 6.88 ps 1.58 ps 0.16 ps

24 19.0 ns 0.43 ps 0.10 ps

32 74.1 ps

This table shows, for example, that it is not worth using a precise 24-bit ADC for sound recording if there is not anultra low jitter clock. One should consider taking this phenomenon into account before choosing an ADC.Clock jitter is caused by phase noise.[2] [3] The resolution of ADCs with a digitization bandwidth between 1MHzand 1GHz is limited by jitter.[4]

When sampling audio signals at 44.1kHz, the anti-aliasing filter should have eliminated all frequencies above22kHz. The input frequency (in this case, 22kHz), not the ADC clock frequency, is the determining factor withrespect to jitter performance.[5]

Sampling rateThe analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is thereforerequired to define the rate at which new digital values are sampled from the analog signal. The rate of new values iscalled the sampling rate or sampling frequency of the converter.A continuously varying bandlimited signal can be sampled (that is, the signal values at intervals of time T, thesampling time, are measured and stored) and then the original signal can be exactly reproduced from thediscrete-time values by an interpolation formula. The accuracy is limited by quantization error. However, thisfaithful reproduction is only possible if the sampling rate is higher than twice the highest frequency of the signal.This is essentially what is embodied in the Shannon-Nyquist sampling theorem.Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constantduring the time that the converter performs a conversion (called the conversion time). An input circuit called asample and hold performs this taskin most cases by using a capacitor to store the analog voltage at the input, andusing an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits includethe sample and hold subsystem internally.

AliasingAll ADCs work by sampling their input at discrete intervals of time. Their output is therefore an incomplete pictureof the behaviour of the input. There is no way of knowing, by looking at the output, what the input was doingbetween one sampling instant and the next. If the input is known to be changing slowly compared to the samplingrate, then it can be assumed that the value of the signal between two sample instants was somewhere between thetwo sampled values. If, however, the input signal is changing rapidly compared to the sample rate, then thisassumption is not valid.

Analog-to-digital converter 6

If the digital values produced by the ADC are, at some later stage in the system, converted back to analog values bya digital to analog converter or DAC, it is desirable that the output of the DAC be a faithful representation of theoriginal signal. If the input signal is changing much faster than the sample rate, then this will not be the case, andspurious signals called aliases will be produced at the output of the DAC. The frequency of the aliased signal is thedifference between the signal frequency and the sampling rate. For example, a 2kHz sine wave being sampled at1.5kHz would be reconstructed as a 500Hz sine wave. This problem is called aliasing.To avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies above half the sampling rate.This filter is called an anti-aliasing filter, and is essential for a practical ADC system that is applied to analog signalswith higher frequency content.Although aliasing in most systems is unwanted, it should also be noted that it can be exploited to providesimultaneous down-mixing of a band-limited high frequency signal (see undersampling and frequency mixer).

DitherIn A-to-D converters, performance can usually be improved using dither. This is a very small amount of randomnoise (white noise) which is added to the input before conversion. Its amplitude is set to be twice the value of theleast significant bit. Its effect is to cause the state of the LSB to randomly oscillate between 0 and 1 in the presenceof very low levels of input, rather than sticking at a fixed value. Rather than the signal simply getting cut offaltogether at this low level (which is only being quantized to a resolution of 1 bit), it extends the effective range ofsignals that the A-to-D converter can convert, at the expense of a slight increase in noise - effectively thequantization error is diffused across a series of noise values which is far less objectionable than a hard cutoff. Theresult is an accurate representation of the signal over time. A suitable filter at the output of the system can thusrecover this small signal variation.An audio signal of very low level (with respect to the bit depth of the ADC) sampled without dither soundsextremely distorted and unpleasant. Without dither the low level may cause the least significant bit to "stick" at 0 or1. With dithering, the true level of the audio may be calculated by averaging the actual quantized sample with aseries of other samples [the dither] that are recorded over time.A virtually identical process, also called dither or dithering, is often used when quantizing photographic images to afewer number of bits per pixelthe image becomes noisier but to the eye looks far more realistic than the quantizedimage, which otherwise becomes banded. This analogous process may help to visualize the effect of dither on ananalogue audio signal that is converted to digital.Dithering is also used in integrating systems such as electricity meters. Since the values are added together, thedithering produces results that are more exact than the LSB of the analog-to-digital converter.Note that dither can only increase the resolution of a sampler, it cannot improve the linearity, and thus accuracy doesnot necessarily improve.

OversamplingUsually, signals are sampled at the minimum rate required, for economy, with the result that the quantization noiseintroduced is white noise spread over the whole pass band of the converter. If a signal is sampled at a rate muchhigher than the Nyquist frequency and then digitally filtered to limit it to the signal bandwidth there are the followingadvantages: digital filters can have better properties (sharper rolloff, phase) than analogue filters, so a sharper anti-aliasing

filter can be realised and then the signal can be downsampled giving a better result a 20-bit ADC can be made to act as a 24-bit ADC with 256 oversampling the signal-to-noise ratio due to quantization noise will be higher than if the whole available band had been used.

With this technique, it is possible to obtain an effective resolution larger than that provided by the converter alone

Analog-to-digital converter 7

The improvement in SNR is 3dB (equivalent to 0.5 bits) per octave of oversampling which is not sufficient formany applications. Therefore, oversampling is usually coupled with noise shaping (see sigma-delta modulators).With noise shaping, the improvement is 6L+3dB per octave where L is the order of loop filter used for noiseshaping. e.g. - a 2nd order loop filter will provide an improvement of 15dB/octave.

Relative speed and precisionThe speed of an ADC varies by type. The Wilkinson ADC is limited by the clock rate which is processable bycurrent digital circuits. Currently, frequencies up to 300MHz are possible. The conversion time is directlyproportional to the number of channels. For a successive approximation ADC, the conversion time scales with thelogarithm of the number of channels. Thus for a large number of channels, it is possible that the successiveapproximation ADC is faster than the Wilkinson. However, the time consuming steps in the Wilkinson are digital,while those in the successive approximation are analog. Since analog is inherently slower than digital, as the numberof channels increases, the time required also increases. Thus there are competing processes at work. Flash ADCs arecertainly the fastest type of the three. The conversion is basically performed in a single parallel step. For an 8-bitunit, conversion takes place in a few tens of nanoseconds.There is, as expected, somewhat of a trade off between speed and precision. Flash ADCs have drifts anduncertainties associated with the comparator levels, which lead to poor uniformity in channel width. Flash ADCshave a resulting poor linearity. For successive approximation ADCs, poor linearity is also apparent, but less so thanfor flash ADCs. Here, non-linearity arises from accumulating errors from the subtraction processes. WilkinsonADCs are the best of the three. These have the best differential non-linearity. The other types require channelsmoothing in order to achieve the level of the Wilkinson.[6] [7]

The sliding scale principleThe sliding scale or randomizing method can be employed to greatly improve the channel width uniformity anddifferential linearity of any type of ADC, but especially flash and successive approximation ADCs. Under normalconditions, a pulse of a particular amplitude is always converted to a certain channel number. The problem lies inthat channels are not always of uniform width, and the differential linearity decreases proportionally with thedivergence from the average width. The sliding scale principle uses an averaging effect to overcome thisphenomenon. A random, but known analog voltage is added to the input pulse. It is then converted to digital form,and the equivalent digital version is subtracted, thus restoring it to its original value. The advantage is that theconversion has taken place at a random point. The statistical distribution of the final channel numbers is decided by aweighted average over a region of the range of the ADC. This in turn desensitizes it to the width of any givenchannel.[8] [9]

ADC structuresThese are the most common ways of implementing an electronic ADC: A direct conversion ADC or flash ADC has a bank of comparators sampling the input signal in parallel, each

firing for their decoded voltage range. The comparator bank feeds a logic circuit that generates a code for eachvoltage range. Direct conversion is very fast, capable of gigahertz sampling rates, but usually has only 8 bits ofresolution or fewer, since the number of comparators needed, 2N - 1, doubles with each additional bit, requiring alarge expensive circuit. ADCs of this type have a large die size, a high input capacitance, high power dissipation,and are prone to produce glitches on the output (by outputting an out-of-sequence code). Scaling to newersubmicrometre technologies does not help as the device mismatch is the dominant design limitation. They areoften used for video, wideband communications or other fast signals in optical storage.

A successive-approximation ADC uses a comparator to reject ranges of voltages, eventually settling on a final voltage range. Successive approximation works by constantly comparing the input voltage to the output of an

Analog-to-digital converter 8

internal digital to analog converter (DAC, fed by the current value of the approximation) until the bestapproximation is achieved. At each step in this process, a binary value of the approximation is stored in asuccessive approximation register (SAR). The SAR uses a reference voltage (which is the largest signal the ADCis to convert) for comparisons. For example if the input voltage is 60 V and the reference voltage is 100 V, in the1st clock cycle, 60 V is compared to 50 V (the reference, divided by two. This is the voltage at the output of theinternal DAC when the input is a '1' followed by zeros), and the voltage from the comparator is positive (or '1')(because 60 V is greater than 50 V). At this point the first binary digit (MSB) is set to a '1'. In the 2nd clock cyclethe input voltage is compared to 75 V (being halfway between 100 and 50 V: This is the output of the internalDAC when its input is '11' followed by zeros) because 60 V is less than 75 V, the comparator output is nownegative (or '0'). The second binary digit is therefore set to a '0'. In the 3rd clock cycle, the input voltage iscompared with 62.5 V (halfway between 50 V and 75 V: This is the output of the internal DAC when its input is'101' followed by zeros). The output of the comparator is negative or '0' (because 60 V is less than 62.5 V) so thethird binary digit is set to a 0. The fourth clock cycle similarly results in the fourth digit being a '1' (60 V is greaterthan 56.25 V, the DAC output for '1001' followed by zeros). The result of this would be in the binary form 1001.This is also called bit-weighting conversion, and is similar to a binary search. The analogue value is rounded tothe nearest binary value below, meaning this converter type is mid-rise (see above). Because the approximationsare successive (not simultaneous), the conversion takes one clock-cycle for each bit of resolution desired. Theclock frequency must be equal to the sampling frequency multiplied by the number of bits of resolution desired.For example, to sample audio at 44.1kHz with 32 bit resolution, a clock frequency of over 1.4MHz would berequired. ADCs of this type have good resolutions and quite wide ranges. They are more complex than some otherdesigns.

A ramp-compare ADC produces a saw-tooth signal that ramps up or down then quickly returns to zero. Whenthe ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and thetimer's value is recorded. Timed ramp converters require the least number of transistors. The ramp time issensitive to temperature because the circuit generating the ramp is often just some simple oscillator. There are twosolutions: use a clocked counter driving a DAC and then use the comparator to preserve the counter's value, orcalibrate the timed ramp. A special advantage of the ramp-compare system is that comparing a second signal justrequires another comparator, and another register to store the voltage value. A very simple (non-linear)ramp-converter can be implemented with a microcontroller and one resistor and capacitor.[10] Vice versa, a filledcapacitor can be taken from an integrator, time-to-amplitude converter, phase detector, sample and hold circuit, orpeak and hold circuit and discharged. This has the advantage that a slow comparator cannot be disturbed by fastinput changes.

The Wilkinson ADC was designed by D. H. Wilkinson in 1950. The Wilkinson ADC is based on the comparisonof an input voltage with that produced by a charging capacitor. The capacitor is allowed to charge until its voltageis equal to the amplitude of the input pulse. (A comparator determines when this condition has been reached.)Then, the capacitor is allowed to discharge linearly, which produces a ramp voltage. At the point when thecapacitor begins to discharge, a gate pulse is initiated. The gate pulse remains on until the capacitor is completelydischarged. Thus the duration of the gate pulse is directly proportional to the amplitude of the input pulse. Thisgate pulse operates a linear gate which receives pulses from a high-frequency oscillator clock. While the gate isopen, a discrete number of clock pulses pass through the linear gate and are counted by the address register. Thetime the linear gate is open is proportional to the amplitude of the input pulse, thus the number of clock pulsesrecorded in the address register is proportional also. Alternatively, the charging of the capacitor could bemonitored, rather than the discharge.[11] [12]

An integrating ADC (also dual-slope or multi-slope ADC) applies the unknown input voltage to the input of an integrator and allows the voltage to ramp for a fixed time period (the run-up period). Then a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero (the run-down period). The input voltage is computed as a function of the reference voltage, the constant

Analog-to-digital converter 9

run-up time period, and the measured run-down time period. The run-down time measurement is usually made inunits of the converter's clock, so longer integration times allow for higher resolutions. Likewise, the speed of theconverter can be improved by sacrificing resolution. Converters of this type (or variations on the concept) areused in most digital voltmeters for their linearity and flexibility.

A delta-encoded ADC or Counter-ramp has an up-down counter that feeds a digital to analog converter (DAC).The input signal and the DAC both go to a comparator. The comparator controls the counter. The circuit usesnegative feedback from the comparator to adjust the counter until the DAC's output is close enough to the inputsignal. The number is read from the counter. Delta converters have very wide ranges, and high resolution, but theconversion time is dependent on the input signal level, though it will always have a guaranteed worst-case. Deltaconverters are often very good choices to read real-world signals. Most signals from physical systems do notchange abruptly. Some converters combine the delta and successive approximation approaches; this worksespecially well when high frequencies are known to be small in magnitude.

A pipeline ADC (also called subranging quantizer) uses two or more steps of subranging. First, a coarseconversion is done. In a second step, the difference to the input signal is determined with a digital to analogconverter (DAC). This difference is then converted finer, and the results are combined in a last step. This can beconsidered a refinement of the successive approximation ADC wherein the feedback reference signal consists ofthe interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significantbit. By combining the merits of the successive approximation and flash ADCs this type is fast, has a highresolution, and only requires a small die size.

A Sigma-Delta ADC (also known as a Delta-Sigma ADC) oversamples the desired signal by a large factor andfilters the desired signal band. Generally, a smaller number of bits than required are converted using a Flash ADCafter the filter. The resulting signal, along with the error generated by the discrete levels of the Flash, is fed backand subtracted from the input to the filter. This negative feedback has the effect of noise shaping the error due tothe Flash so that it does not appear in the desired signal frequencies. A digital filter (decimation filter) follows theADC which reduces the sampling rate, filters off unwanted noise signal and increases the resolution of the output(sigma-delta modulation, also called delta-sigma modulation).

A Time-interleaved ADC uses M parallel ADCs where each ADC sample data every M:th cycle of the effectivesample clock. The result is that the sample rate is increased M times compared to what each individual ADC canmanage. In practice, the individual differences between the M ADCs degrade the overall performance reducingthe SFDR. However, technologies exist to correct for these time-interleaving mismatch errors.

An ADC with intermediate FM stage first uses a voltage-to-frequency converter to converts the desired signalinto an oscillating signal with a frequency proportional to the voltage of the desired signal, and then uses afrequency counter to convert that frequency into a digital count proportional to the desired signal voltage. Longerintegration times allow for higher resolutions. Likewise, the speed of the converter can be improved by sacrificingresolution. The two parts of the ADC may be widely separated, with the frequency signal passed through aopto-isolator or transmitted wirelessly. Some such ADCs use sine wave or square wave frequency modulation;others use pulse-frequency modulation. Such ADCs were once the most popular way to show a digital display ofthe status of a remote analog sensor.[13] [14] [15] [16] [17]

There can be other ADCs that use a combination of electronics and other technologies: A Time-stretch analog-to-digital converter (TS-ADC) digitizes a very wide bandwidth analog signal, that

cannot be digitized by a conventional electronic ADC, by time-stretching the signal prior to digitization. It commonly uses a photonic preprocessor frontend to time-stretch the signal, which effectively slows the signal down in time and compresses its bandwidth. As a result, an electronic backend ADC, that would have been too slow to capture the original signal, can now capture this slowed down signal. For continuous capture of the signal, the frontend also divides the signal into multiple segments in addition to time-stretching. Each segment is individually digitized by a separate electronic ADC. Finally, a digital signal processor rearranges the samples and

Analog-to-digital converter 10

removes any distortions added by the frontend to yield the binary data that is the digital representation of theoriginal analog signal.

Commercial analog-to-digital convertersThese are usually integrated circuits.Most converters sample with 6 to 24 bits of resolution, and produce fewer than 1 megasample per second. Thermalnoise generated by passive components such as resistors masks the measurement when higher resolution is desired.For audio applications and in room temperatures, such noise is usually a little less than 1 V (microvolt) of whitenoise. If the Most Significant Bit corresponds to a standard 2 volts of output signal, this translates to a noise-limitedperformance that is less than 20~21 bits, and obviates the need for any dithering. Mega- and gigasample per secondconverters are available, though (Feb 2002). Megasample converters are required in digital video cameras, videocapture cards, and TV tuner cards to convert full-speed analog video to digital video files. Commercial convertersusually have 0.5 to 1.5 LSB error in their output.In many cases the most expensive part of an integrated circuit is the pins, because they make the package larger, andeach pin has to be connected to the integrated circuit's silicon. To save pins, it is common for slow ADCs to sendtheir data one bit at a time over a serial interface to the computer, with the next bit coming out when a clock signalchanges state, say from zero to 5V. This saves quite a few pins on the ADC package, and in many cases, does notmake the overall design any more complex (even microprocessors which use memory-mapped I/O only need a fewbits of a port to implement a serial bus to an ADC).Commercial ADCs often have several inputs that feed the same converter, usually through an analog multiplexer.Different models of ADC may include sample and hold circuits, instrumentation amplifiers or differential inputs,where the quantity measured is the difference between two voltages.

Applications

Application to music recordingADCs are integral to current music reproduction technology. Since much music production is done on computers,when an analog recording is used, an ADC is needed to create the PCM data stream that goes onto a compact disc ordigital music file.The current crop of AD converters utilized in music can sample at rates up to 192 kilohertz. High bandwidthheadroom allows the use of cheaper or faster anti-aliasing filters of less severe filtering slopes. The proponents ofoversampling assert that such shallower anti-aliasing filters produce less deleterious effects on sound quality, exactlybecause of their gentler slopes. Others prefer entirely filterless AD conversion, arguing that aliasing is lessdetrimental to sound perception than pre-conversion brickwall filtering. Considerable literature exists on thesematters, but commercial considerations often play a significant role. Most high-profile recording studios record in24-bit/192-176.4kHz PCM or in DSD formats, and then downsample or decimate the signal for Red-Book CDproduction (44.1kHz or at 48kHz for commonly used for radio/TV broadcast applications).

Analog-to-digital converter 11

Digital Signal ProcessingAD converters are used virtually everywhere where an analog signal has to be processed, stored, or transported indigital form. Fast video ADCs are used, for example, in TV tuner cards. Slow on-chip 8, 10, 12, or 16 bit ADCs arecommon in microcontrollers. Very fast ADCs are needed in digital oscilloscopes, and are crucial for newapplications like software defined radio.

Electrical Symbol

See also Audio converter Beta encoder Digital signal processing Quantization (signal processing) Modem Differential linearity Sample-and-hold amplifier Ideal sampler

Notes[1] although analog-to-digital conversion is an inherently non-linear process (since the mapping of a continuous space to a discrete space is a

piecewise-constant and therefore non-linear operation).[2] Maxim App 800: "Design a Low-Jitter Clock for High-Speed Data Converters" (http:/ / www. maxim-ic. com/ appnotes. cfm/ an_pk/ 800/ )[3] "Jitter effects on Analog to Digital and Digital to Analog Converters" (http:/ / www. troisi. com/ lit/ jitter. PDF)[4] abstract: "The effects of aperture jitter and clock jitter in wideband ADCs" (http:/ / portal. acm. org/ citation. cfm?id=1222361) by Michael

Lhning and Gerhard Fettweis 2007[5] "Understanding the effect of clock jitter on high-speed ADCs" (http:/ / www. analog-europe. com/ 214000770) by Derek Redmayne & Alison

Steer 2008[6] Knoll (1989, p.664665)[7] Nicholson (1974, p.313315)[8] Knoll (1989, p.665666)[9] Nicholson (1974, p.315316)[10] Atmel Application Note AVR400: Low Cost A/D Converter (http:/ / www. atmel. com/ dyn/ resources/ prod_documents/ doc0942. pdf)[11] Knoll (1989, p.663664)[12] Nicholson (1974, p.309310)[13] [www.analog.com/static/imported-files/tutorials/MT-028.pdf Analog Devices MT-028 Tutorial: "Voltage-to-Frequency Converters"] by

Walt Kester and James Bryant 2009, apparently adapted from "Data conversion handbook" (http:/ / books. google. com/books?id=0aeBS6SgtR4C& pg=RA2-PA274& lpg=RA2-PA274& dq="voltage-to-frequency"+ "frequency+ counter"+ adc& source=bl&ots=6yR9U1k51Y& sig=_LuxxY_xE0uw6LwAdI1ubwIKO7M& hl=en& ei=xCWaSpjaDefqnQfu74irBQ& sa=X& oi=book_result&ct=result& resnum=2#v=onepage& q="voltage-to-frequency" "frequency counter" adc& f=false) by Walter Allan Kester 2005, Page 274

[14] [ww1.microchip.com/downloads/en/AppNotes/00795a.pdf Microchip AN795 "Voltage to Frequency / Frequency to Voltage Converter"]page 4: "13-bit A/D converter"

Analog-to-digital converter 12

[15] "Elements of electronic instrumentation and measurement" (http:/ / books. google. com/ books?id=1yBTAAAAMAAJ&q="voltage-to-frequency"+ "frequency+ counter"+ adc& dq="voltage-to-frequency"+ "frequency+ counter"+ adc) by Joseph J. Carr 1996,Page 402

[16] "Voltage-to-Frequency Analog-to-Digital Converters" (http:/ / www. globalspec. com/ reference/ 3127/Voltage-to-Frequency-Analog-to-Digital-Converters)

[17] "Troubleshooting Analog Circuits" (http:/ / books. google. com/ books?id=3kY4-HYLqh0C& pg=PA130& lpg=PA130&dq="voltage-to-frequency"+ adc& source=bl& ots=opOMCo42vk& sig=6Y8ykUT6fJAB0hFOrhVAz2vzXPY& hl=en&ei=bTGaSqXuL9eEngey_YiWCA& sa=X& oi=book_result& ct=result& resnum=2#v=onepage& q="voltage-to-frequency" adc& f=false) byRobert A. Pease 1991 p. 130

References Allen, Phillip E.; Holberg, Douglas R., CMOS Analog Circuit Design, ISBN0-19-511644-5 Kester, Walt, ed. (2005), The Data Conversion Handbook (http:/ / www. analog. com/ library/ analogDialogue/

archives/ 39-06/ data_conversion_handbook. html), Elsevier: Newnes, ISBN0-7506-7841-0 Johns, David; Martin, Ken, Analog Integrated Circuit Design, ISBN0-471-14448-7 Knoll, Glenn F. (1989), Radiation Detection and Measurement (2nd ed.), New York: John Wiley & Sons,

pp.665666 Liu, Mingliang, Demystifying Switched-Capacitor Circuits, ISBN0-7506-7907-7 Nicholson, P. W. (1974), Nuclear Electronics, New York: John Wiley & Sons, pp.315316 Norsworthy, Steven R.; Schreier, Richard; Temes, Gabor C. (1997), Delta-Sigma Data Converters, IEEE Press,

ISBN0-7803-1045-4 Razavi, Behzad (1995), Principles of Data Conversion System Design, New York, NY: IEEE Press,

ISBN0-7803-1093-4 Staller, Len (February 24, 2005), "Understanding analog to digital converter specifications" (http:/ / www.

embedded. com/ showArticle. jhtml?articleID=60403334), Embedded Systems Design Walden, R. H. (1999), "Analog-to-digital converter survey and analysis" (http:/ / ieeexplore. ieee. org/ xpls/

abs_all. jsp?arnumber=761034), IEEE Journal on Selected Areas in Communications 17 (4): 539550,doi:10.1109/49.761034, ISSN0733-8716

External links Counting Type ADC (http:/ / ikalogic. com/ tut_adc. php) A simple tutorial showing how to build your first ADC. An Introduction to Delta Sigma Converters (http:/ / www. beis. de/ Elektronik/ DeltaSigma/ DeltaSigma. html) A

very nice overview of Delta-Sigma converter theory. Digital Dynamic Analysis of A/D Conversion Systems through Evaluation Software based on FFT/DFT Analysis

(http:/ / www. ieee. li/ pdf/ adc_evaluation_rf_expo_east_1987. pdf) RF Expo East, 1987 Which ADC Architecture Is Right for Your Application? (http:/ / www. analog. com/ library/ analogDialogue/

archives/ 39-06/ architecture. html) article by Walt Kester ADC and DAC Glossary (http:/ / www. maxim-ic. com/ appnotes. cfm/ an_pk/ 641/ CMP/ ELK-11) Defines

commonly used technical terms. Signal processing and system aspects of time-interleaved ADCs. (http:/ / www2. spsc. tugraz. at/ people/ cvogel/

TIADC. html)

Flash ADC 13

Flash ADCA Flash ADC (also known as a Direct conversion ADC) is a type of analog-to-digital converter that uses a linearvoltage ladder with a comparator at each "rung" of the ladder to compare the input voltage to successive referencevoltages. Often these reference ladders are constructed of many resistors; however modern implementations showthat capacitive voltage division is also possible. The output of these comparators is generally fed into a digitalencoder which converts the inputs into a binary value (the collected outputs from the comparators can be thought ofas a unary value).

Benefits and drawbacksFlash converters are extremely fast compared to many other types of ADCs which usually narrow in on the "correct"answer over a series of stages. Compared to these, a Flash converter is also quite simple and, apart from the analogcomparators, only requires logic for the final conversion to binary.A Flash converter requires a huge number of comparators compared to other ADCs, especially as the precisionincreases. A Flash converter requires comparators for an n-bit conversion. The size and cost of all thosecomparators makes Flash converters generally impractical for precisions much greater than 8 bits (255 comparators).In place of these comparators, most other ADCs substitute more complex logic which can be scaled more easily forincreased precision.

Implementation

A 2-bit Flash ADC Example Implementation with Bubble Error Correction and DigitalEncoding

Flash ADCs have been implemented inmany technologies, varying fromsilicon based bipolar (BJT) andcomplementary metal oxide FETs(CMOS) technologies to rarely usedIII-V technologies. Often this type ofADC is used as a first medium sizedanalog circuit verification.

The earliest implementations consistedof a reference ladder of well matchedresistors connected to a referencevoltage. Each tap at the resistor ladderis used for one comparator, possiblypreceded by an amplification stage,and thus generates a logical '0' or '1'depending if the measured voltage isabove or below the reference voltageof the resistor tap. The reason to add anamplifier is twofold: it amplifies thevoltage difference and thereforesuppresses the comparator offset, andthe kick-back noise of the comparatortowards the reference ladder is also strongly suppressed. Typically designs from 4-bit up to 6-bit, and sometimes7-bit are produced.

Flash ADC 14

Designs with power-saving capacitive reference ladders have been demonstrated. In addition to clocking thecomparator(s), these systems also sample the reference value on the input stage. As the sampling is done at a veryhigh rate, the leakage of the capacitors is negligible.Recently, offset calibration has been introduced in the flash ADC designs. Instead of properly designing the analogcircuit (which actually means increasing the components sizes to suppress variation) the offset is removed duringuse. A test signal is applied and each the offset of each comparator is calibrated to below the LSB size of the ADC.Due to the heavy calibration effort the design are up to now always limited to 4-bits.Another recent improvement to many flash ADCs is the inclusion of error correction. When the ADC is used toharsh environments or constructed in very small integrated circuit processes, there is a heightened risk of acomparator randomly outputting a wrong code. Bubble error correction is a digital correction mechanism that willprevent a comparator that has tripped high from outputting a high code if it is surrounded by comparators that havenot tripped high.

Folding ADCThe number of comparators can be reduced somewhat by adding a folding circuit in front, making a so called foldingADC. Instead of using the comparators in a Flash ADC only once, during a ramp input signal, the folding ADCre-uses the comparators multiple times. If a m-times folding circuit is used in an n-bit ADC, the actual number ofcomparator can be reduced from to (there is always one needed to detect the range crossover). Typicalfolding circuits are, e.g., the Gilbert multiplier, or analog wired-or circuits.

ApplicationThe very high sample rate of this type of ADC enable Gigahertz applications like radar detection, wide band radioreceivers and optical communication links. More often the flash ADC is embedded in a large IC containing manydigital decoding functions. Also a small flash ADC circuit may be present inside a Delta-sigma modulation loop.

References Analog to Digital Conversion [1]

Understanding Flash ADCs [2]

"Integrated Analog-to-Digital and Digital-to-Analog Converters ", R. van de Plassche, ADCs, Kluwer AcademicPublishers, 1994.

"A Precise Four-Quadrant Multiplier with Subnanosecond Response", Barrie Gilbert, IEEE Journal of Solid-StateCircuits, Vol. 3, No. 4 (1968), pp. 365-373

References[1] http:/ / hyperphysics. phy-astr. gsu. edu/ hbase/ electronic/ adc. html#c4[2] http:/ / www. maxim-ic. com/ appnotes. cfm/ appnote_number/ 810/ CMP/ WP-17

Successive approximation ADC 15

Successive approximation ADCA successive approximation ADC is a type of analog-to-digital converter that converts a continuous analogwaveform into a discrete digital representation via a binary search through all possible quantization levels beforefinally converging upon a digital output for each conversion.

Block diagram

Successive Approximation ADC Block Diagram

Key

DAC = digital-to-analog converter EOC = end of conversion SAR = successive approximation register S/H = sample and hold circuit Vin = input voltage Vref = reference voltage

Algorithm

The successive approximation Analog todigital converter circuit typically consists offour chief subcircuits:

1. A sample and hold circuit to acquirethe input voltage (Vin).

2. An analog voltage comparator thatcompares Vin to the output of theinternal DAC and outputs the result of the comparison to the successive approximation register (SAR).

3. A successive approximation register subcircuit designed to supply an approximate digital code of Vin to theinternal DAC.

4. An internal reference DAC that supplies the comparator with an analog voltage equivalent of the digital codeoutput of the SAR for comparison with Vin.

The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. Thiscode is fed into the DAC, which then supplies the analog equivalent of this digital code (Vref/2) into the comparatorcircuit for comparison with the sampled input voltage. If this analog voltage exceeds Vin the comparator causes theSAR to reset this bit; otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuingthis binary search until every bit in the SAR has been tested. The resulting code is the digital approximation of thesampled input voltage and is finally output by the DAC at the end of the conversion (EOC).Mathematically, let Vin = xVref, so x in [-1, 1] is the normalized input voltage. The objective is to approximatelydigitize x to an accuracy of 1/2n. The algorithm proceeds as follows:

1. Initial approximation x0 = 0.2. ith approximation xi = xi-1 - s(xi-1 - x)/2

i.where, s(x) is the signum-function(sgn(x)) (+1 for x 0, -1 for x < 0). It follows using mathematical induction that|xn - x| 1/2

n.As shown in the above algorithm, a SAR ADC requires:

1. An input voltage source Vin.2. A reference voltage source Vref to normalize the input.

Successive approximation ADC 16

3. A DAC to convert the ith approximation xi to a voltage.4. A Comparator to perform the function s(xi - x) by comparing the DAC's voltage with the input voltage.5. A Register to store the output of the comparator and apply xi-1 - s(xi-1 - x)/2

i.

Charge-Redistribution Successive Approximation ADC

Charge Scaling DAC

One of the most common implementationsof the successive approximation ADC, thecharge-redistribution successiveapproximation ADC, uses a charge scalingDAC. The charge scaling DAC simplyconsists of an array of individually switchedbinary-weighted capacitors. The amount ofcharge upon each capacitor in the array isused to perform the aforementioned binarysearch in conjunction with a comparatorinternal to the DAC and the successiveapproximation register.

The DAC conversion is performed in four basic steps.1. First, the capacitor array is completely discharged to the offset voltage of the comparator, VOS. This step

provides automatic offset cancellation(i.e. The offset voltage represents nothing but dead charge which can't bejuggled by the capacitors).

2. Next, all of the capacitors within the array are switched to the input signal, vIN. The capacitors now have acharge equal to their respective capacitance times the input voltage minus the offset voltage upon each ofthem.

3. In the third step, the capacitors are then switched so that this charge is applied across the comparator's input,creating a comparator input voltage equal to -vIN.

4. Finally, the actual conversion process proceeds. First, the MSB capacitor is switched to VREF, whichcorresponds to the full-scale range of the ADC. Due to the binary-weighting of the array the MSB capacitorforms a 1:1 divided between it and the rest of the array. Thus, the input voltage to the comparator is now -vINplus VREF/2. Subsequently, if vIN is greater than VREF/2 then the comparator outputs a digital 1 as the MSB,otherwise it outputs a digital 0 as the MSB. Each capacitor is tested in the same manner until the comparatorinput voltage converges to the offset voltage, or at least as close as possible given the resolution of the DAC.

3 bits simulation of a capacitive ADC

Split Capacitor Array

it is used to convert analog to digital signals i.e it is an A/D Converter

See also

Quantization noise Digital-to-Analog Converter

Successive approximation ADC 17

References R. J. Baker, CMOS Circuit Design, Layout, and Simulation, Third Edition, Wiley-IEEE, 2010. ISBN

978-0-470-88132-3

External links Understanding SAR ADCs [1]

References[1] http:/ / www. maxim-ic. com/ appnotes. cfm/ appnote_number/ 1080/ CMP/ WP-50

Integrating ADCAn integrating ADC is a type of analog-to-digital converter that converts an unknown input voltage into a digitalrepresentation through the use of an integrator. In its most basic implementation, the unknown input voltage isapplied to the input of the integrator and allowed to ramp for a fixed time period (the run-up period). Then a knownreference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator outputreturns to zero (the run-down period). The input voltage is computed as a function of the reference voltage, theconstant run-up time period, and the measured run-down time period. The run-down time measurement is usuallymade in units of the converter's clock, so longer integration times allow for higher resolutions. Likewise, the speed ofthe converter can be improved by sacrificing resolution.Converters of this type (or variations on the concept) are able to achieve high resolutions (8.5 digits, or 28 bits, in thecase of the Agilent 3458A digital multimeter), but often do so at the expense of speed. The Agilent 3458A, forexample, only achieves its highest resolution at a rate of six samples per second. For this reason, these converters arenot found in audio or signal processing applications. Their use is typically limited to digital voltmeters and otherinstruments requiring highly accurate measurements.

Basic Design

Basic integrator of a Dual-slope Integrating ADC.The comparator, the timer, and the controller are

not shown.

The basic integrating ADC circuit consists of an integrator, a switch toselect between the voltage to be measured and the reference voltage, atimer that determines how long to integrate the unknown and measureshow long the reference integration took, a comparator to detect zerocrossing, and a controller. Depending on the implementation, a switchmay also be present in parallel with the integrator capacitor to allowthe integrator to be reset (by discharging the integrator capacitor). Theswitches will be controlled electrically by means of the converter'scontroller (a microprocessor or dedicated control logic). Inputs to thecontroller include a clock (used to measure time) and the output of a comparator used to detect when the integrator'soutput reaches zero.The conversion takes place in two phases: the run-up phase, where the input to the integrator is the voltage to bemeasured, and the run-down phase, where the input to the integrator is a known reference voltage. During the run-upphase, the switch selects the measured voltage as the input to the integrator. The integrator is allowed to ramp for afixed period of time to allow a charge to build on the integrator capacitor. During the run-down phase, the switchselects the reference voltage as the input to the integrator. The time that it takes for the integrator's output to return tozero is measured during this phase.

Integrating ADC 18

In order for the reference voltage to ramp the integrator voltage down, the reference voltage needs to have a polarityopposite to that of the input voltage. In most cases, for positive input voltages, this means that the reference voltagewill be negative. To handle both positive and negative input voltages, a positive and negative reference voltage isrequired. The selection of which reference to use during the run-down phase would be based on the polarity of theintegrator output at the end of the run-up phase. That is, if the integrator's output were negative at the end of therun-up phase, a negative reference voltage would be required. If the integrator's output were positive, a positivereference voltage would be required.

Integrator output voltage in a basic dual-slopeintegrating ADC

The basic equation for the output of the integrator (assuming a constantinput) is:

Assuming that the initial integrator voltage at the start of each conversion is zero and that the integrator voltage atthe end of the run down period will be zero, we have the following two equations that cover the integrator's outputduring the two phases of the conversion:

The two equations can be combined and solved for , the unknown input voltage:

From the equation, one of the benefits of the dual-slope integrating ADC becomes apparent: the measurement isindependent of the values of the circuit elements (R and C). This does not mean, however, that the values of R and Care unimportant in the design of a dual-slope integrating ADC (as will be explained below).Note that in the graph to the right, the voltage is shown as going up during the run-up phase and down during therun-down phase. In reality, because the integrator uses the op-amp in a negative feedback configuration, applying apositive will cause the output of the integrator to go down. The up and down more accurately refer to theprocess of adding charge to the integrator capacitor during the run-up phase and removing charge during therun-down phase.The resolution of the dual-slope integrating ADC is determined primarily by the length of the run-down period andby the time measurement resolution (i.e., the frequency of the controller's clock). The required resolution (in numberof bits) dictates the minimum length of the run-down period for a full-scale input ( ):

During the measurement of a full-scale input, the slope of the integrator's output will be the same during the run-upand run-down phases. This also implies that the time of the run-up period and run-down period will be equal (

) and that the total measurement time will be . Therefore, the total measurement time for a full-scaleinput will be based on the desired resolution and the frequency of the controller's clock:

Integrating ADC 19

If a resolution of 16 bits is required with a controller clock of 10MHz, the measurement time will be 13.1milliseconds (or a sampling rate of just 76 samples per second). However, the sampling time can be improved bysacrificing resolution. If the resolution requirement is reduced to 10 bits, the measurement time is also reduced toonly 0.2 milliseconds (almost 4900 samples per second).

LimitationsThere are limits to the maximum resolution of the dual-slope integrating ADC. It is not possible to increase theresolution of the basic dual-slope ADC to arbitrarily high values by using longer measurement times or faster clocks.Resolution is limited by: The range of the integrating amplifier. The voltage rails on an op-amp limit the output voltage of the integrator.

An input left connected to the integrator for too long will eventually cause the op amp to limit its output to somemaximum value, making any calculation based on the run-down time meaningless. The integrator's resistor andcapacitor are therefore chosen carefully based on the voltage rails of the op-amp, the reference voltage andexpected full-scale input, and the longest run-up time needed to achieve the desired resolution.

The accuracy of the comparator used as the null detector. Wideband circuit noise limits the ability of thecomparator to identify exactly when the output of the integrator has reached zero. Goerke suggests a typical limitis a comparator resolution of 1 millivolt.[1]

The quality of the integrator's capacitor. Although the integrating capacitor need not be perfectly linear, it doesneed to be time-invariant. Dielectric absorption causes errors.[2]

EnhancementsThe basic design of the dual-slope integrating ADC has a limitations in both conversion speed and resolution. Anumber of modifications to the basic design have been made to overcome both of these to some degree.

Run-up improvements

Enhanced dual-slope

Enhanced run-up dual-slope integrating ADC

The run-up phase of the basic dual-slope design integrates the inputvoltage for a fixed period of time. That is, it allows an unknownamount of charge to build up on the integrator's capacitor. Therun-down phase is then used to measure this unknown charge todetermine the unknown voltage. For a full-scale input, half of themeasurement time is spent in the run-up phase. For smaller inputs, aneven larger percentage of the total measurement time is spent in therun-up phase. Reducing the amount of time spent in the run-up phasecan significantly reduce the total measurement time.A simple way to reduce the run-up time is to increase the rate thatcharge accumulates on the integrator capacitor by reducing the size ofthe resistor used on the input, a method referred to as enhanced dual-slope. This still allows the same total amount ofcharge accumulation, but it does so over a smaller period of time. Using the same algorithm for the run-down phaseresults in the following equation for the calculation of the unknown input voltage ( ):

Integrating ADC 20

Note that this equation, unlike the equation for the basic dual-slope converter, has a dependence on the values of theintegrator resistors. Or, more importantly, it has a dependence on the ratio of the two resistance values. Thismodification does nothing to improve the resolution of the converter (since it doesn't address either of the resolutionlimitations noted above).

Multi-slope run-up

Circuit diagram for a multi-slope run-upconverter

One method to improve the resolution of the converter is to artificiallyincrease the range of the integrating amplifier during the run-up phase.As mentioned above, the purpose of the run-up phase is to add anunknown amount of charge to the integrator to be later measuredduring the run-down phase. Having the ability to add larger quantitiesof charge allows for more higher-resolution measurements. Forexample, assume that we are capable of measuring the charge on theintegrator during the run-down phase to a granularity of 1 coulomb. Ifour integrator amplifier limits us to being able to add only up to 16 coulombs of charge to the integrator during therun-up phase, our total measurement will be limited to 4 bits (16 possible values). If we can increase the range of theintegrator to allow us to add up to 32 coulombs, our measurement resolution is increased to 5 bits.One method to increase the integrator capacity is by periodically adding or subtracting known quantities of chargeduring the run-up phase in order to keep the integrator's output within the range of the integrator amplifier. Then, thetotal amount of artificially-accumulated charge is the charge introduced by the unknown input voltage plus the sumof the known charges that were added or subtracted.The circuit diagram shown to the right is an example of how multi-slope run-up could be implemented. The conceptis that the unknown input voltage, , is always applied to the integrator. Positive and negative reference voltagescontrolled by the two independent switches add and subtract charge as needed to keep the output of the integratorwithin its limits. The reference resistors, and are necessarily smaller than to ensure that the referencescan overcome the charge introduced by the input. A comparator is connected to the output to compare the integrator'svoltage with a threshold voltage. The output of the comparator is used by the converter's controller to decide whichreference voltage should be applied. This can be a relatively simple algorithm: if the integrator's output above thethreshold, enable the positive reference (to cause the output to go down); if the integrator's output is below thethreshold, enable the negative reference (to cause the output to go up). The controller keeps track of how often eachswitch is turned on in order to estimate how much additional charge was placed onto (or removed from) theintegrator capacitor as a result of the reference voltages.

Output from multi-slope run-up

To the right is a graph of sample output from the integrator during amulti-slope run-up. Each dashed vertical line represents a decisionpoint by the controller where it samples the polarity of the output andchooses to apply either the positive or negative reference voltage to theinput. Ideally, the output voltage of the integrator at the end of therun-up period can be represented by the following equation:

where is the sampling period, is the number of periods in which the positive reference is switched in, is the number of periods in which the negative reference is switched in, and is the total number of periods in the

Integrating ADC 21

run-up phase.The resolution obtained during the run-up period can be determined by making the assumption that the integratoroutput at the end of the run-up phase is zero. This allows us to relate the unknown input, , to just the referencesand the values:

The resolution can be expressed in terms of the difference between single steps of the converter's output. In this case,if we solve the above equation for using and (the sum of and must always equal ), the difference will equal the smallest resolvable quantity. This results in anequation for the resolution of the multi-slope run-up phase (in bits) of:

Using typical values of the reference resistors and of 10k ohms and an input resistor of 50k ohms, we canachieve a 16 bit resolution during the run-up phase with 655360 periods (65.5 milliseconds with a 10MHz clock).While it is possible to continue the multi-slope run-up indefinitely, it is not possible to increase the resolution of theconverter to arbitrarily high levels just by using a longer run-up time. Error is introduced into the multi-slope run-upthrough the action of the switches controlling the references, cross-coupling between the switches, unintended switchcharge injection, mismatches in the references, and timing errors.[3]

Some of this error can be reduced by careful operation of the switches.[4] In particular, during the run-up period, eachswitch should be activated a constant number of times. The algorithm explained above does not do this and justtoggles switches as needed to keep the integrator output within the limits. Activating each switch a constant numberof times makes the error related to switching approximately constant. Any output offset that is a result of theswitching error can be measured and then subtracted from the result.

Run-down improvements

Multi-slope run-down

Multi-slope run-down integrating ADC

The simple, single-slope run-down is slow. Typically, the run downtime is measured in clock ticks, so to get four digit resolution, therundown time may take as long as 10,000 clock cycles. A multi-sloperun-down can speed the measurement up without sacrificing accuracy.By using 4 slope rates that are each a power of ten more gradual thanthe previous, four digit resolution can be achieved in roughly 40 orfewer clock ticksa huge speed improvement.[1]

The circuit shown to the right is an example of a multi-slope run-down circuit with four run-down slopes with eachbeing ten times more gradual than the previous. The switches control which slope is selected. The switch containing

selects the steepest slope (i.e., will cause the integrator output to move toward zero the fastest). At thestart of the run-down interval, the unknown input is removed from the circuit by opening the switch connected to

and closing the switch. Once the integrator's output reaches zero (and the run-down time measured),the switch is opened and the next slope is selected by closing the switch. This repeats until thefinal slope of has reached zero. The combination of the run-down times for each of the slopes determines thevalue of the unknown input. In essence, each slope adds one digit of resolution to the result.In the example circuit, the slope resistors differ by a factor of 10. This value, known as the base ( ), can be anyvalue. As explained below, the choice of the base affects the speed of the converter and determines the number ofslopes needed to achieve the desired resolution.

Integrating ADC 22

Output of the multi-slope run-down integratingADC

The basis of this design is the assumption that there will always beovershoot when trying to find the zero crossing at the end of arun-down interval. This will necessarily be true given any hysteresis inthe output of the comparator measuring the zero crossing and due tothe periodic sampling of the comparator based on the converter's clock.If we assume that the converter switches from one slope to the next ina single clock cycle (which may or may not be possible), the maximumamount of overshoot for a given slope would be the largest integratoroutput change in one clock period:

To overcome this overshoot, the next slope would require no more than clock cycles, which helps to place abound on the total time of the run-down. The time for the first-run down (using the steepest slope) is dependent onthe unknown input (i.e., the amount of charge placed on the integrator capacitor during the run-up phase). At most,this will be:

where is the maximum number of clock periods for the first slope, is the maximum integrator voltageat the start of the run-down phase, and is the resistor used for the first slope.The remainder of the slopes have a limited duration based on the selected base, so the remaining time of theconversion (in converter clock periods) is:

where is the number of slopes.Converting the measured time intervals during the multi-slope run-down into a measured voltage is similar to thecharge-balancing method used in the multi-slope run-up enhancement. Each slope adds or subtracts known amountsof charge to/from the integrator capacitor. The run-up will have added some unknown amount of charge to theintegrator. Then, during the run-down, the first slope subtracts a large amount of charge, the second slope adds asmaller amount of charge, etc. with each subsequent slope moving a smaller amount in the opposite direction of theprevious slope with the goal of reaching closer and closer to zero. Each slope adds or subtracts a quantity of chargeproportional to the slope's resistor and the duration of the slope:

is necessarily an integer and will be less than or equal to for the second and subsequent slopes. Using thecircuit above as an example, the second slope, , can contribute the following charge, , to theintegrator:

in steps of

That is, possible values with the largest equal to the first slope's smallest step, or one (base 10) digit of resolutionper slope. Generalizing this, we can represent the number of slopes, , in terms of the base and the requiredresolution, :

Substituting this back into the equation representing the run-down time required for the second and subsequentslopes gives us this:

Integrating ADC 23

Which, when evaluated, shows that the minimum run-down time can be achieved using a base of e. This base may bedifficult to use both in terms of complexity in the calculation of the result and of finding an appropriate resistornetwork, so a base of 2 or 4 would be more common.

Residue ADC

When using run-up enhancements like the multi-slope run-up, where a portion of the converter's resolution isresolved during the run-up phase, it is possible to eliminate the run-down phase altogether by using a second type ofanalog-to-digital converter.[5] At the end of the run-up phase of a multi-slope run-up conversion, there will still be anunknown amount of charge remaining on the integrator's capacitor. Instead of using a traditional run-down phase todetermine this unknown charge, the unknown voltage can be converted directly by a second converter and combinedwith the result from the run-up phase to determine the unknown input voltage.Assuming that multi-slope run-up as described above is being used, the unknown input voltage can be related to themulti-slope run-up counters, and , and the measured integrator output voltage, using the followingequation (derived from the multi-slope run-up output equation):

This equation represents the theoretical calculation of the input voltage assuming ideal components. Since theequation depends on nearly all of the circuit's parameters, any variances in reference currents, the integratorcapacitor, or other values will introduce errors in the result. A calibration factor is typically included in the term to account for measured errors (or, as described in the referenced patent, to convert the residue ADC's outputinto the units of the run-up counters).Instead of being used to eliminate the run-down phase completely, the residue ADC can also be used to make therun-down phase more accurate than would otherwise be possible.[6] With a traditional run-down phase, the run-downtime measurement period ends with the integrator output crossing through zero volts. There is a certain amount oferror involved in detecting the zero crossing using a comparator (one of the short-comings of the basic dual-slopedesign as explained above). By using the residue ADC to rapidly sample the integrator output (synchronized with theconverter controller's clock, for example), a voltage reading can be taken both immediately before and immediatelyafter the zero crossing (as measured with a comparator). As the slope of the integrator voltage is constant during therun-down phase, the two voltage measurements can be used as inputs to an interpolation function that moreaccurately determines the time of the zero-crossing (i.e., with a much higher resolution than the controller's clockalone would allow).

Other improvements

Continuously-integrating Converter

By combining some of these enhancements to the basic dual-slope design (namely multi-slope run-up and theresidue ADC), it is possible to construct an integrating analog-to-digital converter that is capable of operatingcontinuously without the need for a run-down interval.[7] Conceptually, the multi-slope run-up algorithm is allowedto operate continuously. To start a conversion, two things happen simultaneously: the residue ADC is used tomeasure the approximate charge currently on the integrator capacitor and the counters monitoring the multi-sloperun-up are reset. At the end of a conversion period, another residue ADC reading is taken and the values of themulti-slope run-up counters are noted.The unknown input is calculated using a similar equation as used for the residue ADC, except that two output voltages are included ( representing the measured integrator voltage at the start of the conversion, and

Integrating ADC 24

representing the measured integrator voltage at the end of the conversion.

Such a continuously-integrating converter is very similar to a delta-sigma analog-to-digital converter.

CalibrationIn most variants of the dual-slope integrating converter, the converter's performance is dependent on one or more ofthe circuit parameters. In the case of the basic design, the output of the converter is in terms of the reference voltage.In more advanced designs, there are also dependencies on one or more resistors used in the circuit or on theintegrator capacitor being used. In all cases, even using expensive precision components there may be other effectsthat are not accounted for in the general dual-slope equations (dielectric effect on the capacitor or frequency ortemperature dependencies on any of the components). Any of these variations result in error in the output of theconverter. In the best case, this is simply gain and/or offset error. In the worst case, nonlinearity or nonmonotonicitycould result.Some calibration can be performed internal to the converter (i.e., not requiring any special external input). This typeof calibration would be performed every time the converter is turned on, periodically while the converter is running,or only when a special calibration mode is entered. Another type of calibration requires external inputs of knownquantities (e.g., voltage standards or precision resistance references) and would typically be performed infrequently(every year for equipment used in normal conditions, more often when being used in metrology applications).Of these types of error, offset error is the simplest to correct (assuming that there is a constant offset over the entirerange of the converter). This is often done internal to the converter itself by periodically taking measurements of theground potential. Ideally, measuring the ground should always result in a zero output. Any non-zero output indicatesthe offset error in the converter. That is, if the measurement of ground resulted in an output of 0.001 volts, one canassume that all measurements will be offset by the same amount and can subtract 0.001 from all subsequent results.Gain error can similarly be measured and corrected internally (again assuming that there is a constant gain error overthe entire output range). The voltage reference (or some voltage derived directly from the reference) can be used asthe input to the converter. If the assumption is made that the voltage reference is accurate (to within the tolerances ofthe converter) or that the voltage reference has been externally calibrated against a voltage standard, any error in themeasurement would be a gain error in the converter. If, for example, the measurement of a converter's 5 voltreference resulted in an output of 5.3 volts (after accounting for any offset error), a gain multiplier of 0.94 (5 / 5.3)can be applied to any subsequent measurement results.

Footnotes[1] Goeke, HP Journal, page 9[2] Hewlett-Packard Catalog, 1981, page 49, stating, "For small inputs, noise becomes a problem and for large inputs, the dielectric absorption of

the capacitor becomes a problem."[3] Eng 1994[4] Eng 1994, Goeke 1989[5] Riedel 1992[6] Regier 2001[7] Goeke 1992

Integrating ADC 25

References US 5231403 (http:/ / v3. espacenet. com/ textdoc?DB=EPODOC& IDX=US5231403), Eng, Jr., Benjamin & Don

Matson, "Multiple Slope Analog-to-Digital Converter", issued 14 June 1994 Goeke, Wayne (April 1989), "8.5-Digit Integrating Analog-to-Digital Converter with 16-Bit,

100,000-Sample-per-Second Performance" (http:/ / www. hpl. hp. com/ hpjournal/ pdfs/ IssuePDFs/ 1989-04.pdf), HP Journal 40 (2): 815

US 5117227 (http:/ / v3. espacenet. com/ textdoc?DB=EPODOC& IDX=US5117227), Goeke, Wayne,"Continuously-integrating high-resolution analog-to-digital converter", issued 26 May 1992

Kester, Walt, The Data Conversion Handbook (http:/ / www. analog. com/ library/ analogDialogue/ archives/39-06/ data_conversion_handbook. html), ISBN0-7506-7841-0

US 6243034 (http:/ / v3. espacenet. com/ textdoc?DB=EPODOC& IDX=US6243034), Regier, Christopher,"Integrating analog to digital converter with improved resolution", issued 5 June 2001

US 5101206 (http:/ / v3. espacenet. com/ textdoc?DB=EPODOC& IDX=US5101206), Riedel, Ronald,"Integrating analog to digital converter", issued 31 March 1992

Article Sources and Contributors 26

Article Sources and ContributorsAnalog-to-digital converter Source: http://en.wikipedia.org/w/index.php?oldid=409019159 Contributors: 4johnny, A4, Ablewisuk, Adoniscik, Adpete, AeroPsico, Ahoerstemeier, Alansohn,Ali Esfandiari, Alison22, Alll, Altenmann, Alvin Seville, Alvin-cs, Analogkidr, Andres, Anitauky, Arnab1984, Arnero, BernardH, Berrinkursun, Bhimaji, Binksternet, Biscuittin, Blowfishie, BobK, BrianWilloughby, Brianga, Brisvegas, CambridgeBayWeather, CanisRufus, Cat5nap, ChardonnayNimeque, Charles Matthews, Chepry, Chetvorno, Chris the speller, Christian way, Cindy141,ClickRick, Cmdrjameson, Colin Marquardt, Coppertwig, Crohnie, Csk, Cullen kasunic, Cutler, D4g0thur, DJS, Da monster under your bed, Damian Yerrick, David Underdown, DavidCary,Davidkazuhiro, Dayewalker, DeadTotoro, Derek Ross, Dhiraj1984, Drpickem, Ellmist, EncMstr, Erislover, EthanL, Everyking, Evice, FakingNovember, Febert, Fmltavares, GRAHAMUK,Garion96, Gbalasandeep, Gene Nygaard, Giftlite, Gilliam, Ginsengbomb, Glrx, GyroMagician, Hadal, Haikupoet, Heddmj, Hellisp, Heron, History2007, Hooperbloob, Hu12, Iverson2, Ivnryn,Ixfd64, J.delanoy, Jaho, Jan1nad, Jaxl, Jeff3000, Jerome Charles Potts, Jheiv, Jkominek, Jleedev, JohnTechnologist, Johnteslade, JonHarder, Josecampos, Jusdafax, Juxo, Kaleem str, Keegan,Klo, KnowledgeOfSelf, Kooo, Krishfeelmylove, Kvng, LeaveSleaves, Legend Saber, LilHelpa, LittleOldMe, MER-C, MR7526, Male1979, Materialscientist, Mbell, Mcleodm, Mecanismo,Meggar, Michael Hardy, Micru, MinorContributor, Mortense, MrOllie, Msadaghd, Nacho Insular, Nbarth, Neil.steiner, Nelbs, Nemilar, Nick C, Night Goblin, Nsaa, Nwerneck, Ojigiri, Oli Filth,Omegatron, Overmanic, Pavan206, Peteraisher, Pietrow, Pjacobi, Purgatory Fubar, Qllach, Qz, Redheylin, Reinderien, Requestion, Ring0, RobinK, Romanski, Roscoe x, STHayden,Sandpiper800, SapnaArun, Satan131984, Saxbryn, Sbeath, Schickaneder, Sciurin, Scottr9, Shaddack, Shadowjams, Shalabh24, Shawn81, Sicaspi, Sjbfalchion, Smurfettekla, Snoyes, Sonett72,Southcaltree, Spinningspark, Steven Zhang, Stigwall, Talkstosocks, Tbackstr, TecABC, Techeditor1, Teh tennisman, Theo177, Theslaw, Thue, Tjwikipedia, Travelingseth, Tristanb, Tslocum,UkPaolo, Vayalir, VoidLurker, Welsh, Wernher, Whiteflye, Wiki libs, Wikihitech, Wolfkeeper, Wsmarz, Wtshymanski, Xorx, Yyy, Zipcube, Zueignung, 427 anonymous edits

Flash ADC Source: http://en.wikipedia.org/w/index.php?oldid=403438135 Contributors: Bmearns, Bwpach, ChardonnayNimeque, ELLAPRISCI, Etphonehome, Guerberj, Iridescent,Jim.henderson, JohnI, Overjive, Sharoneditha, Sherool, SlipperyHippo, Wsmarz, 16 anonymous edits

Successive approximation ADC Source: http://en.wikipedia.org/w/index.php?oldid=404455356 Contributors: Amalas, B Pete, Biscuittin, Btyner, Ec5618, Etphonehome, Eus Kevin, Firebat08,Jeff3000, Nolelover, Oli Filth, Omar El-Sewefy, Pjrm, Salvar, Tabletop, Whiteflye, 47 anonymous edits

Integrating ADC Source: http://en.wikipedia.org/w/index.php?oldid=406023201 Contributors: Bender235, Bootsup, ElPeste, Glrx, Iamchanged, Scottr9, 3 anonymous edits

Image Sources, Licenses and Contributors 27

Image Sources, Licenses and ContributorsFile:WM WM8775SEDS-AB.jpg Source: http://en.wikipedia.org/w/index.php?title=File:WM_WM8775SEDS-AB.jpg License: Creative Commons Attribution-Sharealike 3.0 Contributors:Chepry, Clusternote, Glenn, Jaho, MMuzammilsFile:ADC voltage resolution.svg Source: http://en.wikipedia.org/w/index.php?title=File:ADC_voltage_resolution.svg License: Creative Commons Attribution-Sharealike 3.0 Contributors:User:SpinningsparkFile:ADC voltage resolution mid-tread.svg Source: http://en.wikipedia.org/w/index.php?title=File:ADC_voltage_resolution_mid-tread.svg License: Creative Commons Attribution-Sharealike3.0 Contributors: User:SpinningsparkFile:ADC voltage resolution mid-tread2.svg Source: http://en.wikipedia.org/w/index.php?title=File:ADC_voltage_resolution_mid-tread2.svg License: Creative CommonsAttribution-Sharealike 3.0 Contributors: User:SpinningsparkFile:ADC Symbol.jpg Source: http://en.wikipedia.org/w/index.php?title=File:ADC_Symbol.jpg License: Public Domain Contributors: User:TjwikcomFile:Flash_ADC.png Source: http://en.wikipedia.org/w/index.php?title=File:Flash_ADC.png License: Creative Commons Attribution 3.0 Contributors: Jon GuerberImage:SA ADC block diagram.png Source: http://en.wikipedia.org/w/index.php?title=File:SA_ADC_block_diagram.png License: Creative Commons Attribution-Sharealike 2.5 Contributors:White FlyeImage:ChargeScalingDAC.png Source: http://en.wikipedia.org/w/index.php?title=File:ChargeScalingDAC.png License: Creative Commons Attribution-Sharealike 2.5 Contributors: WhiteFlyeFile:CAPadc.png Source: http://en.wikipedia.org/w/index.php?title=File:CAPadc.png License: Public Domain Contributors: User:GonzaljImage:basic integrating adc.svg Source: http://en.wikipedia.org/w/index.php?title=File:Basic_integrating_adc.svg License: Public Domain Contributors: Scottr9Image:dual slope integrator graph.svg Source: http://en.wikipedia.org/w/index.php?title=File:Dual_slope_integrator_graph.svg License: Public Domain Contributors: Original uploader wasScottr9 at en.wikipediaImage:enhanced runup dual slope.svg Source: http://en.wikipedia.org/w/index.php?title=File:Enhanced_runup_dual_slope.svg License: Public Domain Contributors: Scottr9Image:multislope runup.svg Source: http://en.wikipedia.org/w/index.php?title=File:Multislope_runup.svg License: Public Domain Contributors: Scottr9Image:multislope runup integrator graph.svg Source: http://en.wikipedia.org/w/index.php?title=File:Multislope_runup_integrator_graph.svg License: Public Domain Contributors: Scottr9Image:multislope rundown.svg Source: http://en.wikipedia.org/w/index.php?title=File:Multislope_rundown.svg License: Public Domain Contributors: Scottr9Image:multislope rundown graph.svg Source: http://en.wikipedia.org/w/index.php?title=File:Multislope_rundown_graph.svg License: Public Domain Contributors: Scottr9

License 28

LicenseCreative Commons Attribution-Share Alike 3.0 Unportedhttp:/ / creativecommons. org/ licenses/ by-sa/ 3. 0/

ContentsAnalog-to-digital converterConceptsResolutionResponse typeAccuracySampling rateAliasingDitherOversamplingRelative speed and precisionThe sliding scale principle

ADC structuresCommercial analog-to-digital convertersApplicationsElectrical SymbolSee alsoNotesReferencesExternal links

Flash ADCBenefits and drawbacksImplementationFolding ADCApplicationReferences

Successive approximation ADCBlock diagramAlgorithmCharge-Redistribution Successive Approximation ADCSee alsoReferencesExternal links

Integrating ADCBasic DesignLimitations

EnhancementsRun-up improvementsRun-down improvementsOther improvements

CalibrationFootnotesReferences

Article Sources and ContributorsImage Sources, Licenses and ContributorsLicense