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Partitions and Partial Reconfiguration
IRI FrankfurtNorbert Abel, Christian Stüllein, Udo Kebschull
History
Page 2Norbert Abel & Christian Stüllein, IRI Frankfurt
ISE 1 ISE 2 ISE 3 ISE 4 ISE 5
ISE 6 ISE 7 ISE 8 ISE 9
ISE 10 ISE 11
ISE 12 ISE 13
No PR at all
PREApatch
New approach based on Partitions& official support
Motivation
Page 3
Black, Donovan, Bunton, Keist„SystemC: From the Ground Up“
Norbert Abel & Christian Stüllein, IRI Frankfurt
Motivation
Page 4
● High Level Synthesis
● Team Design
● Hierarchical Design & Re-Use
Norbert Abel & Christian Stüllein, IRI Frankfurt
Partitions
Page 5
Partitions are Xilinx's approach to Team Design and Hierarchical DesignTool: PlanAhead
Norbert Abel & Christian Stüllein, IRI Frankfurt
RTL Project
Page 6Norbert Abel & Christian Stüllein, IRI Frankfurt
RTL Project
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RTL Project
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clkbufds: ibufgds port map (O=>clk, I=>clk_p, IB=>clk_n); team1_inst: team1 port map (clk=>clk, led=>led1);
team2_inst: team2 port map (clk=>clk, led=>led2);
Norbert Abel & Christian Stüllein, IRI Frankfurt
RTL Project
Page 9
process (clk) begin if rising_edge(clk) then c <= c + 1; end if; end process;
led(3 downto 0) <= c (31 downto 28);
Norbert Abel & Christian Stüllein, IRI Frankfurt
RTL Project
Page 10
process (clk) begin if rising_edge(clk) then c(31 downto 0) <= c(30 downto 0) & c(31); end if; end process;
led(3 downto 0) <= c (31 downto 28);
Norbert Abel & Christian Stüllein, IRI Frankfurt
RTL Project
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RTL Project
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RTL Project
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RTL Project
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RTL Project
Page 15Norbert Abel & Christian Stüllein, IRI Frankfurt
RTL Project
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RTL Project
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RTL Project
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RTL Project
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3 Levels of Design Preservation:● Synthesis● Placement● Routing
Norbert Abel & Christian Stüllein, IRI Frankfurt
NGC Project
Page 20Norbert Abel & Christian Stüllein, IRI Frankfurt
NGC Project
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Differences to the RTL Project:
Sources: NGC files (netlists)==> Requires external synthesis
top.ngc
team1.ngc team2.ngc
general Synthesis hints:- deactivate automatically generated I/O buffers- instantiate all I/O buffers directly
Instantiates team1 andteam2 as black box
Norbert Abel & Christian Stüllein, IRI Frankfurt
NGC Project
Page 22
Differences to the RTL Project:
3 Levels of Design Preservation:● Synthesis (same as Implement)● Placement● Routing
Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 23
Requires a specialPR-License
No patches neededany longer!
Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 24
PR designs are NGC designs
Sources: NGC files (netlists)==> Requires external synthesis
top.ngc
recoModule1.ngc recoModule2.ngc
general Synthesis hints:- deactivate automatically generated I/O buffers- instantiate all I/O buffers directly
Instantiates subcomponentsas black boxes
staticModule.ngc
no BUFGs, PLLs,DCMs, etc. allowed
Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 25Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 26Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 27Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 28Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 29Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 30Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 31Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 32Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
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Partial Reconfiguration
Page 34Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 35Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 36Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 37Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 38Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 39Norbert Abel & Christian Stüllein, IRI Frankfurt
!!
Partial Reconfiguration
Page 40Norbert Abel & Christian Stüllein, IRI Frankfurt
FPGA
staticModule
recoModule1
recoModule2
proxy logic (LUT1)
Partial Reconfiguration
Page 41Norbert Abel & Christian Stüllein, IRI Frankfurt
Partial Reconfiguration
Page 42Norbert Abel & Christian Stüllein, IRI Frankfurt
Conclusion
Page 43Norbert Abel & Christian Stüllein, IRI Frankfurt
FPGA
staticModule
recoModule1
recoModule2
proxy logic (LUT1)
Problems:● Timing● change of static Module causes rebuild of all Modules
● a Areas using m Modules => m configurations => m full implementation runs => m full bitfiles => a • m partial bitfiles● no support of Spartan-6
Our aims:● clear Timing● strict module separation● movable bitfiles
Questions?
Page 44Norbert Abel & Christian Stüllein, IRI Frankfurt
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