Lecture 9: Sequential Networks: Implementation CSE 140: Components and Design Techniques for Digital...

Lecture 9:

Sequential Networks: Implementation

CSE 140: Components and Design Techniques for Digital Systems

Fall 2014

CK Cheng

Dept. of Computer Science and Engineering

University of California, San Diego1

Implementation

• Format and Tool

• Procedure

• Excitation Tables

• Example

2

3

Mealy Machine: yi(t) = fi(X(t), S(t))Moore Machine: yi(t) = fi(S(t))

si(t+1) = gi(X(t), S(t))

C1 C2

CLK

x(t)

y(t)

Mealy Machine

C1 C2

CLK

x(t) y(t)

Moore Machine

S(t) S(t)

Canonical Form: Mealy and Moore Machines

D

iClicker

4

y

CLK

xQ

In the logic diagram below, a D flip-flop has input x and output y.A: x= Q(t), y=Q(t)B: x=Q(t+1), y=Q(t)C: x=Q(t), y=Q(t+1)D: None of the above

Understanding Current State and Next State in a sequential circuit

5

today

sunrise

Preparing for tomorrow according to our effort in today

C1 C2

CLK

x(t)

y(t)

Implementation Format

Q(t)

Q(t+1) = h(x(t), Q(t)) Circuit C1 y(t) = f(x(t), Q(t)) Circuit C2

6

Canonical Form: Mealy & Moore machinesState Table Netlist

Tool: Excitation Table

Implementation Tool: Excitation Table

7

x(t)

Q(t)

CLK

C1C1

id x(t) Q(t) Q(t+1)

0 0 0 1

1 1 1 0

2 0 0 1

3 1 1 0

State Table

Find D, T, (S R), (J K) to drive F-Fs

Implementation Tool: Excitation Table

8

x(t)

Q(t)

CLK

Q(t)

C1C1id x(t) Q(t) T(t) Q(t+1)

0 0 0 1 1

1 1 1 1 0

2 0 1 0 1

3 1 1 1 0

id x(t) Q(t) Q(t+1)

0 0 0 1

1 1 1 0

2 0 1 1

3 1 1 0

State Table

Excitation Table

Example with T flip flop

T(t)

Implementation Tool: Excitation Table

9

x(t)

Q(t)

CLK

Q(t)

C1C1id x(t) Q(t) T(t) Q(t+1)

0 0 0 1 1

1 1 1 1 0

2 0 1 0 1

3 1 1 1 0

Excitation Table

Implement combinational logic C1D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t))

Implementation: ProcedureState Table => Excitation Table

Problem: Given a state table, we haveNS: Q(t+1) = h(x(t),Q(t))

We find D, T, (S R), (J K) to drive F-Fs from Q(t) to Q(t+1).

Excitation Table: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to driveQ(t) to Q(t+1).

We implement combinational logic C1D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t)).

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Implementation: ProcedureState Table => Excitation Table

Problem: Given a state table, we haveNS: Q(t+1) = h(x(t),Q(t))

We find D, T, (S R), (J K) to drive F-Fs from Q(t) to Q(t+1).

Excitation Table: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to driveQ(t) to Q(t+1).

We implement combinational logic C1D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t)).

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Implementation: ProcedureF-F State Table <=> F-F Excitation Table

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DTSRJKPS

Q(t)NS Q(t+1)

NS Q(t+1) PS

Q(t)DTSRJK

State table of JK F-F:

00 0 1

01 0 0

10 1 1

11 1 0

01Q(t) Q(t+1)

JK

Excitation table of JK F-F:

00--1

11--0

01

PSNS

Q(t)

Q(t+1)

JK

If Q(t) is 1, and Q(t+1) is 0, then JK needs to be -1.

Excitation Table

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Excitation Tables and State Tables

00-01

110-0

01

PSNS

Q(t)

Q(t+1)SR

Excitation Tables:

0 0 1

1 1 0

01

PSNS

Q(t)

Q(t+1)T

00 0 1

01 0 0

01

PSSR

Q(t)Q(t+1)

SR 10 1 1

11 - -

0 0 1

1 1 0

01

PST

Q(t)Q(t+1)

T

State Tables:

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00--1

11--0

01

PSNS

Q(t)

Q(t+1)JK

Excitation Tables:

0 0 0

1 1 1

01

PSNS

Q(t)

Q(t+1)D

00 0 1

01 0 0

01

PSJK

Q(t)Q(t+1)

JK 10 1 1

11 1 0

0 0 0

1 1 1

01

PSD

Q(t)Q(t+1)

D

State Tables:

Excitation Tables and State Tables

15

Implementation: Procedure1. State table: y(t)= f(Q(t), x(t)), Q(t+1)= h(x(t),Q(t))2. Excitation table of F-Fs:

• D(t)= eD(Q(t+1), Q(t)); • T(t)= eT(Q(t+1), Q(t)); • (S, R), or (J, K)

3. From 1 & 2, we derive excitation table of the system• D(t)= gD(x(t),Q(t))= eD(h(x(t),Q(t)),Q(t)); • T(t)= gT(x(t),Q(t))= eT(h(x(t),Q(t)),Q(t));• (S, R) or (J, K).

4. Use K-map to derive optional combinational logic implementation.• D(t)= gD(x(t),Q(t)) • T(t)= gT(x(t),Q(t))• y(t)= f(x(t),Q(t)) 16

Implementation: ExampleImplement a JK F-F with a T F-F

00 0 1

01 0 0

01

PSJK

Q(t)

Q(t+1) = h(J(t),K(t),Q(t)) = J(t)Q’(t)+K’(t)Q(t)

JK 10 1 1

11 1 0

Implement a JK F-F:

Q

Q’

C1

J

K T

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Q

id 01234567

J(t) 0 0 0 0 1 1 1 1

K(t) 0 0 1 1 0 0 1 1

Q(t) 0 1 0 1 0 1 0 1

Q(t+1) 0 1 0 0 1 1 1 0

T(t) 0 0 0 1 1 0 1 1

0 0 1

1 1 0

01

PSNS

Q(t)

Q(t+1)

Excitation Table of T Flip-Flop T(t) = Q(t) ⊕ Q(t+1)

T(t) = Q(t) XOR ( J(t)Q’(t) + K’(t)Q(t))

Excitation Table of the Design

Example: Implement a JK flip-flop using a T flip-flop

T

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0 2 6 4

1 3 7 5

Q(t)

J

0 0 1 1

0 1 1 0

KT(J,K,Q):

T = K(t)Q(t) + J(t)Q’(t)

Q

Q’

J

K

T

Example: Implement a JK flip-flop using a T flip-flop

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iClicker

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Given a flip-flop, the relation of its state table and excitation table isA.One to oneB.One to manyC.Many to oneD.Many to manyE.None of the above

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Let’s implement our free running 2-bit counter using T-flip flops

S0

S1

S2

S3

PS Next state

S1 S2 S3 S0

State Table

S0S0

S1S1

S2S2

S3S3

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Let’s implement our free running 2-bit counter using T-flip flops

S0

S1

S2

S3

S1 S2 S3 S0

State Table

S0S0

S1S1

S2S2

S3S3

State Table with AssignedEncoding

0 0 0 11 01 1

Current

01101100

Next

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Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1)

0 0 0 0 1

1 0 1 1 0

2 1 0 1 1

3 1 1 0 0

Excitation table

24

Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1)

0 0 0 0 1 0 1

1 0 1 1 1 1 0

2 1 0 0 1 1 1

3 1 1 1 1 0 0

Excitation table

25

Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1)

0 0 0 0 1 0 1

1 0 1 1 1 1 0

2 1 0 0 1 1 1

3 1 1 1 1 0 0

Excitation table

T0(t) = T1(t) =

Q0(t+1) = T0(t) Q’0(t)+T’0(t)Q0(t)Q1(t+1) = T1(t) Q’1(t)+T’1(t)Q1(t)

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Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1)

0 0 0 0 1 0 1

1 0 1 1 1 1 0

2 1 0 0 1 1 1

3 1 1 1 1 0 0

Excitation table

T0(t) = 1 T1(t) = Q0(t)

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TQ

Q’

TQ

Q’

Q0

Q1

1

T1

Free running counter with T flip flops

T0(t) = 1 T1(t) = Q0(t)

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Implementation: State Diagram => State Table => Netlist

Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.

Assign mapping a:0, b:1

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Implementation: State Diagram => State Table => Netlist

Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.

Assign mapping a:0, b:1

PI Q How many states should the pattern recognizer haveA.One because it has one outputB.One because it has one inputC.Two because the input can be one of two states (a or b)D.Three because . .. . . . .E.Four because . . . . .

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PI Q: How many states should the pattern recognizer haveA.One because it has one outputB.One because it has one inputC.Two because the input can be one of two states (a or b)D.Three because . .. . . . .E.Four because . . . . .

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Implementation: State Diagram => State Table => Netlist

Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.

S1S0a/0

b/0

a/0

b/1

S2a/0

b/0

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State Diagram => State Table with State Assignment

State AssignmentS0: 00S1: 01S2: 10

PS\x a b

S0 S1,0 S0,0

S1 S2,0 S0,0

S2 S2,0 S0,1

PS\x 0 1

00 01,0 00,0

01 10,0 00,0

10 10,0 00,1

Q1(t+1)Q0(t+1), ya: 0b: 1

S1S0a/0

b/0

a/0

b/1

S2a/0

b/0

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Example 2: State Diagram => State Table => Excitation Table => Netlist

PS\x 0 1

00 01,0 00,0

01 10,0 00,0

10 10,0 00,1

id Q1Q0x D1D0 y

0 000 01 0

1 001 00 0

2 010 10 0

3 011 00 0

4 100 10 0

5 101 00 1

6 110 -- -

7 111 -- -

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0 2 6 4

1 3 7 5

x(t)

Q1

0 1 - 1

0 0 - 0

Q0D1(t):

D1(t) = x’Q0 + x’Q1

D0 (t)= Q’1Q’0 x’y= Q1x

id Q1Q0x D1D0 y

0 000 01 0

1 001 00 0

2 010 10 0

3 011 00 0

4 100 10 0

5 101 00 1

6 110 -- -

7 111 -- -

Example 2: State Diagram => State Table => Excitation Table => Netlist

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DQ

Q’

DQ

Q’

Q1

Q0

D1

D0

Q0

Q1

x’

D1(t) = x’Q0 + x’Q1

D0 (t)= Q’1Q’0 x’y= Q1x

x

y

Q’1

Q’0x’

Example 2: State Diagram => State Table => Excitation Table => Netlist

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DQ

Q’

DQ

Q’

Q1

Q0

D1

D0

Q0Q1

x’

x

y

Q’1

Q’0x’

Example 3: State Diagram => State Table => Excitation Table => Netlist

S1S0 a/0b/0

a/0

b/1

S2a/0

b/0

iClicker: The relation between the above state diagram and sequential circuit.A.One to one.B.One to manyC.Many to oneD.Many to manyE.None of the above

Modified 2 bit counter

37

Q0(t)

Q1(t)

DQ

Q’

DQ

Q’

CLK

x(t)

Q0(t)

Q1(t) y(t)

Modified 2 bit counter

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Q0(t)

Q1(t)

DQ

Q’

DQ

Q’

CLK

x(t)

Q0(t)

Q1(t)

y(t)

y(t) = Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)’ Q0(t)’Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))

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State table

0 0 0 11 01 1

PSinput

x=0 x=1

Q1(t) Q0(t) | (Q1(t+1) Q0(t+1), y(t))Present State | Next State, Output

S0

S1

S2

S3

PSinput

x=0 x=1

Netlist State Table State Diagram Input Output Relation

State Assignment

Characteristic Expression:

y(t) = Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)’ Q0(t)’Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))

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State table

0 0 0 11 01 1

PSinput

x=0 x=1

01, 0 00, 010, 0 00, 011, 0 00, 000, 1 00, 1

Q1(t) Q0(t) | Q1(t+1) Q0(t+1), y(t)Present State | Next State, Output

S0

S1

S2

S3

PSinput

x=0 x=1

S1, 0 S0, 0S2, 0 S0, 0S3, 0 S0, 0S0, 1 S0, 1

Let:S0 = 00S1 = 01S2 = 10S3 = 11

Remake the state table using symbols instead of binary code , e.g. ’00’

Netlist State Table State Diagram Input Output Relation

State Assignment

y(t) = Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)’ Q0(t)’Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))

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Netlist State Table State Diagram Input Output Relation

Given inputs and initial state, derive output sequence

S1 S2 S3S0

Time 0 1 2 3 4 5

Input 0 1 0 0 0 -

State S0

Output

S0

S1

S2

S3

PSinput

x=0 x=1

S1, 0 S0, 0S2, 0 S0, 0S3, 0 S0, 0S0, 1 S0, 1

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Netlist State Table State Diagram Input Output Relation

Example: Given inputs and initial state, derive output sequence

Time 0 1 2 3 4 5

Input 0 1 0 0 0 -

State S0 S1 S0 S1 S2 S3

Output 0 0 0 0 0 1

(0 or 1)/1

S0

S1

S2

S3

PSinput

x=0 x=1

S1, 0 S0, 0S2, 0 S0, 0S3, 0 S0, 0S0, 1 S0, 1

x/y

S1 S2 S3S00/0 0/00/0

1/0

1/0 1/0

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Finite State Machine Example

• Traffic light controller– Traffic sensors: TA, TB (TRUE when there’s traffic)

– Lights: LA, LB

TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.B

rava

do

Blv

d.

Dorms

Fields

DiningHall

Labs

44

FSM Black Box

• Inputs: CLK, Reset, TA, TB

• Outputs: LA, LB

TA

TB

LA

LB

CLK

Reset

TrafficLight

Controller

45

FSM State Transition Diagram

• Moore FSM: outputs labeled in each state• States: Circles• Transitions: Arcs

S0LA: greenLB: red

Reset

46

FSM State Transition Diagram

• Moore FSM: outputs labeled in each state• States: Circles• Transitions: Arcs

S0LA: greenLB: red

S1LA: yellowLB: red

S3LA: redLB: yellow

S2LA: redLB: green

TATA

TB

TB

Reset

47

FSM State Transition Table

PS Inputs NS

TA TB

S0 0 X S1

S0 1 X S0

S1 X X S2

S2 X 0 S3

S2 X 1 S2

S3 X X S0

48

State Transition TablePS Inputs NS

Q1(t) Q0(t) TA TB Q1(t +1) Q0(t +1)

0 0 0 X 0 1

0 0 1 X 0 0

0 1 X X 1 0

1 0 X 0 1 1

1 0 X 1 1 0

1 1 X X 0 0

State Encoding

S0 00

S1 01

S2 10

S3 11

Q1(t+1)= Q1(t) Q0(t)

Q0(t+1)= Q’1(t)Q’0(t)T’A + Q1(t)Q’0(t)T’B

49

FSM Output TablePS Outputs

Q1 Q0 LA1 LA0 LB1 LB0

0 0 0 0 1 0

0 1 0 1 1 0

1 0 1 0 0 0

1 1 1 0 0 1

Output Encoding

green 00

yellow 01

red 10

LA1 = Q1

LA0 = Q’1Q0

LB1 = Q’1

LB0 = Q1Q0

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FSM Schematic: State Register

S1

S0

S'1

S'0

CLK

state register

Reset

r

51

Logic Diagram

S1

S0

S'1

S'0

CLK

next state logic state register

Reset

TA

TB

inputs

S1 S0

r

52

FSM Schematic: Output Logic

S1

S0

S'1

S'0

CLK

next state logic output logicstate register

Reset

LA1

LB1

LB0

LA0

TA

TB

inputs outputs

S1 S0

r

Summary: Implementation

53

• Set up canonical form • Mealy or Moore machine

• Identify the next states • state diagram ⇨ state table • state assignment

• Derive excitation table• Inputs of flip flops

• Design the combinational logic• don’t care set utilization