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News on production at IZM / Twente. Yevgen Bilevych. CERN 22.02.2012. Main technological steps for the formation of structure TimePix chip or dummy substrate / spacer / Al grid. 1. Formation of protection layer. - PowerPoint PPT Presentation

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News on production at IZM / Twente

Yevgen Bilevych

CERN 22.02.2012

Main technological steps for the formation of structureTimePix chip or dummy substrate / spacer / Al grid

4. Formation of “support” / grid

1. Formation of protection layer

2. Deposition of spacer material

3. Deposition of Al thin film

Main technological steps for the formation of GemGrid structure

4. Dry etching of BCB

Chip

1. Aluminum deposition (bottom electrode)

2. Deposition of BCB

3. Formation of Al grid

Chip

GemGrid IZM, Berlin and University of Bonn

200 mm silicon dummy wafer

Main technological steps for the formation of structureTimePix chip / SiO2 or SU-8 / Al grid

4. Dry wet etching of SiO2

or wet etching of SU-8

Chip

1. Formation of SixNy layer

2. Deposition of SiO2 or SU-8

3. Formation of Al grid

GemGrid NIKHEF and University of Twente

TimePix single chip

SiO2

SU-8

Main technological steps for the formation of structureTimePix wafer / SU-8 pillar / Al grid

5. Development of SU-8

Chip

1. Formation of SixNy protection layer

2. Deposition of SU-8

3. Pillars-like structure formation

4. Formation of Al grid

InGrid University of Bonn, IZM Berlin, NIKHEF and University of Twente

200 mm TimePix wafer

before

now

Main problems:- formation of protection layer

- deposition of Al- final development of SU-8

Polyimide mask

Microsystems HD 4100 polyimide - negative tone, solvent developed, photodefinable polyimide

Steps:• Spinning• Baking• Exposition• Development• Silicon nitride deposition• Chemical activation of polyimide• Stripping

Advantage:• Silicon technology compatible

• Perfect alignment• No residuals

Disadvantage:• Temperature sensitive process

• Time consuming process• mechanical scratching of bonding pads

deposition of Al layer

Sputtering system Leybold Z660

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25x x x x x x x x x x x x x x x x x x x x x x

DC 50%, no sputter etching, 30 sec – the deposition time for every sputtering run, + cooling delay

Total thickness: ~ 800 nm

Development of SU-8

1. Acetone2. Acetone:IPA:H2O (1:1:2)3. Acetone:IPA:H2O (1:1:1)4. Acetone:IPA (1:1)5. Microstrip 60016. H2O7. IPA8. Acetone9. Drying in the air

1. 200 mm TimePix wafer / SixNy / SU-8 pillars / Al grid - yield of high quality InGrids about 70%

2. Single TimePix chip / SixNy / SiO2 (hole) / Al grid

3. Single TimePix chip / SixNy / SU-8 (hole) / Al grid

4. 200 mm silicon wafer / BCB (hole) / Al grid

Conclusion