On Timing- Independent False Path Identification Feng Yuan, Qiang Xu Cuhk Reliable Computing Lab,...

On Timing-Independent False Path IdentificationFeng Yuan, Qiang XuCuhk Reliable Computing Lab,The Chinese University of Hong KongICCAD 2010

Outline Introduction Preliminaries False Path Examination Method Experimental Results & Conclusion

Outline Introduction Preliminaries False Path Examination Method Experimental Results & Conclusion

Introduction False Path

The test vector which cannot propagate in function mode.

Used in STA of timing-driven placement. In manufacturing testing is unnecessary

and may cause over-testing. Optimization does not help to improve the

performance of the circuit.

Introduction (cont.) Kinds of False Path

Timing-don’t-care false paths Path in async. clock domain crossovers

Timing-independent false paths Logically unsensitizable in function mode

Delay-dependent false paths Logically sensitizable but dominated by one

or more side-input signals all the time

Outline Introduction Preliminaries False Path Examination Method Experimental Results & Conclusion

Illegal State Identification Previous Work[12]

False Path caused by Illegal State If a path is activated only with illegal states in

the circuit, this path is a false path.

Outline Introduction Preliminaries False Path Examination Method Experimental Results & Conclusion

Controlling Signal

0

x0

1

xx

1

x1

0

xx

Criterion A path is a timing-independent false

path iff there exist at least one on-path signal such that when it is a non-controlling value, one or more of its corresponding side-input signals are with controlling values in function mode.

Meet some illegal state?

Criterion (cont.) A path is not a timing-independent false

path iff there any on-path signal such that when it is a non-controlling value, one or more of its corresponding side-input signals are with non-controlling values in function mode.

Path Sensitizaton Given a path P, to determine whether it

is a timing-independent false path. Propagate logic ‘0’and ‘1’ at launch point.

Proposed Examination Procedure Phantom logic AND gate

Use AND gates and inverters to represent the illegal states.

Set output of AND gates to be logic ‘0’

Outline Introduction Preliminaries False Path Examination Method Experimental Results & Conclusion

Find False Path The number of false paths is exponential

to circuit size. Find the root cause structures

Prime False path segment

Static Implication Learning Consider illegal state: {FF0(1), FF2(1)}

Conduct implication for the inverse values of FF0(0), FF2(0) independently

FF0(0)=>B(0)=>G(0) FF2(0)=>A(0)=>C(1)

=>D(0)=>F(1)

Use counter-positive low

Suspicious Node Extraction Suspicious Node

Starting point of S-Frontier All the possible false segments can be

detect. The selected points are as less as possible.

Affect Node The nodes have implications after Static

Implication Learning. Not all the affect nodes need to consider

as the starting points.

S-Frontier Propagation Do a BFS process to launch nodes with

0(1) Created at each suspicious node Launch 0(1) and propagate to new node Add the implication and check if meet the

illegal state. Check the starting point

is already in existing falsepath segment to avoidfinding the same segment.

Outline Introduction Preliminaries False Path Examination Method Experimental Results & Conclusion

Experiment Results Benchmark

ISCAS’89 IWLS 2005

Environment 2GHz PC 1GB memory

Competitor [5] Fast Identification of Untestable Delay

Faults Using Implications

Experiment Results (cont.) Use PrimeTime to fetch 5000 critical

paths Worse Case Delay(WCD)

Report the true critical paths delay

Experiment Results (cont.) Use academic ATPG tool Atalanta [7]

Check whether we can find a solution to activate them.

Conclusion Develop novel false path identification

techniques by taking illegal states in the circuit into consideration.

The proposed solution find much more false paths than existing FPI techniques.