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SEQUENTIAL CIRCUITSIntroduction
Overview
Circuits require memory to store intermediate data
Sequential circuits use a periodic signal to determine when to store values. A clock signal can determine storage times Clock signals are periodic
Single bit storage element is a flip flop A basic type of flip flop is a latch Latches are made from logic gates
NAND, NOR, AND, OR, Inverter
The story so far ...
Logical operations which respond to combinations of inputs to produce an output. Call these combinational logic circuits. Usually these circuits do not contain loops However, some combinational circuits have loops:
The story so far ...
Combinational circuits No way of remembering or storing information
after inputs have been removed. To handle this, we need sequential logic
capable of storing intermediate (and final) results.
Sequential CircuitsCombinational
circuitFlip Flops
OutputsInputs
Nextstate Present
state
Timing signal (clock)
Clocka periodic external event (input)
Clocka periodic external event (input)
synchronizes when current state changes happen
keeps system well-behavedmakes it easier to design and build large
systems
synchronizes when current state changes happen
keeps system well-behavedmakes it easier to design and build large
systems
Cross-coupled Inverters
0
1
1
0
State 1 State 2
The system has two stable states A stable value can be stored at
inverter outputs Not possible to set a desired state
Cross-coupled Inverters (cont.)
• This circuit has no stable states
Y X Z
XZ
ZY
YX
XXZYX
Time0
X
Y
Z
'1'
'0'
2 3 6 754 8 9 10 11
S-R Latch with NORs
1 11 00 10 0
S R Q Q’
0 1
1 0 Set
1 0Stable
0 1 Reset
0 0 Forbidden
R (reset)
Q
Q
S (set)
S-R latch made from cross-coupled NORs If Q = 1, set state If Q = 0, reset state
Usually S=0 and R=0 S=1 and R=1 generates unpredictable
results
reset
set S
R
Q
Q
S-R Latch with NORs
1 11 00 10 0
S R Q Q’
0 1
1 0 Set
1 0Stable
0 1 Reset
0 0 Forbidden
R (reset)
Q
Q
S (set)
S
R
Q
Q
tpd
S-R Latch with NORs
1 11 00 10 0
S R Q Q’
0 1
1 0 Set
1 0Stable
0 1 Reset
0 0 Forbidden
R (reset)
Q
Q
S (set)
What happens if both inputs R and S simultaneously change from 0 to 1?
Race conditions
S-R Latch with NANDs
S
R
Q
Q’
0 00 11 01 1
S R Q Q’
0 1
1 0 Set
1 0 Store
0 1 Reset
1 1 Forbidden
Latch made from cross-coupled NANDsSometimes called S’-R’ latchUsually S=1 and R=1S=0 and R=0 generates unpredictable results
S-R Latches
Latch operation Latch operation enabled byenabled by
CC
Latch operation Latch operation enabled byenabled by
CC
Input sampling
enabled by gatesInput sampling
enabled by gates
NOR S-R Latch with Control Input
R’
S’Q’
Q
C’
Outputs change Outputs change when C is low:when C is low:RESET and SETRESET and SET
Otherwise: HOLDOtherwise: HOLD
Outputs change Outputs change when C is low:when C is low:RESET and SETRESET and SET
Otherwise: HOLDOtherwise: HOLD
Latch is Latch is level-sensitivelevel-sensitive, in regards to C, in regards to CLatch is Latch is level-sensitivelevel-sensitive, in regards to C, in regards to C
Only stores data if C’ = 0Only stores data if C’ = 0
S-R Latch with control input
Occasionally, desirable to avoid latch changesC = 0 disables all latch state changesControl signal enables data change when C = 1Right side of circuit same as ordinary S-R latch.
D Latch
Q
Q’
C
D S
R
X
Y
X Y C Q Q’
0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset1 0 1 1 0 Set1 1 1 1 1 DisallowedX X 0 Q0 Q0’ Store
0 1 0 11 1 1 0X 0 Q0 Q0’
D C Q Q’
Q0 indicates the previous state (the previously stored value)
D Latch
Q
Q’
C
D S
R
X
Y
0 1 0 11 1 1 0X 0 Q0 Q0’
D C Q Q’
Input value D is passed to output Q when C is highInput value D is ignored when C is low
D Latch
E
x
Latches on following edge of clock
E
D Q
C
x
z
z
Z only changes when E is highIf E is high, Z will follow X
D Latch
E
x
Latches on following edge of clock
E
D Q
C
x
z
z
The D latch stores data indefinitely, regardless of input D values, if C = 0
Forms basic storage element in computers
Enabling Signal
E
D Q
C
x
z
Complete the waveform
D
G
Q
E
D Q
C
x
z
Complete the waveform
D
G
Q
Symbols for Latches
SR latch is based on NOR gatesS’R’ latch based on NAND gatesD latch can be based on either.D latch sometimes called transparent latch
Notes Latches are based on combinational gates (e.g. NAND,
NOR) Latches store data even after data input has been
removed S-R latches operate like cross-coupled inverters with
control inputs (S = set, R = reset) With additional gates, an S-R latch can be converted to a
D latch (D stands for data) D latch is simple to understand conceptually
When C = 1, data input D stored in latch and output as Q When C = 0, data input D ignored and previous latch value
output at Q Next time: more storage elements!
Why FFs Latches respond to trigger levels on control inputs
Example: If G = 1, input reflected at output Difficult to precisely time when to store data with latches Flip flips store data on a rising or falling trigger edge.
Example: control input transitions from 0 -> 1, data input appears at output
Data remains stable in the flip flop until until next rising edge. Different types of flip flops serve different functions Flip flops can be defined with characteristic functions.
Disadvantage of Transparent Latches
Difficult to implement a shift register!
D
G
Q D
G
QD
G
Q QD
G
Clocking Event
Lo-HiLo-Hi edgeHi-LoHi-Lo edge
What if the output only changed on a C transition?
C
D Q
Q’
0 0 11 1 0X 0 Q0 Q0’
D C Q Q’
Positive edge triggered
Master-Slave D Flip Flop
Consider two latches combined togetherOnly one C value active at a timeOutput changes on falling edge of the clock
0 1 0 11 1 1 0X 0 Q0 Q0’
D C Q Q’
D Flip-Flop
D gets latched to Q on the rising edge of the clock.
Stores a value on the positive edge of CInput changes at other times have no effect on output
C
D Q
Q’
0 0 11 1 0X 0 Q0 Q0’
D C Q Q’
Positive edge triggered
Clocked D Flip-Flop
Stores a value on the positive edge of CInput changes at other times have no effect on output
Positive and Negative Edge D Flip-FlopD flops can be triggered on positive or negative edgeBubble before Clock (C) input indicates negative edge trigger
Lo-HiLo-Hi edge Hi-LoHi-Lo edge
Positive Edge-Triggered J-K Flip-Flop
0 0 Q0 Q0’ 0 1 0 1 1 0 1 0 1 1 TOGGLE
Q J Q’CLK K Created from D flopJ setsK resetsJ=K=1 -> invert output
Clocked J-K Flip FlopTwo data inputs, J and KJ -> set, K -> reset, if J=K=1 then toggle output
Characteristic Table
Positive Edge-Triggered T Flip-Flop
0 Q0 Q0’ 1 TOGGLE
Q Q’C T Created from D flopT=0 -> keep currentK resetsT=1 -> invert current
Asynchronous Inputs
• J, K are synchronous inputs
o Effects on the output are synchronized with the CLK input.
• Asynchronous inputs operate independently of the synchronous inputs and clock
o Set the FF to 1/0 states at any time.
Asynchronous Inputs
Asynchronous Inputs
• Note reset signal (R) for D flip flop
• If R = 0, the output Q is cleared
•This event can occur at any time, regardless of the value of the CLK
Parallel Data TransferFlip flops store outputs from combinational logicMultiple flops can store a collection of data
Notes
Flip flops are powerful storage elements They can be constructed from gates and latches!
D flip flop is simplest and most widely used Asynchronous inputs allow for clearing and
presetting the flip flop output Multiple flops allow for data storage
The basis of computer memory! Combine storage and logic to make a computation
circuit Next time: Analyzing sequential circuits.
Must know items
Understanding flip flop state: Stored values inside flip flops
Clocked sequential circuits: Contain flip flops
Representations of state: State equations State table State diagram
Finite state machines Mealy machine Moore machine
Flip Flop StateBehavior of clocked sequential circuit can be determined
from inputs, outputs and FF state
y(t) = x(t)Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)Q1(t)Q1(t+1) = D1(t) = x(t) + Q0(t)
x
Q1
Q0
DQ
Q’
DQ
Q’
y
Q0
Q1
D0
D1
Clk
Output and State EquationsNext state dependent on previous state.
State equations
Output equationy(t) = x(t)Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)Q1(t)Q1(t+1) = D1(t) = x(t) + Q0(t)
x
Q1
Q0
DQ
Q’
DQ
Q’
y
Q0
Q1
D0
D1
Clk
State Table Sequence of outputs, inputs, and flip flop
states enumerated in state table Present state indicates current value of flip
flops Next state indicates state after next rising
clock edge Output is output value on current clock edge
0 0 0 11 01 1
Present State
Next State
x=0 x=1
00 10 0 0 10 10 0 000 11 0 010 11 0 1
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
x=0 x=1
Output
State Table
State Table All possible input combinations enumerated All possible state combinations enumerated Separate columns for each output value. Sometimes easier to designate a symbol for
each state.
Present State
Next State
x=0 x=1
s0 s2 0 0 s2 s2 0 0 s0 s3 0 0 s2 s3 0 1
x=0 x=1
Output
s0
s1
s2
s3
Let:s0 = 00s1 = 01s2 = 10s3 = 11
State Diagram Circles indicate current state Arrows point to next state For x/y, x is input and y is output
0 0 0 11 01 1
Present State
Next State
x=0 x=1
00 10 0 0 10 10 0 000 11 0 010 11 0 1
x=0 x=1
Output
01 10000/0 1/0
0/01/0
0/00/0
11
1/1
1/0
State Diagram
s1 s2s0
0/0 1/0
0/01/0
0/00/0
s3
1/1
1/0
Each state has two arrows leavingOne for x = 0 and one for x = 1
Unlimited arrows can enter a stateNote use of state names in this example
Easier to identify
Flip Flop Input Equations
DQ0 = xQ1
DQ1 = x + Q0
Boolean expressions which indicate the input to the flip flops.
Format implies type of flop used
x
Q1
Q0
DQ
Q’
DQ
Q’
y
Q0
Q1
D0
D1
Clk
Analysis with D Flip-FlopsIdentify flip flop input equationsIdentify output equation
Note: this example has no output
Mealy Machine
Comb.Logic
X(t)
Q(t+1)
Q(t)
Y(t)
clk
present state
present input
nextstate
Comb.Logic
• Output based on state and present input
FlipFlops
Moore Machine
Comb.Logic
X(t)
Q(t+1)
Q(t)
Y(t)
clk
present state
present input
nextstate
Comb.Logic
• Output based on state only
FlipFlops
OutputsOutputLogic
Combina-tional
Combina-tional
LogicInput
MemoryElement
Inputs
Mealy Model
OutputsOutputLogic
Combina-tional
Combina-tional
LogicInput
MemoryElement
Inputs
Moore Model
Mealy versus Moore
State Diagram with One Input & One Mealy Output
Mano text focuses on Mealy machines State transitions are shown as a function of inputs
and current outputs.
S1
S2
S3
S4
1/0
1/01/0
1/1
Input(s)/Output(s) shown in transition
0/0
0/0e.g. 1
0/00/0
State Diagram with One Input & a Moore Output
Moore machine: outputs only depend on the current state
Outputs cannot change during a clock pulse if the input variables change
Moore Machines usually have more states. No direct path from inputs to outputs Can be more reliable
Designing Finite State Machines
Specify the problem with words (e.g. Design a circuit that detects three consecutive 1
inputs) Assign binary values to states Develop a state table Use K-maps to simplify expressions
Flip flop input equations and output equations Create appropriate logic diagram
Should include combinational logic and flip flops
Example: Detect 3 Consecutive 1 inputs
State S0 : zero 1s detectedState S1 : one 1 detectedState S2 : two 1s detectedState S3 : three 1s detected
0
Note that each state has 2 output arrowsTwo bits needed to encode state
State Table for Sequence Detector
Sequence of outputs, inputs, and flip flop states enumerated in state table
Present state indicates current value of flip flops
Next state indicates state after next rising clock edge
Output is output value on current clock edge
Present State
Next State
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 00 1 0 0 0 00 1 1 1 0 01 0 0 0 0 0
1 0 1 1 1 01 1 0 0 0 11 1 1 1 1 1
OutputInput
S0 = 00S1 = 01
S2 = 10S3 = 11
Finding Expressions for Next State and Output Value Create K-map directly from state table (3 columns = 3 K-maps) Minimize K-maps to find SOP representations Separate circuit for each next state and output value
Circuit for Consecutive 1s Detector
Note location of state flip flops
Output value (y) is function of state
This is a Moore machine.
Concept of the State MachineExample: Odd Parity Checker
Even [0]
Odd [1]
Reset
0
0
1 1
Assert output whenever input bit stream has odd # of 1's
StateDiagram
Present State Even Even Odd Odd
Input 0 1 0 1
Next State Even Odd Odd Even
Output 0 0 1 1
Symbolic State Transition Table
Output 0 0 1 1
Next State 0 1 1 0
Input 0 1 0 1
Present State 0 0 1 1
Encoded State Transition Table
Note: Present state and output are the same value Moore machine
Concept of the State MachineExample: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
D
R
Q
Q
Input
CLK PS/Output
\Reset
NS
D FF Implementation
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
Clk
Output
Input 1 0 0 1 1 0 1 0 1 1 1 0
1 1 0 1 0 0 1 1 0 1 1 1
Mealy and Moore Machines
Solution 1: (Mealy)
0/0
Even
Odd
1/11/0
0/1
0Even
11
0
Reset[0]
Odd [1]
Output
InputOutput
Input
Transition Arc
Output is dependent only on current state
O/P is dependenton current state andinput in Mealy
Solution 2: (Moore)
Mealy Machine: Output is associated with the state transition- Appears before the state transition is completed (by the next clock pulse).
Moore Machine: Output is associatedwith the state-Appears after the state transition takes place.
Vending Machine FSM
Step 1. Specify the problemStep 1. Specify the problemStep 1. Specify the problemStep 1. Specify the problem
Vending Machine
FSM
N
D
Reset
Clk
OpenCoin
SensorGum
Release Mechanism
Deliver package of gum after 15 cents deposited
Single coin slot for dimes, nickels
No change
Design the FSM using combinational logic and flip flops
Vending Machine FSM
State DiagramState DiagramState DiagramState Diagram
Reset
N
N
N, D
[open]
15¢
0¢
5¢
10¢
D
D
Reuse statesReuse stateswhenever possiblewhenever possible
Reuse statesReuse stateswhenever possiblewhenever possible
Symbolic State TableSymbolic State Table
Present State
0¢
5¢
10¢
15¢
D
0 0 1 1 0 0 1 1 0 0 1 1 X
N
0 1 0 1 0 1 0 1 0 1 0 1 X
Inputs Next State
0¢ 5¢ 10¢ X 5¢ 10¢ 15¢ X
10¢ 15¢ 15¢ X
15¢
Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1
Vending Machine FSM
State EncodingState EncodingState EncodingState Encoding
Next State D 1 D 0
0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X
Present State Q 1 Q 0
0 0
0 1
1 0
1 1
D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
N
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Inputs Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X
How many flip-flops are needed?
Vending Machine FSM
Determine F/F implementationDetermine F/F implementationDetermine F/F implementationDetermine F/F implementation
K-map for OpenK-map for D0 K-map for D1
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
D Q
QR
D Q
QR
Q0
N
N
Q0
Q1
N
Q1
D
D0
D1 Q1
OPEN
D
0Q
NCLK
CLK
Vending machine FSM implementation based on D flip-flops(Moore).
0Q
1Q
Q1
Q0
Reset
Reset
Minimized Implementation
YASE Example: Edge Detector
Bit are received one at a time (one per cycle),
such as: 000111010 time
Design a circuit that asserts
its output for one cycle when
the input bit stream changes
from 0 to 1.
Try two different solutions.
FSM
CLK
IN OUT
State Transition Diagram Solution A
ZEROOUT=0
CHANGEOUT=1
ONEOUT=0
IN=1
IN=1
IN=1 IN=0
IN=0
IN=0
IN PS NS OUT 0 00 00 0 1 00 01 0 0 01 00 1 1 01 11 1 0 11 00 0 1 11 11 0
ZERO
CHANGE
ONE
Solution A, circuit derivation
FF
FF
OUT
IN
NS1
NS0
PS1
PS0
IN PS NS OUT 0 00 00 0 1 00 01 0 0 01 00 1 1 01 11 1 0 11 00 0 1 11 11 0
ZERO
CHANGE
ONE
00 01 11 10
0 0 0 0 -1 0 1 1 -
PS
IN
00 01 11 10
0 0 0 0 -1 1 1 1 -
PS
IN
00 01 11 10
0 0 1 0 -1 0 1 0 -
PS
IN
NS1= IN PS
0
NS0= IN
OUT= PS1 PS0
Solution BOutput depends non only on PS but also on input, IN
ZERO
ONE
IN=0OUT=0
IN=1OUT=1
IN=0OUT=0
IN=1OUT=0
FF
OUT
NS PSIN
IN PS NS OUT 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 0
Let ZERO=0, ONE=1
NS = IN, OUT = IN PS’
What’s the intuition about this solution?
Edge detector timing diagrams
OUT (solution A)
IN
OUT (solution B)
CLK
Solution A: output follows the clockSolution B: output changes with input rising edge and is
asynchronous wrt the clock.
FSM ComparisonSolution A
Moore Machine output function only of PS maybe more state synchronous outputs
no glitching one cycle “delay” full cycle of stable output
Solution B
Mealy Machine output function of both PS & input maybe fewer states asynchronous outputs
if input glitches, so does output output immediately available output may not be stable long
enough to be useful:
CLK
IN
OUT CL
CLK
OUT
FSM RecapMoore Machine Mealy Machine
STATE[output values]
input value
STATE
input value/output values
Both machine types allow one-hot implementations.
FSM Optimization State Reduction:
Motivation:
lower cost fewer flip-flops in one-hot
implementations possibly fewer flip-flops in
encoded implementations more don’t cares in next
state logic fewer gates in next state
logic
Simpler to design with extra states then reduce later.
Example: Odd parity checker
S0[0]
S1[1]
S2[0]
0
1
11
0
0
S0[0]
S1[1]
0
1
0
1
Moore machine
State Reduction “Row Matching” is based on the state-transition table:• If two states
have the same output and both transition to the same next state or both transition to each other or both self-loop then they are equivalent.
• Combine the equivalent states into a new renamed state.• Repeat until no more states are combined
NS outputPS x=0 x=1 S0 S0 S1 0 S1 S1 S2 1 S2 S2 S1 0
State Transition Table
FSM Optimization Merge state S2 into S0 Eliminate S2 New state machine shows
same I/O behavior
Example: Odd parity checker.
S0[0]
S1[1]
S2[0]
0
1
11
0
0
S0[0]
S1[1]
0
1
0
1
NS outputPS x=0 x=1 S0 S0 S1 0 S1 S1 S0 1
State Transition Table
Row Matching Example
NS outputPS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1
State Transition Table
Row Matching Example NS outputPS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f e f 0 1
NS outputPS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 1 e a d 0 1
Reduced State Transition Diagram
State Reduction The “row matching” method is not guaranteed
to result in the optimal solution in all cases, because it only looks at pairs of states.
For example:
Another (more complicated) method guarantees the optimal solution:
“Implication table” method:See Mano, chapter 9.
S0
S1
S2
0/1
1/0
1/01/0
0/1
0/1
Encoding State Variables
Option 1: Binary values000, 001, 010, 011, 100 …
Option 2: Gray code000, 001, 011, 010, 110 …
Option 3: One hot encodingOne bit for every stateOnly one bit is a one at a given timeFor a 5-state machine
00001, 00010, 00100, 01000, 10000
State Transition Diagram Solution B
ZEROOUT=0
CHANGEOUT=1
ONEOUT=0
IN=1
IN=1
IN=1 IN=0
IN=0
IN=0
IN PS NS OUT 0 01 01 0 1 01 10 0 0 10 01 1 1 10 00 1 0 00 01 0 1 00 00 0
ZERO
CHANGE
ONE
How does this change the combinational logic?
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