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(—THIS SIDEBAR DOES NOT PRINT—) DES IGN GUIDE
This PowerPoint 2007 template produces an A0 presentation poster. You can use it to create your research poster and save valuable time placing titles, subtitles, text, and graphics. We provide a series of online tutorials that will guide you through the poster design process and answer your poster production questions. To view our template tutorials, go online to PosterPresentations.com and click on HELP DESK. When you are ready to print your poster, go online to PosterPresentations.com Need assistance? Call us at 1.510.649.3001
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ATLAS phase II upgrade
CHESS1 transistors performance q Two types of transistors in CHESS1 chip : regular and circular q Good agreement between simulation and measurements before irradiation for both.
Isolated amplifier in HV-‐CMOS sensor Ø A low noise built-in amplifier into the HV-CHESS1 chip q Modified from original design by Ivan Peric q Many configurable biases, such as: u Bias in source follower(InSF) u Feedback current (IFB) …..
Strip sensor design using HV-‐CMOS
A. Affolder0, K.Arndt1, R. Bates2, A. Blue2, D. BortoleLo1, C. BuLar2, P. Caragiulo3, D. Das4, J. Dopke4, A. Dragone3, F. Ehrler5, V. Fadeyev6, Z Galloway6, H. Grabas6, I. M. Gregor7, P. Grenier3
A. Grillo6, L. B. A. Hommels8, T. Huffman1, J. John1, K. Kanisauskas1,2, C. Kenney3, J. Kramberger9, Z. Liang6, I. Mandic9, D. Maneuski2, S. McMahon1,4, M. Mikuz9,10, D. Muenstermann11, R. Nickerson1, I. Peric5, P. Phillips1,4, R. PlackeL1, F. Rubbo3, J. Segal3, A. Seiden6, I. Shipsey1, W. Song14, M. Stanitzki 7, D. Su3, C. Tamma3, R. TurcheLa4, L. Vigani1, J. Volk6, R. Wang12,
M. Warren13, F. Wilson4, S. Worm4, Q. Xiu14, J. Zhang12, H. Zhu14 12Argonne Na/onal Laboratory, 8Cambridge University, 7 Deutsches Elektronen-‐Synchrotron, 14Ins/tute of High Energy Physics, Beijing, 9 Jožef Stefan Ins/tute, Ljubljana, Slovenia, 5 Karlsruhe Ins/tute of Technology, 1University of Oxford, 4Rutherford Appleton Laboratory, Didcot, United Kingdom, 3 SLAC Na/onal Accelerator Laboratory, 2SUPA -‐ School of Physics and Astronomy,
University of Glasgow, Glasgow, United Kingdom, 11 Universite de Geneve, 6 University of California Santa Cruz, Santa Cruz Ins/tute for Par/cle Physics (SCIPP), Santa Cruz, CA, United States of America, 13 University College, London, 0University of Liverpool, 10 University of Ljubljana, Slovenia.
Study of built-‐in amplifier performance on HV-‐CMOS sensor for ATLAS phase-‐II strip tracker upgrade Zhijun Liang
(University of California Santa Cruz, Santa Cruz Ins/tute for Par/cle Physics ) On behalf of strip CMOS collaboraNon
IntroducNon to HV-‐CMOS � CMOS sensor is part of the investigation for the ATLAS strip detector upgrade. ◦ Alternative to baseline strip sensor solution (n+-strip in p-type substrate planar sensor)
� Advantage of CMOS sensor: ◦ High segmenta/on and precision: q pitch can be reduced to below 50μm q longitudinal posi/on readout from a strip ◦ low material budget : Can be thinned down to 50μm ◦ Monolithic: Front-end electronics and sensor can be built in the same chip ◦ Has potential to reduce the cost ◦ Has poten/al to have radia/on hard electronics due to small feature size
� Drawback: ◦ Low MIP signal : 1000~2000 e- (10 times lower than baseline planar sensor) ◦ Need low noise built-in amplifier to improve signal-to-noise ratio
� High Luminosity-‐LHC (HL-‐LHC) is foreseen to be completed in 2026. ◦ Aim to increase the integrated luminosity to about ten /mes the original LHC design. ◦ Will improve the precision of the Higgs proper/es measurement ◦ Enhance the sensi/vity for new physics searches.
� ATLAS tracker is expected to have much higher occupancy (200 collisions per beam crossing) � à Need a new detector to survive in such high fluences and occupancy � New detector should have high granularity and radiation hardness
HL-‐LHC Current LHC
� 20mm X 25mm full size sensor is designed for ATLAS strip upgrade ◦ 40μm pitch X 800 μm length (pixel size)◦ Analog frontend and comparators on the sensors. ◦ Digital encoding in periphery for low hit rate application in strip detector. q Maximum 8 hits per 128 stripsq Maximum 1 hit per strip
� Test chips have been fabricated for R & D of strip detector � One chip (HV-‐CHESS1, fabricated in a AMS 0.35 μm high-‐voltage CMOS process) comprises ◦ Several pixel matrices with different geometry ◦ Isolated transistors (regular and circulate geometry) ◦ Standalone amplifier and built-‐in amplifier in pixel arrays
HV-‐CHESS1 test chip
Isolated amplifier Nming performance
AcNve pixel array performance in alpha source test
AcNve pixel array performance in laser scan
Isolated amplifier gain
q Ac/ve pixel = passive pixel + built-‐in amplifier q Use red laser (640nm) for charge injec/on q Red region is the N-‐well. (45 X 100 μm per N-‐well) q Can see all 8 N-‐well inside one pixel (45 X 800 μm ) q Metal layer between each N-‐well. q More metal is on the boLom N-‐well due to Built-‐in amplifier
• Americium-‐241 (Am-‐241) alpha source : 5.5~5.6 MeV • Self trigger , Threshold at 100mV (20 /mes of noise level) , trigger rate is about 3Hz. • Sharper peak at higher V_bias due to higher driq electron contribu/on.
Linear (regular) NMOS
Circular NMOS
Zoom in
Typical signal pulse in alpha source test Signal amplitude distribu/on
Data VS simula/on Before irradia/on
Radia/on hardness Study
q Circular one is expected and measured to have a beLer radia/on hardness q Therefore, only circular ones are used in built-‐in amplifier
Isolated amplifier in CHESS1 is characterized using external pulser
Response curve Signal-‐to-‐noise ra/o Noise level vs dose (HVstrip1)
• Observe higher gain aqer 3Mrad gamma irradia/on Ø Before irradia/on : gain is 1000 mV/fC at 1500 e-‐ input charge. Ø Aqer 3Mrad Gamma irradia/on :gain is 1900 mV/fC at 1500 e-‐ input charge. • Amplifier noise was studied as a func/on of dose. There is a peak at 5Mrad gamma irradia/on • Signal-‐to-‐noise ra/o for MIP signal (>=1500 e-‐) would have been above 50 if one could neglect the influence of n-‐well capacitance.
MIP signal
• Signal rise /me is about 20~50ns, depending on the amplifier configura/on • Timewalk and jiLer studies indicate a single LHC bunch crossing resolu/on (25 ns) • The signal pulse width (dead /me for one pixel) is about a few hundred ns.
Time(s)
Timing JiLer Signal pulse width
8 N-‐well in one of CMOS pixel
VGS (V) VGS (V)
ID ID
Amplifier output with different input charge
HSTD-‐10, Xian, China
Summary Ø HV/HR-‐CMOS technologies are a very aLrac/ve form of monolithic sensors. Ø ATLAS commenced R&D efforts to evaluate them for tracking. Ø Some test chips have been fabricated using these technologies. Ø The performance of built-‐in electronics (circular transistors and isolated amplifier) and ac/vity pixel shows reasonable S/N, /ming proper/es, and radia/on tolerance. Ø The goal for next year : q complete studies of gamma irradiated chips (10/30/100 Mrad) q Study the ac/ve pixel response with beta source. q to design, fabricate and test the large-‐area devices. Acknowledgements Ø We thank Mar/n Hoeferkamp, and Sally Seidel for performing gamma irradia/ons. Ø The work at SCIPP was supported by Department of Energy, grant DEFG02-‐13ER41983.
Time walk
Threshold=0.1V
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