Verilog VHDL code Multiplexer and De Multiplexer

Experiment 3

Name: Shyamveer Singh

Reg no:11205816

Rollno:B-54

AIM: To implement the multiplexer and demultiplexer with data flow and gate level

molding. Appratus: Xilinx ISE 9.2i.

Theory:

Multiplexer:

A multiplexer is a combinational digital logic switching device that has multiple

inputs and one output. In addition to the input and output lines, the

multiplexer has data select lines through which the data passed from an input line to the output line.

Demultiplexer :

A demultiplexer is a combinational digital logic switching device that has a

single input line and multiple outputs. In addition to the input and output

lines, the demultiplexer has data select lines through which the data passed

from the input line to an output line is determined.

Truth table:

4:1 Multiplexer:

S0 S1 y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Multiplexer 2:1:

Veriloge code: module muxtwo(a,b,s,y);

input a,b,s; output y; assign y=((~s)&a)|(s&b);

endmodule

RTL simulation :

Output Waveform :

Implementation of 4:1 Multiplexer: Verilog Code: module muxeight (a,b,c,d,s0,s1,y);

input a,b,c,d,s0,s1; output y; wire w1,w2,w3,w4,w5,w6,w7,w8;

not(w1,s0); not(w2,s1); not(w3,s0); not(w4,s1); and(w5,w1,w2,a); and(w6,w3,s1,b); and(w7,so,w4,c); and(w8,s0,s1,d);

or(y,w5,w6,w7,w8);

endmodule

RTL

Simulation:

Output waveform:

Implementation of demultiplexure 1:2; veriloge code: module demuxtwo(en,s0,s1,y0,y1);

input en,s0,s1; output y0,y1; assign y0=en&(~s0);

assign y1=en&s1;

endmodule

RTL simulation:

Output wave form

Implementation of Four to One

Decoder: veriloge code: module demuxfour(en,s0,s1,y0,y1,y2,y3);

input en,s0,s1; output y0,y1,y2,y3;

wire w1,w2,w3,w4;

not(w1,s0);

not(w2,s1);

not(w3,s0);

not(w4,s1);

and(y0,en,w1,w2);

and(y1,en,w3,s1);

and(y2,en,s0,w4);

and(y3,en,s0,s1);

endmodule

RTL waveform: Output waveform: