Frequency Converter

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3724 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 11, NOVEMBER 2010

Design of Delta-Modulated GeneralizedFrequency Converter

Anshul Agarwal, Student Member, IEEE, and Vineeta Agarwal, Senior Member, IEEE

AbstractThis paper proposes a novel power electronic appli-cation, which is an IGBT-based frequency converter that performsthe function of both cycloconverter and cycloinverter by changingthe 2-b input parameter. It finds its application in speed controlof induction motor, induction heating, fluorescent lighting, ballast,high-frequency power supplies, and so many other applications.A methodology is developed to generate the trigger signals forvarious IGBTs used in frequency converters such that the circuitis not restricted to a particular value of output frequency but itcan produce any output frequency that is an integer multiple ofthe input supply frequency. The output of the converter has beenimproved using delta-modulation technique. Hardware design isobtained using readily available ICs and other components. Thetrigger circuit has been tested qualitatively by observing wave-forms on CRO. The operation of the proposed system has beenfound to be satisfactory.

Index TermsCycloinverter, delta modulation, harmonicreduction.

I. INTRODUCTION

THYRISTOR-CONTROLLED cycloconverters are widely

used in heavy industries such as electric traction, rolling

mills, cement industry applications, static scherbius drives,

ship propellers, and so on [1]. One of the main limitations of

the cycloconverter circuit is that the output frequency cannotbe increased to that of the input frequency [2], [3]. How-

ever, if self-commutated devices are used in place of silicon

controlled rectifiers (SCRs), the need of an external com-

mutation circuit is eliminated, and the same cycloconverter

circuit with self-commutated devices (IGBT) will result to a

direct ac-to-ac or frequency converter, capable of converting

power at the main frequency to a variable frequency [4]. Thus,

this frequency converter will work both as a cycloconverter

and as a cycloinverter. The cycloconverter will convert the

ac input power at one frequency to ac output power at a

lower frequency, whereas a cycloinverter will convert the ac

input power at one frequency to ac output power at a higher

frequency. The output of the converter is however rich in

harmonics. Some of the methods which are employed for

harmonic suppression are the modulation techniques [5][7]

and conventional filter system [8], [9]. The conventional filter

Manuscript received August 25, 2009; revised December 23, 2009; acceptedJanuary 7, 2010. Date of publication February 8, 2010; date of current versionOctober 13, 2010.

The authors are with the Electrical Engineering Department, Motilal NehruNational Institute of Technology (MNNIT), Allahabad 211004, India (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2010.2041740

Fig. 1. Generalized frequency converter.

cannot be used for reduction of harmonics in frequency convert-

ers because the output frequency is varying and using a tuned

filter for each harmonic is not feasible. Hence, the solution

lies in the use of modulation techniques which are flexible and

effective in reducing the output harmonic content to a greater

extent. Various modulation techniques employed to improve

the quality of the load voltage are sinusoidal PWM [10],

space vector PWM [11][13], and delta modulation [14][16].A detailed theoretical study of the delta-modulation technique

has been made in [17] for cycloinverter operation. In this paper,

an attempt has been made to develop a prototype of delta-

modulated generalized frequency converter operating both in

cycloconverter and cycloinverter modes.

II. PRINCIPLE OF OPERATION

Fig. 1 shows the circuit of the proposed frequency converter.

It consists of two converters, namely, a positive (PC) and

negative converters (NC) connected in antiparallel. IGBTs 1

and 2 form a PC, whereas IGBTs 3 and 4 form an NC. Outputis obtained through proper conduction of IGBTs in the two

input cycles. For example, to generate an output frequency that

is twice the input frequency, a firing sequence of 14, 23, 14,

and so on is adopted, whereas for a frequency that is half of

the input frequency, this firing sequence becomes 12, 43, 12,

and so on. Similarly, for an output frequency that is thrice the

input frequency, a firing sequence of 141, 323, 141, and so on is

adopted, and for one third of the input frequency, this becomes

121, 343, 121, and so on.

Thus, the output of the converter will have a frequency of

either fo = fi Nr or fo = fi/Nr, where Nr is an integer andfi

is the source frequency.

0278-0046/$26.00 2010 IEEE


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AGARWAL AND AGARWAL: DESIGN OF DELTA-MODULATED GENERALIZED FREQUENCY CONVERTER 3725

Fig. 2. Basic signals.

Fig. 3. Converter selector.

III. TRIGGER PULSE GENERATION

To generate trigger pulses for the proposed frequency con-verter, six basic signals are required, as shown in Fig. 2. Signal

X1 is a square wave synchronized with the input voltage Viat a frequency of 50 Hz, and signal X2 is the inverted square

wave of X1. Signal X3 is square wave of frequency Nr fisynchronized with X1, and then, signal X4 is the inverted signal

of X3. Similarly, signal X5 is the square wave of frequency

fi/Nr synchronized with X1, and then, signal X6 is the invertedsignal of X5.

The frequency converter in a particular mode may be realized

using an exclusive OR gate by taking a 2-b input word AB

from the user, as shown in Fig. 3. If A = 1 and B = 1 or

A= 0

and B= 0

, the output line Y2 will be high, while Y1will be low. Therefore, the cycloconverter function connected

to the Y2 output line will be enabled else vice versa. Once the

converter is selected, the trigger signals for the cycloconverter

or cycloinverter operation are generated by operating the logical

operators on the basic signals, as shown in Table I.

In order to optimize the harmonics and to improve the output

of the frequency converter, gate pulses to different IGBTs are

modulated using the delta-modulation technique. The standard

delta-modulation principles [14] are shown in Fig. 4. It has been

observed in [17] that, for any output frequency, the total har-

monic distortion (THD) factor is lowest for a modulation index

equal to one. It has also been observed that, with an increase

in carrier frequency, the switching frequency increases, but theTHD does not reduce significantly. Therefore, for hardware

TABLE ITRUTH TABLE FOR THE GENERATION OF THE TRIGGER SIGNAL

Fig. 4. Delta-modulation technique.

implementation, the value of the modulation index has been

kept to be equal to 1, while the carrier frequency fc is 2 kHz.

IV. HARDWARE REALIZATION

Fig. 5 shows the block diagram that is used to generate

the required delta-modulated trigger signals. The input signal

having a frequency fi, which has to be converted into a vari-able frequency signal fo, is stepped down from a step-downtransformer in the input stage. It is then converted into a square

signal using a zero crossing detector (ZCD) to generate signal

X1, and signal X2 is then generated by inverting signal X1.

A converter selector selects the mode of operation of the

frequency converter, as shown in Fig. 3. After selecting themode of operation of the frequency converter, the basic signals

X3, having the frequency fo = Nr fi, and X5, having thefrequency fo = fi/Nr, both synchronized with input signal X1,are generated for cycloinverter and cycloconverter operations,

respectively. Signals X4 and X6 are inverted signals of X3 and

X5, respectively. These signals are then fed to a pulse generator

block to perform the logical operation in order to generate the

required pulses for the IGBT.

The output of the pulse generator is fed to the multiplier

which multiplies it with the delta-modulated analog signal. The

output of the multiplier, which is a delta-modulated signal of the

desired frequency, is fed to the driver circuit, which isolates and

boosts the level of pulses. The obtained isolated pulses drivethe gate of individual IGBTs. The next section illustrates the


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Fig. 5. Block diagram for trigger pulse generation.

Fig. 6. Block diagram of the frequency multiplier using PLL.

generation of basic signals and, then, delta-modulated trigger

signals.

A. Generation of Signals X3 and X4

Signals X3 and X4 at frequency fo = Nr fi are generatedby using a PLL IC 565 and a divide by an Nr counter, as shownin Fig. 6. PLL consists of a phase comparator, an amplifier, a

low-pass filter, and a voltage-controlled oscillator (VCO). Thephase comparator compares the input frequency fi with thefeedback frequency ff and generates an output signal whichis a function of the difference between the phases of two input

signals. The output signal of the phase comparator, which is

a dc voltage, is applied to low-pass filter to remove high-

frequency noise from the dc voltage. This output of the filter

is known as error or control voltage Vc for VCO.When the control voltage is zero, VCO is in the free-running

mode, and its output frequency is called as the center frequency

fcn. The nonzero control voltage results in a shift in the VCOfrequency from its free-running frequency fcn to a frequencyf= fcn + Kv Vc, where Kv is the voltage-to-frequency trans-

fer coefficient of the VCO. The control voltage that is appliedas the input to VCO forces the VCO to change its output

Fig. 7. Divide by an Nr counter for Nr from 2 to 17.

TABLE IITRUTH TABLE FOR THE DECODER

frequency in the direction that reduces the difference between

the input and output frequencies of VCO. This action, which

is commonly known as capturing, continues until the output

frequency of VCO is the same as the input frequency [18]. Once

the two frequencies are the same, the circuit is locked.

If a divide by an Nr counter is inserted between the VCOoutput and the phase comparator input, then the output of the

counter will be locked to the input frequency fi, and VCOwill be actually running at a multiple of the input frequency.

Therefore, in the locked state, the VCO output frequency f isgiven by

f= Nr fi. (1)

The counter counts the output of VCO for a predetermined

period defined by the output frequency fo and thus toggles at

Nr times the output frequency. It has been implemented usinga 4 16 decoder and 16 mod counters (mod 2, mod 3, andup to mod 17). There are sixteen separate output channels,

with one for each Nr. Fig. 7 shows a divide by an Nr counterimplemented for Nr from 2 to 17. A particular mod counter andoutput channel are selected by taking a 4-b word U1U2U3U4from the user and decoding it by a 4 16 decoder according to

the truth table shown in Table II.

The maximum count Nr obtainable with the counter corre-sponds to the maximum output frequency to be generated.

The counter outputs are connected to a 16-to-1 multiplexer.

Four single-pole double-throw switches generate the 4-b mul-

tiplexer address. Depending upon the desired output frequency,

the multiplexer address is selected. The output of MUX is, thus,at a frequency which is well synchronized with fi.


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Fig. 8. Block diagram in generating signals X5 and X6.

B. Generation of X5 and X6

Fig. 8 shows the block diagram that is used to generate

signals X5 and X6 at frequencyfo = fi/Nr. The output voltageVr of the step-down transformer is fed to a full-wave rectifierso that it is rectified to a voltage Vrd. From the rectified voltageVrd, a transistor operating under the ON/OFF mode generates

pulses Ck around zero crossing points of reference voltage Vr.The output Ck triggers a divide by an Nr counter followed by aflip flop. The flip flop gives equal ON and OFF durations to the

counter output required by trigger signal X5 with X6.

The counter counts the output of ZCD for a predetermined

period defined by the output frequency fo. The counter togglesat twice the output frequency. The counter has 16 separate

output channels, with one for each Nr. The maximum countNr obtainable with the counter corresponds to the minimumoutput frequency to be generated.

The counter outputs are connected to a 16-to-1 multiplexer.

The 4-b multiplexer address is generated by using four single-

pole double-through switches. Depending upon the desiredoutput frequency, the multiplexer address is selected as shown

in Table II. The multiplexer output is, thus, X5. Signal X6 is

obtained by inverting X5.

C. Generation of Delta-Modulated Trigger Signal

The delta-modulated signal is generated by using a combi-

nation of OP-AMP and sample-and-hold integrated circuit, as

shown in Fig. 9. It consists of a comparator, an integrator, a

quantizer, and a sample-and-hold circuit. It is a closed-loop

network where the noninverting amplified analog signal having

a frequency of 50 Hz is compared with the delta-modulatedanalog signal, and the generated error is passed through the

integrator which integrates the generated square signal into a

triangular signal having a frequency of 50 Hz.

The error signal is quantized into one of two possible lev-

els Vcc depending on its polarity, whereas the slope of thereference signal determines the time duration between two

successive levels. The comparator output is regularly sampled

by the signal fc to produce the output binary pulses usingsample-and-hold circuit.

The generated delta-modulated output is multiplied by the

pulses produced by the pulse generator circuit to get the desired

delta-modulated trigger pulses. Multiplication is obtained in

a multiplier IC AD633. The obtained delta-modulated triggerpulses are usually at low power levels. They may not be able to

Fig. 9. Delta modulator.

Fig. 10. Experimental setup.

Fig. 11. Synchronization of X1 (upper trace: 5 V/div) with X3 (lower trace:5 V/div) for Nr = 3.

trigger the devices into conduction if fed directly. These pulses

are therefore boosted to high power level by a driver circuit.

The amplified pulses are isolated using opto-coupler 4N35 and

fed to the gate of respective IGBT.

V. EXPERIMENTAL RESULTS

Experimental results are obtained qualitatively by observing

various waveforms on CRO at salient point of the designed cir-

cuit. Fig. 10 shows the photograph of the complete experimen-

tal setup. It consists of power, control, driver, synchronization,

and isolation circuits.

Fig. 11 shows the synchronized signals X1 and X3 with an

input frequency of 50 Hz and a desired output frequency of

150 Hz, while Fig. 12 shows the synchronized signals X1 and

X5 with an input frequency of 50 Hz and an output frequencyof 10 Hz, respectively. The trigger signals for four IGBTs


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Fig. 12. Synchronization of X1 (lower trace: 2.5 V/div) with X5 (upper trace:5 V/div) for Nr = 5.

Fig. 13. Triggering pulses for T1, T2, T3, and T4 in CI operation (all trace:5 V/div) for Nr = 6.

Fig. 14. Delta-modulated signal (2.5 V/div) at a carrier frequency of 2 kHz.

Fig. 15. Delta-modulated triggering pulses for T1, T2, T3, and T4 in CI

operation (all trace: 5 V/div) forNr = 6

.

are shown in Fig. 13 for Nr = 6 in the cycloinverter modeoperation. Fig. 14 shows the delta modulator circuit output at

a switching frequency of 2 kHz.

Delta-modulated trigger signals for four IGBTs are shown in

Fig. 15 forNr = 6 in the cycloinverter mode operation. Figs. 16and 17 show the trace of the output voltage of the proposed

converter along with the input voltage for Nr = 3 and Nr = 5,respectively, for the cycloinverter operation. Figs. 18 and 19

show the trace of the output voltage of the converter for Nr = 2and Nr = 5 for the cycloconverter operation. Due to some volt-age drop in the circuit, the output voltage level is somewhat less

than the input supply voltage level. The converter is designed towork satisfactorily in the output frequency range of 3850 Hz.

Fig. 16. Input voltage (upper trace: 50 V/div) and output voltage (lower trace:50 V/div) of the cycloinverter for Nr = 3.

Fig. 17. Input voltage (upper trace: 50 V/div) and output voltage (lower trace:50 V/div) of the cycloinverter for Nr = 5.

Fig. 18. Input voltage (upper trace: 50 V/div) and output voltage (lower trace:100 V/div) of the cycloconverter for Nr = 2.

Fig. 19. Input voltage (upper trace: 50 V/div) and output voltage (lower trace:100 V/div) of the cycloconverter for Nr = 5.

The range may be extended by selecting the input address of

the multiplexer circuit more than 4 b.

VI. CONCLUSION

A direct frequency converter has been realized, which per-

forms the function of both cycloconverter and cycloinverter.The delta-modulation technique has been implemented in order


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to improve the output of the frequency converter. A method-

ology is obtained in generating the required trigger signal for

any integer multiple/submultiple output frequency. Hardware

realization of the control and power circuits has been done

using readily available ICs and less expensive flip flops. Design

of the control circuit is done in such a manner that no new

components are needed in changing Nr from one value toanother. This reduces the complexity of the control circuit. The

trigger circuit has been tested qualitatively by observing the

various waveforms on CRO. The operation of the proposed

system has been found satisfactory. Although the topology

developed is single phase and low powered, it can be easily

converted into three phase [1] and may be used for speed control

of ac drives or for aerospace or aircraft to keep planes powered

up when on the ground in ground power units.

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[6] G. Joos, P. D. Ziogas, and D. Vincenti, A model reference adaptivePWM technique, IEEE Trans. Ind. Electron., vol. 5, no. 4, pp. 485494,Oct. 1990.

[7] J. Zaragoza, J. Pou, S. Ceballos, E. Robles, P. Ibanez, and J. L. Villate, Acomprehensive study of a hybrid modulation technique for the neutral-point-clamped converter, IEEE Trans. Ind. Electron., vol. 56, no. 2,pp. 294304, Feb. 2009.

[8] P.-T. Cheng, S. Bhattacharya, and D. M. Divan, Control of square-waveinverters in high-power hybrid active filter systems, IEEE Trans. Ind.

Appl., vol. 34, no. 3, pp. 458472, May/Jun. 1998.[9] T. Shimizu and S. Iyasu, A practical iron loss calculation for ac filter

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[10] D. Yonggui and X. Keming, The SPWM inversion mode of suppress-ing harmonic waves based on genetic algorithm, in Proc. 5th ICEMS,Aug. 2001, vol. 2, pp. 13041307.

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[13] J. Leon, S. Vazquez, J. Sanchez, R. Portillo, L. Franquelo, J. Carrasco, andE. Dominguez, Conventional space-vector modulation techniques versusthe single-phase modulator for multilevel converters, IEEE Trans. Ind.

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[14] P. D. Ziogas, The delta modulation technique in static PWM inverter,IEEE Trans. Ind. Appl., vol. IA-17, no. 4, pp. 199204, Mar./Apr. 1981.[15] M. A. Rahman, J. E. Quaicoe, and M. A. Choudhury, Perfor-

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Anshul Agarwal (S10) was born in Mathura,India, on May 5, 1984. He received the B.Tech.degree in electrical and electronics engineering fromthe Uttar Pradesh Technical University, Lucknow,India, in 2007, and the M.Tech. degree (goldmedalist) in power electronics and ASIC design fromthe Motilal Nehru National Institute of Technology,Allahabad, India, in 2009, where he is currentlyworkingtowardthePh.D.degreeinpowerelectronics.

His research interests include power electronic de-vices, converters, inverters, and ac-to-ac converters.

Vineeta Agarwal (M05SM10) received the B.E.

and the M.E. degrees in electrical engineeringfrom Allahabad University, Allahabad, India, in1980 and 1984, respectively, and the Ph.D. de-gree in power electronics from the ElectricalEngineering Department, Motilal Nehru RegionalEngineering College, Allahabad, while she wasteaching.

In 1982, she joined as a Lecturer with theElectrical Engineering Department, Motilal NehruRegional Engineering College. She is currently a

Professor with the Electrical Engineering Department, Motilal Nehru NationalInstitute of Technology, Allahabad. She has taught numerous courses in electri-cal engineering and electronics. Her research interests are single- to three-phaseconversion and ac drives. She has a number of publications in journals andconferences in her field. She has attended and presented papers at both nationaland international conferences.

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