Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits

I46 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 2, FEBRUARY 1993

Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits

Jitendra Khare, Student Member, IEEE, Derek B. I. Feltham, Student Member, IEEE, and Wojciech Maly, Fellow, IEEE

Abstract- This paper presents a general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensi- tivity to manufacturing defects of varying sizes. The important concept addressed in this paper is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell’s critical area (CA) for accurate yield estimation. Two examples-a 256-kb SRAM and reconfigurable 32 x 32-port 32-b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method.

I. INTRODUCTION

HE drive towards incorporating increasingly complex T functions on a single integrated circuit (IC) has led to an active interest in fabrication of large-area IC’s, which can accommodate more devices on a single substrate (see, e.g., [15]). In order to improve these circuits’ yield, which would otherwise be too low for commercial manufacturing, they are designed with redundant elements. These redundant elements are used to repair the circuit if necessary, using one of the available reconfiguration techniques. Traditionally, redundancy has been used mainly in memories [ 5 ] , [9], [19]. However, there is an increasing trend towards the use of reconfiguration techniques in logic circuits [26], [27], [30], and even in high-performance microprocessors [6]. In the near future, it is likely that a significant fraction of complex IC’s will need to have some reconfiguration on chip, in order to be commercially viable.

This trend towards reconfigurable circuits opens up a number of design issues that need to be addressed. The most important of these is the question of how best to apply the advantages of reconfiguration in future systems, to maximize the number of working dice per wafer. Determination of opti- mal redundancy and reconfiguration strategy for a given circuit must be approached by using appropriate yield modeling methodologies, a number of which have been reported in the literature (e.g., [ 171). Unfortunately though, these traditional yield methodologies cannot handle reconfigurable circuits, other than DRAM’S, with sufficient accuracy. The actual yields obtained for these circuits are often much lower than

predicted by theoretical calculations, resulting in hard-to- predict fabrication costs. Given the increased competition and low profit margins in modern semiconductor manufacturing operations, such inaccuracies can lead to a loss of profits. Hence, there exists an urgent need for new yield methodologies and related CAD tools which are able to estimate yield of reconfigurable circuits with sufficient accuracy.

The main problems with traditional models, which any new methodology will have to address, are of two kinds. First, the majority of current yield models represent defects as dimensionless “points” [ 171. Any such point defect occurring in a block of an IC is assumed to cause a functional failure of the block. The problem is that these models take into account neither the fact that defects have a nonuniform size distribution [3], 141, [8], 1111, [ 121, [23], [24], nor the true nature of the interaction between defects and the layout [ 111. In addition, traditional yield models do not account for the fact that a single defect in a cell of reconfigurable circuit may affect more than just the cell in which it occurs [ 151. Consequently, traditional yield models do not distinguish between failure behaviors, and they treat all faults within a cell as reconfigurable failures. This inability of traditional methodologies to consider “local” (i.e., reconfigurable) and “global” (i.e., nonreconfigurable) failures separately is the key reason for their tendency to overestimate circuit yield.

One methodology, based on Monte Carlo simulation techniques [2], which addresses the above problems for a specific class of reconfigurable circuits (i.e., DRAM’s) has been presented in [22]. This methodology, however, is appropriate only for reconfigurable circuits with small replicated cells. It cannot be easily extended to reconfigurable circuits with large replicated cells, due to the enormous computing time required to perform a statistically significant number of simulations for such circuits.

In this paper, a generalized methodology is presented, which is applicable for all classes of reconfigurable circuits. This methodology is based upon ideas explored initially in [ 131, [15], and [21]. This paper also presents a CAD tool that has been implemented in order to demonstrate the feasibility of the proposed methodology.

This paper is organized as follows. In Section 11, the yield model and methodology for accurate yield estimation

Manuscript received March 26, 1992; revised September 24, 1992. This work was supported by the National Science Foundation under Grant MIP for reconfigurable circuits are described’ In Section ‘I1* the 8822805, the’semiconductor Research Corporation under Grant 91-DC-068, and by SEMATECWSRC under Contract 89-MC-5 1 1.

The authors are with the Department of Electrical and Computer Engineer- ing, Camegie Mellon University, Pittsburgh, PA 15213.

application of this methodology in evaluating design for maun- facturability trade-offs is demonstrated, using two designs of a 256-kb SRAM. In Section IV, this methodology is applied to a 32 x 32-port 32-b crossbar switch design. Section V presents IEEE Log Number 9205340.

0018-9200/93$03.00 0 1993 IEEE

KHARE et al.: DEFECT-RELATED YIELD LOSS IN RECONFIGURABLE VLSI CIRCUITS I47

U Reconfigurable Parts Non-configurable Parts

Fig. 1. Example layout of a reconfigurable VLSI circuit, showing reconfigurable and nonreconfigurable blocks of a system.

the details of a prototype CAD tool implementation based on the above methodology. Finally, the conclusions which can be drawn from this work are described in Section VI.

11. YIELD ESTIMATION FOR RECONFIGURABLE VLSI CIRCUITS

A. System-Level Yield Model

Consider a typical VLSI circuit as shown in Fig. 1, con- sisting of some r reconfigurable blocks and a number of nonreconfigurable blocks. For yield purposes, the nonreconfigurable blocks can be lumped together as a single block, which would include all I/O, control and self-testing circuitry, and the actual reconfiguration-control logic on the chip. The yield of such a VLSI circuit is given by the formula:

where Y,, Yz, . . . , Y, are the yields of the r reconfigurable blocks, and Ynon-reconf is that of all nonreconfigurable blocks of the circuit.

Consider the yield expression for some typical reconfigurable block in the above system, in which at least m out of n replicated cells must Se functional for the block to yield. According to traditional yield models [17], the yield of this block is given by

where Yeell is the yield of the basic replicated cell in the block. Note, however, that the replicated cells in a reconfigurable

design can be affected by two kinds of faults: 1) faults affecting only the local nets, which can be repaired (i.e., reconfigured) by using the available redundant elements, and 2) faults affecting at least one global signal (such as V d d , GND, or clock lines), which make it impossible for the circuit to be repaired by reconfiguration. Hence, Yeell can be expressed more accurately as

(3)

where Yeell-, is the cell yield due to defects affecting only local nets and Ycell-n is the cell yield due to defects affecting at least

Yeell = (Ke1I-r) . (YcelI-n)

one global net in the cell. In this case, for the reconfiguration scheme to be successful, at least m out of n cells need to be free from local faults, but all n cells must be free from faults affecting global signals. &,lock is therefore described more accurately by

Depending on Yeell-, and Ycell-n, the value of Yblock obtained from the above expression can be very different than if evaluated according to the traditional model of (2). To see the relevance of this observation, consider, for example, a reconfigurable block with n = 11 and m = 10. Let Yeell-, = 0.95 and Ycell-n = 0.95 for the replicated cell. Evaluating by (2) gives Yblock = 0.70, while (4) gives Yblock = 0.51. The percentage overestimation in this case is about 40% of the more accurate yield value. Such errors in yields of reconfigurable blocks will also cause a significant error in the total yield estimate for an entire system. Therefore, Yeell-, and Ycell..n must be evaluated separately for accurate yield estimation. Most traditional yield models [ 171, however, are unable to obtain these values, as they do not use any notion of signal nets in a layout while calculating the yield. A high-fidelity yield model has to be used therefore to obtain these numbers. The methodology for evaluating these yields is described in the following section.

B . Accurate Yield Evaluation for a Replicated Cell

1 ) Defect Model: As indicated in Section I, defect size distribution must be taken into consideration for accurate yield estimation. The defect model used in this paper is one that is typically used in industry [3], [4], [23], [24] to model size distributions. Note, however, that the user does not have to use this model, but is free to use one that best suits the manufacturing facility under consideration.

According to the chosen model, defects are modeled as shorts or opens occumng in the various conducting and semiconducting layers of an IC. These shorts and opens are treated as disks of extra or missing material regions in those layers. The size distribution for defects of any type z is given by

klR, 0 < R 5 Xoa ( 5 ) { &> X o z 5 R

f,(R) =

where R is the defect radius and Xoz and p , are parameters to be extracted from the fabrication line. The value of Xo2 is always very small compared to the minimum feature size. Therefore, any fabrication line will always see a size distribution of only f z (R) = k z / ( R ) J ” . Both X O , and p , are assumed to have different values for each defect type 2.

The defect model used in this paper has another parameter DO, which is a measure of the effective density (i.e., defect density actually seen by the layout) for the defect of type a . The defect density variation D,(R) with respect to defect size

I48 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 2, FEBRUARY 1993

is obtained by multiplying DO, and fi ( R ) . Therefore

(6) DOA2 - Kz D , ( R ) = - - - (R)pt (R)pa.

Thus, in order to characterize the density variation of any defect type completely, two parameters, p, and K , , have to be determined.

The parameters pi and Ki are related to the effective defect (a) density as follows. Consider, as an example, shorts occurring in a metal layer that has minimum spacing s. In such a case, all defects with radius less than s/2 will not be able to cause any short in that layer. Hence, the effective defect density seen by the layout, Di-effective, is determined by only those defects that have a radius not smaller than s/2. Therefore, according to the defect model, Di-effective for shorts is given by

In a similar way, if w is the minimum width of lines in a layer, then the effective density of opens in the layer is given bv

Thus, for any defect type i, if the three parameters4ffective density Di-effective, spacing s, and width w-are known, along with one of Ki and p i , the remaining parameter can be calculated.

2) Yield Model: The yield model used in the examples presented in this paper is the Poisson yield model [28]. However, any yield model can be used without loss in generality. For instance, a model that deals with defect clustering [17], [25] may be more appropriate for certain fabrication facilities.

According to the simple Poisson model, which treats defects as points defects, the yield for any cell of area A due to defects of any one type i (shodopen in any layer) is given by

(9)

where Di-effective is the density of defects of that type. The problem with (9), however, is that it assumes defects to be dimensionless “point” defects. In addition, the area of a die that can be affected by a defect is the function of the defect radius. This area can be described by a function called the critical area [3], [4], [ l l ] , [12], [23], [24]. The critical area for a defect of radius R , A ( R ) , can be defined as that area on the die in which the center of a circular defect has to fall for a fault to occur in the circuit. The function A( R ) can be defined for both shorts and opens in each conducting/semiconducting layer of an IC.

In order to better understand the critical area concept introduced above, consider the example of shorts in a layer of an IC, in which the layout consists of a simple array of lines as shown in Fig. 2. Let s be the minimum spacing between the lines, w be the line width, and A0 be the layout area. For such a layout, extra material circular defects of radius

y. - e-(ADt-effective) 2 -

Critical

%

].,,,,I Causing Fault

’ s/2 R I R 2 R o = (2s + a ) / Z Defect Radius

(C)

Fig. 2. Critical area function for shorts in a simple array in an IC layer.

less than s/2 will not be big enough to be able to touch any pair of lines. Hence, these defects would not cause a short, irrespective of where on the layout they occur. As a result, the critical area A( R ) is zero for defect radius 5 s/2. However, as defect radius increases beyond s/2 (see Fig. 2(a) and (b)), the area on which the defect could fall to cause a short increases with the defect radius. This increase in A ( R ) is linear, and continues until the critical area reaches the value Ao. At this radius Ro = (s + w/2), for which A( R ) = Ao, a defect could fall anywhere on the die and cause a short. This is also true for all defects with radius greater than Ro. Hence, the critical area function saturates at Ao. Fig. 2(c) shows the complete critical area variation for this layout.

Note that the critical area function does not always increase linearly for all layouts. In the example in Fig. 2, the increase was linear due to the simplicity of the layout pattern. In general, this increase is monotonic and nonlinear, with the rate of increase at any radius being completely determined by the actual layout geometry.

Taking into account both these factors, f i ( R ) and A ; ( R ) , for each defect type i , and using (9), the total yield (taking into account yield loss from all types of defects) can be obtained [ l l ] as

where n is the number of defect types and D;(R) is as seen

KHARE er al.: DEFECTRELATED YIELD LOSS IN RECONFIGURABLE VLSl CIRCUITS

~

149

in (6). Hence, if Di(R) is known for all defect types, then the corresponding critical area functions for a replicated cell and (10) can be used to calculate the yield of the cell.

3 ) Separation of Reconfigurable and Nonreconfigurable Yield: The advantage of using the concept of critical area is that it is not limited to considering the whole cell at once. Critical area functions can also be defined for defects affecting any chosen subset of nodes. For example, A; (R) can be defined for metal shorts between V d d and GND, or for polysilicon opens affecting some node ‘‘k” in the circuit. This ability is of great importance to the yield methodology presented here. To see this, notice that depending upon where a defect falls inside a replicated cell, it can either cause a fault affecting only local nodes within the cell, or it can cause a fault affecting at least one node (referred to as a “global” node) which spans many cells. The critical area function A;(R) for the cell, therefore, can be separated and written as the sum of Ai-global(R) and Ai-loca1(R), representing these two classes of faults which may occur in the cell. Modifying (10) to account for this separation of critical areas, the total yield for the replicated cell can be written as

n

Note that the first product term in (11) is the modified Poisson expression for cell yield due to reconfigurable faults, and the second term is that for nonreconfigurable faults. Thus, if the critical areas Ai-local(R) and Ai-g~obal(R) are known for each defect kind, the reconfigurable and the nonreconfigurable yields can be obtained for each replicated cell. Once the yield components Yeell-,. and Ycell-n have been obtained separately for each cell, the yield of a complete reconfigurable system can be estimated.

111. EXAMPLE 1-256-kb SRAM

To analyze the relevance of the yield-modeling methodology proposed above, the manufacturability of the core of two 256- kb SRAM’s is discussed in detail in this section. The SRAM’s provide an example of a reconfigurable circuit in which the replicated cell is small.

A. SRAM Architecture Fig. 3 shows the floorplan of the core of the two SRAM

memories under consideration, designed for a 1 .O-pm standard CMOS process. The core of each memory consists of four blocks, each containing a basic array of 256 x 256 SRAM cells. In addition, in every block, there is one redundant column that may be used to replace any other column in the block. The only difference between the two memories is in the layout of the basic memory cell. The two versions of the cell layout are shown in Fig. 4. The main difference between the two layouts is a more relaxed spacing of metal lines in the SRAM2 cell, causing an increase in the cell area of 5.4%. The total areas of

Fig. 3. Floorplan of the core of the 256-kb SRAM.

Vdd Vdd

Gnd Word Line

Gnd

Word Line

Active Areo 88 Poly First Metal Second Metoi

(a) (b)

Fig. 4. (a) Layout of SRAMl cell (b) Layout of SRAM2 cell.

the core array are 0.63 and 0.67 a n 2 for SRAMl and SRAM2, respectively.

B . Yield Equations-Traditional Methodology In this section, the yield of the SRAM cores will be esti-

mated by using the traditional yield-estimation methodology. In each SRAM core, there are four large blocks of memory

cells, all of which must be functional for the entire circuit to yield. Since the blocks are reconfigurable, at least 256 out of 257 columns must function in every block. Therefore, the yield equations for each SRAM core can be written as

Ytotal = (Yb10ck)~ (12)

Ycol = (Yce11)256 (14) Yblock = f 257 ’ ( y c 0 1 ) ~ ~ ~ ’ (1 - Zol) (13)

where Ycell is the yield of each individual memory cell in the circuit. Yeell can be calculated from (10) if the total critical area function Ai(R) is known for all defect types i .

C. Yield Equations-Proposed Methodology

According to the model proposed in Section I1 for accurate computation of yield loss, the equation for Ytotal is the same as (2), but Yblock must be broken down into its reconfigurable

150 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 2, FEBRUARY 1993

and nonreconfigurable components. Therefore

Yblock = (Yblock-r) ' (Yblock-n). (15)

As in the traditional yield-estimation methodology, the reconfigurable component of the memory block yield should be calculated assuming that at least 256 of the 257 columns in a block are operational. The nonreconfigurable components of all 257 cells, however, must be fault-free for a block to yield. Therefore

where Yce1l-,. and Ycel~-n are the reconfigurable and nonreconfigurable components of Ycell. As shown in (1 I), Ycel1-,. and Ycell-n can be calculated if A;-local(R) and A;-global(R) are known, respectively, for all defect types i.

D. Critical Area Calculations for the SRAM Cells In order to calculate cell yield accurately, it is necessary to

calculate critical area functions for all defect types that affect the circuit. To simplify the calculations, however, Ycell was calculated taking into account only extra material defects in first and second metal in the memory cell. Yce1l, therefore, represented only the interconnect yield of the cell in these examples. It should be noted that for a SRAM, the contribution of other defect types (mainly extra polysilicon defects) to the total yield loss may be comparable to that of extra metal defects.

There are three distinct fault classes for which critical area functions needed to be calculated:

fatal faults, which are caused by the defects that involve a global node of the memory cell (i.e., V d d or GND) in the resulting short; double-column faults, which arise from those shorts that do not include global nodes, but do include a node from an adjacent column of the memory core; single-column faults, which include all other faults that may arise as the result of an extra material defect.

Triple column (and larger) faults were ignored, as their probability of occurrence is very small.

The critical area functions for each of these fault classes were derived using a prototype CAD tool, which was implemented under the Cadence Edge Framework [I]. The implementation of this tool is described in detail in the Section V.

The graphs of Fig. 5 show the critical area curves for first and second metal extra-material defects for all three fault classes for the SRAMl cell. The graphs of Fig. 6 show the corresponding curves for the SRAM2 cell. Note that the uppermost curve in the graphs shows the total critical area, and the shaded areas in the graphs represent the contribution of each class of critical area to this total.

0.0 1.0 2.0 3.0 4.0 5.0 6.0

Defecl Radius (pin)

w - - f 0.0 1.0 2.0 3.0 4.0 5.0 6.0

y1 Defect Radius (pin)

Fig. 5. First- and second-metal critical area components for the SRAMl cell.

The critical area graphs illustrate some interesting properties of the SRAM circuitry under consideration. In the first metal graphs for both cells, it can be-seen that as the defect radius gets larger, successively more of the critical area becomes classified as fatal, as larger defects have a progressively higher probability of affecting a global circuit node. Secondly, in either cell layout is there no possibility of a fatal fault occurring as a result of a second metal short. This is simply because V d d and GND (which are the only global metal nodes in these circuits) never run in second metal. Note again that the traditional yield estimation methodology takes into account only the total critical for each cell, while the proposed methodology makes use of the detail of the relative proportions of each class of critical area.

E . Yield Calculation

In the computation reported in this section, the commonly used f ; ( R ) a l / R 3 defect size distribution [23], [24] was used for both first- and second-metal shorts in both methodologies. The K, values for each defect type were chosen to represent a typical processing line [7], in which first-metal shorts account for 20% of the total observed defects, and second-metal shorts account for 30% of the total observed defects.

Yield calculation using the traditional methodology was straightforward. A;(R) was simply taken to be the entire critical area of the memory cell. A i ( R ) and f ; (R) were then used to determine Yce1lr according to (10). From this, Yblock

and Ytotal for the memory array were derived using (12H14).

KHARE el al.: DEFECT-RELATED YIELD LOSS IN RECONFIGURABLE VLSI CIRCUITS 151

0.0 1.0 2.0 3.0 4.0 5.0 6.0

0.0 1.0 2.0 3.0 4.0 5.0 6.0

Defect Radius (pm)

Fig. 6. First- and second-metal critical area components for the SRAM2 cell.

Yield calculation using the proposed methodology was performed as follows. Since the redundancy scheme had just one extra column per memory block, both fatal and double- column faults were classified as nonreconfigurable faults, while single-column faults were classified as reconfigurable faults. Therefore, for this example:

Using (l l) , (20), and (21), and the critical area functions in Figs. 5 and 6, Ycell-r and Ycell-n were obtained for each of SRAMl and SRAM2. These values were then used to determine Yblock, from which the yield of each version of the 256-kb SRAM was determined.

In Fig. 7(a), yield curves for SRAMl and SRAM2 cores are shown as functions of defect density, calculated using the traditional methodology. In Fig. 7(b), the same curves are shown, calculated using the modified yield model. As expected, the traditional yield-estimation methodology showed a slight improvement in the yield for the SRAM2 cell layout as compared to the SRAMl cell. However, the more detailed calculation of the proposed methodology showed the opposite to be true-according to the proposed yield model, the "improved" memory cell of SRAM2 actually has a worse yield than the SRAMl cell. This is due to the fact that by increasing the spacing of the second metal lines for the SRAM2 cell, the

. 0.0 1.0 2.0 3.0 4.0 5.0

Defect Density (per "2)

(a)

1 .o

3 0.9

ss re * = 0.8 - 8 ga U00

z5 <a 0.7

gz 0.6

Y 0.5

0.0 1.0 2.0 3.0 4.0 5.0

Defect Density (per m A 2 )

(b)

Yield curves for SRAMl and SRAM2 calculated using the (a) traditional and (b) improved yield-estimation methodologies.

Fig. 7.

probability of occurrence of double-column faults, which are nonreconfigurable, increased significantly.

Furthermore, for each memory, there was a very large difference in the yield estimate between the traditional and the proposed methodologies, even for moderate defect densities. This is due to the fact that, in the basic cell for both designs, the majority of interconnect defects cause either fatal or double- column faults. Neither of these cases is accounted for properly using the traditional yield-estimation methodology. Thus, it can be seen that not only can the traditional methodology significantly overestimate the yield of a reconfigurable circuit, but it can also give false indications as to which of a set of design choices will be more profitable.

Iv. EXAMPLE 2-RECONFIGURABLE CROSSBAR SWITCH

In this section, the application of the described yield- estimation methodology to a reconfigurable circuit with a large replicated cell is shown. The circuit considered is a reconfigurable 32 x 32-port 32-b crossbar switch, presented in [21].

A. Crossbar Switch Architecture [21] The crossbar switch under consideration has 32 input ports

and 32 output ports, each 32 b wide. The function of the switch is to connect any of its inputs to any of the outputs,

I52

Output dolo ond address buses in first metol ( 0II reconliguroble nodes )

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 2, FEBRUARY 1993

VWGNO

VWGND

VWGND

(16ml. Out Of 17) (16 ml. Out Of 17)

Port0 Port1 -..- Port15 Pcf l l6 Pcfl17 -..- Port31

- GND

- Vdd

- GND

poly-silicon lirst metol second metol

Fig. 8. Layout of the basic cell of the crossbar switch.

Port 0

I I I

Port30

Port31

cm~sbar oumut pots

Fig. 9. Floorplan of the 32 x 32-port crossbar switch.

According to the traditional methods, defects occumng in according to the address received by its reconfiguration logic. Such circuits can be used to provide efficient large-bandwidth

as very long instruction word (VLIW) architecture systems [IO].

each replicated cell only affect the cell locally. Therefore

communication networks for a number of applications, such Yblock = (Yco~)'~ + 1 7 . (Ycol)l6 . (1 - ycol) (23) yco~ = ( y c e 1 1 ) ~ ~ (24)

The desired configuration of the crossbar switch is 32 functional columns of switches, eqch containing 32 basic switch cells. The need for reconfiguration for the crossbar switch becomes apparent when one considers the size of the chip. The layout of the basic crossbar switch cell (in 1.0-pm CMOS technology) is shown in Fig. 8. The dimensions of this cell are 553 x 376pm. The dimensions of the complete 32 x 32 cell crossbar chip, not including any I/O circuitry or redundant elements, would therefore be approximately 1.7 x 1.2 cm. Assuming a simple Poisson yield model and a defect density of 1 defect per cm2, this crossbar would have a yield of less than 0.13. Thus, the size of the crossbar switch makes it necessary to include a reconfiguration scheme in order to ensure an acceptable yield during its manufacture.

The reconfiguration scheme considered for yield calculation is shown in Fig. 9. The circuit is organized into two identical blocks, each containing 17 columns of 32 identical cells. The full crossbar switch of 32 working columns is configured by selecting and connecting 16 out of 17 defect-free columns in each half of the chip. The reconfiguration is performed under the control of 34 built-in test circuits [14], [16], [20], one associated with each available column in the layout.

where Ycell can be estimated using (10).

C . Yield Equation-Proposed Methodology

According to the methodology proposed in Section 11, (22) still gives the total crossbar yield, but (23) no longer models Yhlock with sufficient accuracy, since the crossbar column actually contains some circuitry which is not reconfigurable. (As seen from Fig. 9, V d d , GND, and crossbar input bus lines run across all columns, with no provision made for their reconfiguration.) Considering Ycol-r to be the yield of the reconfigurable nets in the crossbar columns, and Ycol-n to be the yield of the nonreconfigurable nets in the column, the yield expression for &lock can be written as

Since there are 32 copies of the basic cell in each column of the layout, and since all must be defect-free for a column to be considered functional, the following expressions for Ycol-r and Ycol-n can be written:

Ycoi-r = (Yce11-r)~~ and Yco~-n = (Yce~l-n)32 (26)

Yce~l-r and Ycell-n represent, respectively, the yields of the reconfigurable and nonreconfigurable portions of the basic cell layout, and can be calculated using (11) in Section 11.

D. critical

B . Yield Equations-Traditional Method

In calculating the yield for the crossbar switch, note first that there are two identical blocks in the crossbar layout. Each block contains 17 columns of crossbar switch circuitry, 16 Calculations for the Crossbar Cell of which must be functional for a block to be configurable as functional. Both blocks must be functional for the complete circuit to work. Therefore, the total yield of the crossbar circuit can be calculated from

Nonreconfigurable faults in the basic crossbar switch cell were defined as those shorts which included either V d d , GND, or data bus nodes (see Fig. 8). All other shorts were classified as reconfigurable faults. As said earlier, the reconfigurable

Ytotal = (Yhlock)2. (22) and the nonconfigurable critical area functions were calculated

KHARE et al.: DEFECT-RELATED YIELD LOSS IN RECONFIGURABLE VLSI CIRCUITS 153

reconfigurable nodes in first metal

non-reconfiguroble nodes in first metal

criticol area for non-reconfigurable nodes

Fig. 10. Nonreconfigurable critical area geometry for 5.0-pm radius first-metal defects in a section of the crossbar switch cell.

using the CAD tool described in Section V. Fig. 10 shows an example of the first-metal nonreconfigurable critical area geometry for a section of the cell, for a defect radius of 5.0 pm. In the figure, all original first-metal geometry is drawn, as well as the nonreconfigurable critical area related to the Vdd and GND nodes in the layout.

Fig. 1 l(a) and (b) shows the calculated critical area curves for the first-metal and second-metal defects in the basic switch cell. In these graphs, the reconfigurable component of the critical area, Ai-local(R), is represented by the difference between the nonreconfigurable and total critical area curves. For first metal, it can be seen that the nonreconfigurable component of the critical area represents roughly 50% of the total critical area for smaller defect radii, and increases to over 65% of the total critical area for larger defect radii. For second metal, the situation is even more remarkable-the nonreconfigurable critical area can represent as much as 90% of the total critical area. The reason for this is that the majority of second metal in the layout of the basic cell is used in the large (nonreconfigurable) input data bus running across the top of the cell (see Fig. 8). In addition, l/dd and GND lines run across the cell in second metal. For large defect radii, the critical area representing shorts in this bus will dominate the critical area of second metal.

E. Yield Calculations As in the SRAM example, metal 1 and metal 2 shorts were

assumed to be the only defects affecting the crossbar yield. For the crossbar, this is a realistic assumption, since the cell area occupied by the nonmetallic conducting layers (i.e., poly and diffusion area) is only a small fraction of the total area of the crossbar cell. The defect parameters used in yield calculations were the same as those used in the SRAM example.

In order to calculate the crossbar yield using the traditional methodology, the total critical area functions in Fig. 11 for metal 1 and metal 2 were used along with (10) to obtain Yce1l. From this, Yblock and Ytotal for the crossbar were derived using (22)-(24). Yield calculation using the proposed methodology

-I 1 , 1 1 1 1 , I l l

0.0 2.0 4.0 6.0 8.0 10.0

Defect Radius (bm)

(a)

2.5e+5 I I I I I I l , I 1 CAfwReconfigurableNodcs I , ,

2.oc+5

1.5e+5

1.oc+5

O.oc+O 0.0 2.0 4.0 6.0 8.0 10.0

Defect Radius (Bm)

(b)

Fig. 1 1. Nonreconfigurable and reconfigurable components of the total critical area for (a) first metal and (b) second metal in the crossbar switch cell.

was performed as follows. Using (11) and the critical area components in Fig. 11, Yce~l-r and Ycel~-n were obtained for the crossbar cell. The total yield was then obtained from these values using (22), (25), and (26). The yield curves obtained by both the methodologies are plotted in Fig. 12(a). As in the SRAM example, there is a considerable difference in the two curves, solely due to accurate separate consideration of the reconfigurable and nonconfigurable components of the critical area.

It must be noted, however, that the yield curves of Fig. 12(a) only account for the reconfigurable blocks of the crossbar switch. In order to estimate the total yield for a realistic chip layout, yield for the nonreconfigurable blocks on the chip (including test, reconfiguration control, and 1/0 circuitry) must also be calculated and factored in, using (1). However, for the simple purpose of comparing the traditional and presented methodologies, it is not necessary to estimate yields for the nonreconfigurable blocks. In both methodologies, Ynon-reconf is calculated in the same way. Therefore, both yield curves of Fig. 12(a) overestimate the actual yield of the crossbar switch by the same factor, which is Ynon-reconf. In order to make an accurate comparison of the two methodologies, it is sufficient to consider simply the ratio of the yield

0.0 1.0 2.0 3.0 4.0 5.0

Total Defect Density (per cmA2)

(a)

0.0 1.0 2.0 3.0 4.0 5.0

Total Defect Density (per “2)

(b)

Fig. 12. (a) Traditional and proposed yield estimates for the crossbar switch. (b) Percent error between traditional and proposed yield estimation methodologies.

curves. (In taking the ratio, the nonreconfigurable components of the two yield estimates will cancel.) Fig. 12(b) shows the overestimation error of yield estimated by the traditional method, as compared to the yield estimate of the proposed method. It can be seen from this graph that, in the case of the presented crossbar switch cell and reconfiguration scheme, traditional yield models can overestimate the yield of this IC by as much as 90% for typical present-day process defect densities.

V. A CAD TOOL FOR ACCURATE YIELD ESTIMATION

A. General Algorithm

The proposed yield-estimation methodology discussed in this paper separates the yield of a replicated cell into reconfigurable and nonreconfigurable components. In order to evaluate these components, every fault that can occur in a cell needs to be classified as being one of the two. This classification depends very much on the reconfiguration scheme in use. Once the faults are classified, the yield components can be easily calculated if the yield loss due to each fault is known.

Therefore, in order to compute yield accurately, the se- quence of operations shown in Fig. 13 must be performed. The first step of the algorithm shown in this figure is to identify

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28. NO. 2, FEBRUARY 1993

Ddcnnion of WBliTpbility of Erb Nodc

critical A m EsIiIMlim

Non-mfigurablc Yield Reconfigurable Yield

Computation of Tocal Yield

.1 T d Syseni Yicld

Fig. 13. Algorithm of the yield estimation tool needed for design of reconfigurable integrated circuits.

the properties of each node in a given circuit. Of importance is whether faults involving each node would have global or local effect. Once this has been determined for all nodes, critical area computation can be performed to assess the probabilities of occurrence of faults affecting each class of nodes. From this information, yields can be determined for the broad classes of “reconfigurable” and “nonreconfigurable” faults in the circuit.

B . Critical Area Component Extraction There are a number of possible methods to implement the

critical area computation step in the progression shown in Fig. 13. One method would be to perform a Monte Carlo simulation-placing defects randomly on the layout of the circuit and analyzing the electrical effects of the generated faults [22], [29]. This technique has the advantage that it is the most general, and that the probability distributions used to generate the defects for placement in the Monte Carlo loop can be simply customized to mimic many aspects of the expected defect characteristics. This approach, however, has its disadvantages, the main one being the enormous computation time required to place and analyze a statistically significant number of defects for a large cell layout. Therefore, in general, it is necessary to use a more direct method of computing the critical area for each fault class.

One such method is proposed in this paper. It was developed to handle bridging defects, and is based upon the algorithm summarized in Fig. 14. The basic steps in determining critical area for bridging faults between two nodes are: selection of all geometry connected to each node, expansion of this geometry by the defect radius, and finding the overlap of the expanded polygons. The overlap of the expanded polygons represents the critical area for extra material defects of a given radius that may short nodes within the circuit. From the geometry of the expanded polygons, it is also possible to directly determine

KHARE et al.: DEFECT-RELATED YIELD LOSS IN RECONFIGURABLE VLSI CIRCUITS 155

Fig. 14. Critical area extraction for accurate yield estimation.

which classes of nodes are involved in each potential short, and thus to separate the components of the critical area function.

Similar techniques [ 121 can be used to calculate the critical area related to missing material defects in a layout. This extraction, however, is in general more complicated than that for bridging faults, due to the fact that the occurrence of missing material defects can create new nodes in a circuit.

C. CAD Tool Implementation

To check the feasibility of the described concepts, a prototype CAD tool CAFE (Critical Area Function Extractor) was developed within the Cadence Edge design framework [ 11. This prototype is capable of separate critical area extraction for distinct classes of bridging faults within the interconnect layers of a design. It allows the user to interactively define classes of nodes in a circuit layout, and extracts critical area components accordingly. In Fig. 15, the implemented pseudocode for critical area extraction for two fault classes is shown. Note that, in this pseudocode, reconfigurable critical area is calculated by subtraction of global critical area from the total critical area. Note also that this approach builds critical area geometry one electrical net at a time. This provides the flexibility to divide the critical area function into as many classes as needed for a given circuit. The critical area graphs extracted for the two examples in this paper-the memory cell and the crossbar cell-were produced using CAFE. Fig. 16 shows an example output of the nonreconfigurable critical area geometry obtained using CAFE, for some layout.

D. Results of the Implementation Experiment

The implementation experiment showed that determining the reconfigurable and nonreconfigurable components of critical area geometry for even a simple layout may not be trivial, and therefore cannot be easily performed without appropriate CAD tools. The complexity of the algorithm implemented in CAFE for critical area extraction, however, was O(n2) , thus making it impractical for application to very large circuit

for R - minvalue to maxValue by stepsize 1

/ * Expansion of layout geometry */ foreach net i in layout->nets (

shapelist(i) grownSllapes(i) - Grow( shapelistti). R )

- all shapes in net i on layer of interest t

/ * Calculation of total critical area, Ai-total(R) * / CAgeometry - nil foreach net i in layout->nets I

otherGrownShapes - UNION( grownShapes(j) for all j # i ) OverlapGeometry - AND( shapelist (i), OtherGrownShapes ) CAgeometry - OR( CAgeometry, overlapGeametry 1

t Ai-total (RI - Area( CAgeometry / * Calculation of non-reconfigurable C.A., Aiglobal(R) * / CAgeometry - nil foreach net i in 1istOfGlobalNets I

OtherGrownShapes - UNION( grownShapes(j) for all j # i ) OverlapGeometry - AND ( shapelist (i), OtherGrownShapes CAgeometry - OR( CAgeometry. overlapGeornetry )

) Ai-global (RI - Area( CAgeometry )

/ * Calculation of reconfigurable C.A., Ai-local(R) * / Ai-local ( R ) - Ai-total I R ) - Ai-global ( R )

t

Fig. 15. Pseudocode for the critical area extraction algorithm.

Fig. 16.

Non-Reconfigurable Nodes in Metal 1

Reconfigurable Nodes in Metal 1

Criticol Area for Non-Reconfigurable Nodes

Nonreconfigurable critical area geometry for an example circuit, extracted using the presented algorithm.

designs. More efficient approaches (e.g., [IS]) will therefore be required in future for accurate yield analysis of coming large-area integrated circuits.

VI. SUMMARY AND CONCLUSIONS

In this paper, an accurate yield estimation methodology for reconfigurable circuits has been presented. The accuracy of this methodology stems from the ability to separately account for reconfigurable and nonreconfigurable faults within the replicated cell. As illustrated by the examples, the use of the proposed methodology instead of traditional methodologies will enable VLSI designers not only to accurately estimate the yield, but to also better evaluate design for manufacturability trade-offs in future systems.

In order to apply the proposed methodology, new CAD tools are needed, which are able to separately calculate the reconfigurable and nonreconfigurable critical area components and probability of failure of each fault class affecting a replicated cell. The feasibility of building these tools has been demonstrated in this paper through the implementation of the prototype tool, CAFE.

156 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 2, FEBRUARY 1993

ACKNOWLEDGMENT [25] C. H. Stapper, “The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions,” IBM J. Res. Develop., vol. 29, no. 1, pp. 87-97, Jan. 1985.

1261 Y. Takafuji et al., “A poly-Si TFT monolithic LC data driver with The authors would like to thank M. Patyra for providing the

layout of the crossbar example used in Section IV.

REFERENCES

Cadence Edge Integrated IC Design System, Reference Manual Set, Cadence Design Systems Inc., San Jose, CA, 1991. E. R. Dougherty, Probability and Statistics for the Engineering, Com- puting, and Physical Sciences. Englewood Cliffs, NJ: Prentice-Hall, 1990. A. V. Ferris-Prabhu, “Modeling the critical area in yield forecasts,” IEEE J . Solid-state Circuits, vol. SC-20, no. 4, pp. 874-878, Aug. 1985. A. V. Fenis-Prabhu, “Role of defects size distributions in defect modeling,” IEEE Trans. Electron Devices, vol. ED-32, no. 9, pp. 1727-1736, Sept. 1985. I. Fukushi et al., “A 256 kb ECL RAM with redundancy,” in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 134-135. B. Josbi et al., “A BiCMOS 50 MHz cache controller for superscalar microprocessors,” in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 110-1 11. J. Khare, W. Maly, S. Naik, and T. Storey, “Estimation of relative defect densities for a typical CMOS process,” Camegie Mellon Univ., Pittsburgh, PA, CMU-SRC Tech. Rep., 1992, in preparation. J. Khare, W. Maly, and M. E. Thomas, “Extraction of defect size distributions in an IC layer using test structure data,” submitted to IEEE Trans. Semicond. Manuf., 1991. S. Kikeda et al., “Optimized redundancy selection based on failure- related yield model for a 64-Mb DRAM and beyond,” IEEE J . Solid- State Circuits, vol. 26, no. 11, pp. 1550-1555, Nov. 1991. J. Labrousse and G. Slavenburg, “A 50 MHz microprocessor with VLIW architecture,” in ISSCC Dig. Tech. Papers, Dec. 1990. W. Maly and J. Deszczka, “Yield estimation model for VLSI artwork evaluations,” Electron. Len., vol. 19, no. 6, pp. 226227, Mar. 1983. W. Maly, “Modeling of lithography related yield losses for CAD of VLSI circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 161-177, Julv 1985.

[I31 W. Maly, “Fiasibility of large area integrated circuits,” in Wafer Scale Norwell, MA: Kluwer Academic, Intearation. E. Swartzlander. Ed.

I98i, pp. 31-56. W. Maly and P. Nigh, “Built-in current testing: Feasibility study,” in Proc. 1988 Int. Conf Computer-Aided Design, Nov. 1988, pp. 340-343. W. Maly, “Computer-aided design for VLSI circuit manufacturability,” Proc. IEEE, vol. 78, no. 2, Feb. 1990. W. Maly and P. Nigh, “Built-in current testing of integrated circuits,” U.S. Patent 5025344. 1990. T. L. Michalka, R. C. Varshney and J. D. Meindl, “A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy,” IEEE Trans. Semicond. Manuf., vol. 3 , no. 3, pp. 116127, Aug. 1990. P. K. Nag and W. Maly, “Yield estimation of VLSI circuits,” in Proc.

Y. Naruke et al., “A 16 Mb mask ROM with programmable redundancy,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 128-129. M. Patyra and W. Maly, “Circuit design for built-in current testing,” in Proc. IEEE Custom Integrated Circuits Conf., May 1991, pp. 13.4.1-13.4.5. M. Patyra and W. Maly, “Circuit design for a large area crossbar switch,” in Proc. IEEE Int. Workshop Defect and Fault Tolerance in V U 1 Syst., Nov. 1991, pp. 32-45. C. H. Stapper, A. N. McLaren, and M. Drekmann, “Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product,” IBM J. Res. Develop., vol. 24, no. 3, pp. 398-409, May 1980. C. H. Stapper, “Modeling of integrated circuit defect sensitivities,” IBM J. Res. Develop., vol. 27, no. 6, pp. 549-557, Nov. 1983. C. H. Stapper, “Modeling of defects in integrated circuit photolitho- graphic patterns,” IBM J. Res. Develop., vol. 28, no. 4, pp. 461474, July 1984.

TECHCON 90, Oct. 1990, pp. 267-270.

redundancy,” in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 118-1 19. [27] G. H. Teepe and W. L. Engl, “A bipolar correlator with redundancy,”

IEEE J . Solid-State Circuits, vol. SC-22, no. 6, pp. 1190-1195, Dec. 1987.

[28] R. M. Warner, Jr., “Applying a composite model to the IC yield problem,” IEEE J. Solid-state Circuits, vol. SC-9, no. 3, pp. 8 6 9 5 , June 1974.

[29] D. M. H. Walker, “Critical area analysis,” in Proc. 1992 Int. Conf Wafer Scale Integration, Jan. 1992, pp. 281-290.

1301 C. Wey, T. Chang, and J. Ding, “Design of fault-diagnosable and repairable folded PLA’s for yield enhancement,” IEEE J. Solid-state Circuits, vol. 26, no. 1, pp. 54-57, Jan. 1991.

5

Jitendra Khare (S’92) received the B.Tech. degree from the Indian Institute of Technology, Bombay, India, in 1987, and the M.S. degree from Camegie Mellon University, Pittsburgh, PA, in 1989. Presently he is pursuing the Ph.D. degree in electrical and computer engineering at Camegie Mellon University. He has also worked for nine months at the Fairchild Research Center of National Semiconductor, Santa Clara, CA, and has been a Visiting Scientist at Siemens Research Laboratory, Munich. Germanv. His research interests include

defect simulation and characterization, design for manufacturability, design for testability, and large-area integrated circuits.

burgh, PA, where he is

Derek B. I. Feltham (S’86) received the B.A.Sc. and M.A.Sc. degrees in engineering science and electrical engineering from the University of Toronto in 1985 and 1987, respectively, and the Ph.D. degree in electrical and computer engineering from Camegie Mellon University in Pittsburgh, PA, in 1992. He is currently working as a post-doctoral research assistant at Carnegie Mellon University. His ongoing research interests are in the areas of defect modeling, design for manufacturability, and design for testability of VLSI systems.

Wojciech Maly (M’8 I-SM’86F’91) received the M.Sc. degree in electronic engineering from the Technical University of Warsaw, Poland, in 1970, and the Ph.D. degree from the Institute of Applied Cybemetics, Polish Academy of Sciences, Warsaw Poland, in 1975.

From 1970 to 1973 he was with the Institute of Applied Cybernetics. In 1973 he joined the Techni- cal University of Warsaw, where he was appointed Assistant Professor in 1975. Since September 1983 he has been with Carnegie Mellon University, Pitts-

I Professor of Electrical and Computer Engineering.

Documents

Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits