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GENERATING REGULAR ARITHMETIC CIRCUITS WITHAlpHardPATRICIA LE MOENNER, LAURENT PERRAUDEAU,

PATRICE QUINTON, SANJAY RAJOPADHYE,TANGUY RISSET

INSTITUT DE RECHERCHE EN INFORMATIQUE ET SYSTEMES ALEATOIRES

Campus de Beaulieu – 35042 Rennes Cedex – FranceTel. : (33) 02 99 84 71 00 – Fax : (33) 02 99 84 71 71

http://www.irisa.fr

Generating Regular Arithmetic Circuits with AlpHardPatricia Le Moenner, Laurent Perraudeau,Patrice Quinton, Sanjay Rajopadhye,Tanguy RissetTh�eme 1 | R�eseaux et syst�emesProjet APIPublication interne n�1001 | March 1996 | 17 pagesAbstract: The e�cient vlsi implementation of arithmetics operators requires that designbe optimized, both by looking for e�cient algorithms, and by producing compact regularlayouts. We present AlpHard, a subset of Alpha { a language for the synthesis of regularalgorithms. AlpHard is intended for specifying the Register Transfer Level (RTL) repre-sentation of an architecture, in such a way that any regularity in the algorithm is preserved.An AlpHard description can be obtained as the result of a formal derivation process, thusenabling di�erent solutions to be found automatically from Alpha programs. In this paperwe demonstrate the e�ectiveness of AlpHard on the derivation of regular layouts for atwo's complement bit-serial multiplier.Key-words: high level synthesis, regular arrays, vlsi, arithmetic (R�esum�e : tsvp)To appear in the Proceedings of 2th International Conference on Massively Parallel Computing Systems(MPCS'96) { Ischia, Italy { 6-9 May 1996�This research is partly supported by CNET/France Telecom.��flemoennegfperraudegfquintongfrajopadhgfrissetg@irisa.fr

Centre National de la Recherche Scientifique Institut National de Recherche en Informatique(UPRESSA 6074) Universite de Rennes 1 – Insa de Rennes et en Automatique – unite de recherche de Rennes

G�en�erations de circuits arithm�etiques r�eguliers avecAlpHardR�esum�e : L'impl�ementation e�cace d'op�erateurs arithm�etiques n�ecessite d'optimiser leurconception en travaillant sur deux aspects : la recherche d'algorithmes e�caces et la pro-duction de dessins de masques r�eguliers compacts. Dans ce document nous pr�esentonsAlpHard, un sous-ensemble du langage Alpha utilis�e pour la synth�ese d'algorithmes r�egu-liers. AlpHard est con cu pour sp�eci�er des architectures au niveau transfert de registres(RTL) de telle mani�ere que la r�egularit�e des algorithmes initiaux est pr�eserv�ee. Une des-cription AlpHard peut etre le r�esultat d'un processus de d�erivation formelle. Cela rendpossible l'exploration syst�ematique de di��erentes solutions �a partir d'un programmeAlpha.Dans ce document nous d�emontrons l'e�cacit�e d'AlpHard pour la d�erivation de dessins demasques r�eguliers sur l'exemple d'un multiplieur bit-s�erie en compl�ement �a deux.Mots cl�es : synth�ese de haut niveau, architectures r�egulieres, vlsi, arithm�etique

Generating Regular Arithmetic Circuits with AlpHard 31 IntroductionDesigning high performance vlsi circuits for arithmetic requires many di�erent algorith-mic and architectural choices to be made. To reach such a goal, Computer Aided Design(CAD) tools must operate at the highest level of abstraction: executable speci�cations thatcan quickly re ect the algorithmic choices. A second key aspect of arithmetic circuits istheir inherent regularity which should be exploited at all levels in order to obtain e�cientsolutions. Although many vlsi design tools now operate on the behavioral VHDL levelof description, it is nevertheless not easy to explore di�erent algorithmic choices. Further-more, these tools usually operate by attening out descriptions and this prevents them fromexploiting regularity. In this paper, we present an attempt to solve these problems usingAlpHard, a regular vlsi description language developed at IRISA. AlpHard is a propersubset of Alpha [Mau89], a language based on systems of a�ne recurrence equations usedat IRISA for the systematic synthesis of regular arrays. While Alpha is intended for theinitial speci�cation and is a richer language, AlpHard is used to describe regular circuitswith local interconnections, and their control. It is intended to interface either with conven-tional vlsi CAD tools or layout editors that can exploit regularity such as MADMACS[Per93] or LILA [WCC95]. AlpHard draws upon the existing Alpha tools. In particular,it is possible to simulate the functionality of a given architecture written in AlpHard usingthe Alpha-to-C simulator. This allows us to verify the functionality at multiple levels ofabstraction.One of the motivations of AlpHard is the need to specify regular vlsi computationsat an algorithmic level of abstraction. As stated above, this is essential since we want toenable the user to easily explore di�erent choices. Secondly, the language must be closeenough to the hardware level so that it can be automatically translated into vlsi layouts.The contribution of this paper is thus a systematic and convenient exploration of designchoices and linkage of the resulting regular circuit descriptions to lower level CAD tools. Weillustrate this using a well known bit-serial two's complement multiplier.The remainder of the paper is organized as follows. In the following section, we presentan overview of the AlpHard language, with an emphasis on the hierarchical grouping ofcomponents, the separation of temporal aspects of cells, and the regular spatial instantia-tion of such cells. In Sec. 3 we present the AlpHard descriptions of the multiplier, andhighlight the main features. In Sec. 4 we brie y show how this description can be translatedmechanically into a description for MADMACS [Per93], a vlsi layout editor that exploitsregularity.2 AlpHardSystematic design of regular vlsi arrays has been an active research topic for a numberof years. The work at IRISA in this area is based on the speci�cation and transformationof recurrences [KMW67]. The initial algorithm is expressed in Alpha [Mau89], a func-tional language based on systems of a�ne recurrence equations. It permits a declarativePI n�1001

4 P. Le Moenner, L. Perraudeau, P. Quinton, S. Rajopadhye, T. Rissetspeci�cation of the algorithm, without implementation details such as sequential orderingand processor allocation. These aspects are deduced (semi) automatically and are used totransform the original Alpha program into an equivalent one which represents a systolicarray. This new Alpha program has one index dedicated to represent time, and has onlylocal dependencies. At this point, many low level details such as control signals, and RTLdescriptions of the processors need to be speci�ed explicitly. A subset, Alpha0 was de�nedby Dezan [Dez93] and extended by Si�e [Si�e95]. Recent improvements in the hierarchical des-cription of systems in Alpha [DQR95] has enabled us to develop a more powerful hardwaredescription language, AlpHard.AlpHard is intended to meet two important goals. First, AlpHard programs areobtained by automatic transformation of Alpha programs, and hence AlpHard must be acoherent subset of Alpha (however, a detailed discussion of this aspect is beyond the scopeof this paper). Second, the architectural description given by AlpHard must:� provide organization (because complex design process must be hierarchical);� provide genericity (in order to allow components to be reused);� express regularity of computations (so as to reuse hardware descriptions and simplifythe design process).2.1 Overview of AlpHard languageIn Alpha (and also AlpHard), every variable has a declared domain, i.e., the set of indexpoints where it is de�ned. The language semantics specify how the domains of all expressionscan be systematically determined, using well de�ned rules for manipulating polyhedra. Avery simple Alpha program can be seen in Fig. 1b: A,B are variables and t is the index oftheir domains.AlpHard is hierarchical. At the lowest level of description one has cells consisting ofcombinational circuits, registers, multiplexors, etc. A cell may also contain other cells. Atthe same level in the hierarchy, we may also have controllers responsible for initialization1.At this point we have a description of a piece of circuit that has no \spatial dimensions".It represents a single processing element which may later be instantiated at multiple spatiallocations.The next level of the hierarchy is the module which allows the user to specify howdi�erent cells are assembled regularly in one or more spatial dimensions. This is achieved byinstantiating previously declared cells. Typically, controllers are instantiated only once withno spatial replication. The separation of temporal and spatial aspects is also re ected in thefact that the equations describing the behaviour of cells have only one local index variable(time), and in the equations for modules, the dependencies have only spatial components,indicating pure (delayless) interconnections.1In systolic arrays, the control signals are themselves distributed in a regular fashion, and their data-pathcan also be described in terms of cells.Irisa

Generating Regular Arithmetic Circuits with AlpHard 5p=1 p=2 p=3A[t,1] B[t,1]=A[t,2]RegInvModule RegInvCellA1[t] B1[t]=notA1[t-1](a) A simple architecture of three identical cells Size=31 system RegInvCell:{Tinit,D|Tinit,D>=0}2 (A:{t|Tinit<=t<=Tinit+D} of boolean)3 returns (B1:{t|Tinit+1<=t<=Tinit+D+1}4 of boolean);5 let6 A[t] = not B1[t-1];7 tel;

...1 use {p|1<=p<=Size} RegInvCell2 [Tinit+p-1,D] (A) returns (B);3 A[t,p] = case4 {| p=1}: a[t];5 {| p>1}: B[t,p-1];6 esac; ...(b) De�nition of the cell (c) Its instantiation in a moduleFigure 1: An AlpHard program describing a simple cell, RegInvCell (b), and instantiationof Size copies of it in a module. Note how p is used to specify the value Tinit for eachinstance (the p-th cell starts p-1 cycles after the �rst).These ideas are illustrated in Fig. 1a, which shows a three-cell module, where each cellis a simple register-inverter. The AlpHard code corresponding to the cell de�nition is inFig. 1b, which shows that the system RegInvCell has two parameters (line 1) correspondingto its start time and its duration. Lines 2-4 are the declaration of input and output signalsof the cell, the domain between the braces represents the lifetime of signals A1 and B1. Theequation de�ning B1 (line 6) consists of an atomic function not and a variable A1 with adelay A1[t-1], and this implies a register. Notice that the only index appearing in theequation is time, t.Fig. 1c shows how RegInvCell is instantiated within a module. Multiple copies areinstantiated by means of the construct, use {p|1<=p<=Size}. Such a multiple instantiationalso means that the variables A and B will have two indexes, t (inherited from the RegInvCellde�nition) and p (from the multiple use in line 1). We also see that the value of theTinit parameter is instantiated as a function of p so that the cells start at di�erent timeinstants. Lines 3-6 specify the connections between the input/output of the cells, andillustrate the case construct, which allows us to describe the boundary processor. Noticehow the constraints in the case involve only spatial indices. Also note that the time index,t, is the same on both sides of the equation. These are two essential syntactic properties ofPI n�1001

6 P. Le Moenner, L. Perraudeau, P. Quinton, S. Rajopadhye, T. Rissetan AlpHard module|it speci�es how a collection of cells (or even other sub-modules) areassembled spatially.2.2 Multiplexers and feedbackAs noted above, the domains of all (sub) expressions in an AlpHard program can besystematically determined, using a library for manipulating polyhedra. This informationis used by the system to automatically type check an AlpHard program and ag anyinconsistencies. For example, the domain of the expression, B[t-1] on the rhs of line 6(Fig. 1b), can be deduced to be the domain of B, shifted right by 1. This matches thedeclared domain of A, and so the program is type-correct.Also note that in systolic arrays (the class of regular vlsi circuits to which AlpHardis geared) all the control information is known statically, and corresponds to a booleanpredicate involving linear (in)equalities on the space and time indices (i.e., whether thecurrent space-time indices belong to a given polyhedron or not). It is also known howthis information can be (semi) automatically transformed into propagating control signals[Raj89, TT91, Xue92]. As a result, it is statically possible to determine the instants whena given control signal will be true and when it will be false (the control signals are notdata-dependent).Furthermore, all atomic operators in Alpha are strict (including the if-then-elseconditional), and the domain of an expression (containing arbitrary combinations of atomicoperators and named variables) is the intersection of the domain of these variables.The above considerations need a special treatment of multiplexors in AlpHard, espe-cially when used in a feedback loop. Consider, a simple cell as shown in Fig. 2a. Our �rstinstinct would be to describe this as shown in Fig. 2b. However, this program is not typecorrect: the domain of S is the intersection of those of A, B and C, but the domain of B doesnot include t=0. Hence, S is unde�ned at t=0. However, it may well be the case that weknow a priori that C is false at t=0, and we would like to have S de�ned at t=0 (indeed,this may well be a circuit that initializes the register). The problem cannot be resolvedby simply changing the domain of B to include t=0, since this will make the equation online 8 inconsistent (B[0] will never be de�ned). The only construct that allows us to buildan expression whose domain is the union of the domains of its subexpressions is the case.Indeed, all that we need in order to describe \systolic" type control signals is an ability toname certain (sub) domains as corresponding to a control signal. Furthermore, note thatthe control signal for a multiplexer is always boolean, while the data may be declared to beeither real, integer or boolean. Since the only construct in the language which permitssuch a combination in a single expression is the conditional, we use the syntax shown inFig. 2c for multiplexers. There is an implicit assumption that the domain of the restriction(i.e., the constraints before the colon) corresponds to the indices where the control signal iseither true or false.Irisa

Generating Regular Arithmetic Circuits with AlpHard 7B

C

AS0

1(a) A simple circuit (b) Naive AlpHard description1 system MuxEx (A,C:{t|0<=t} of boolean)2 returns (S:{t|0<=t} of boolean);3 var B:{t|1<=t}of boolean;4 let5 B[t] = S[t-1];6 S = if C then B else A;7 tel;

...6a S = case6b {|t=0}: if not C then A else A;6c {| t >= 1}: if C then B else B;6d esac; ...(c) Actual AlpHard descriptionFigure 2: Multiplexers and feedback in AlpHard.3 Lyon's bit-serial multiplierWe now present the AlpHard speci�cation of a well-known two's complement bit-serialmultiplier, originally due to Lyon [Lyo76]. It is a classic sytolic array, although it evenpredates the work of Kung and Leiserson [KL80] who �rst introduced the phrase systolicarrays. It is implemented as a linear network of elementary boolean cells, as shown in �gure3.3.1 Algorithmic Description of the MultiplierConsider two numbers Y � [yn�1yn�2 : : : y0] and X � [xn�1xn�2 : : : x0]. Both numbers aretwo's complement representation of numbers, so that Y = �yn�12n�1 +Pn�2i=0 yi2i. Theoperation of the multiplier can be summarized as follows. Numbers X and Y enter the arrayleast signi�cant bit (lsb) �rst. The result Y �X is output at the right end of the array 2 �nclock cycles later. Only the n most signi�cant bits of the product are recovered (Lyon alsoPI n�1001

8 P. Le Moenner, L. Perraudeau, P. Quinton, S. Rajopadhye, T. RissetXYPR type IItype I type I type IFigure 3: Lyon's two's complement multipliershows how various rounding strategies may be implemented, but we will not address themhere). Two consecutive X numbers are separated by one (extra) clock cycle. The bits of Xtravel twice as slowly as the bits of Y , and each bit of X is aligned with a control signal, Rwhich is always 1 (true), except for the cycle associated with the lsb of X . For the purposeof the algorithm, we do a sign extension of each number X , i.e., we replicate its msb.Note that the control information is statically known and is independent of the data,and that the instants when the control signal is true can be expressed only in terms oflinear (in) equalities involving the processor and time coordinates. This control informationcan be summarized as follows: the p-th processor becomes active at t = 2p � 2 (using theconvention that the processors are numbered from 1 : : : n, and the �rst processor becomesactive at t = 0). Each processor remains active for n + 1 cycles. However, even though aprocessor becomes active at t = 2p � 2, the loading circuitry for the Y values propagatesthe Y faster than the control signal. Thus, processor p starts seeing the Y bits at t = p� 1,well before the control signal arrives (processor p is designated to load yp�1, and so thispropagation is irrelevant for correct operation).Because the numbers are two's complement, the multiplication of X and Y has twocomponents: computation of the product XPn�2i=0 yi2i, and the subtraction of the termXyn�12n�1. Each one of these phases is performed by a di�erent cell shown in �gure 4(a)and �gure 4(b). Type 1 cells compute XPn�2i=0 yi2i. There is one such cell for each binarydigit yi, i = 0 : : : n� 2. Each cell contains a full-adder, a 1-bit register containing the carry,a 1-bit register containing the yi digit, and a 1-bit register which is used for extending thesign of the partial sum, in order to have the correct two's complement representation forthe next stage. Digits xj ow from the left to the right. Finally, the cell is controlled bya boolean rj . Type 2 does the subtraction. Because of the 2's complement representation,this subtraction is done using the relation A�B = (B +A), hence the inverters in the cell.3.2 AlpHard Description of the MultiplierWe now present anAlpHard program that describes the behavior of the architecture duringthe multiplication of just one pair of integers (the repetitive reuse of this architecture is notdescribed). Note that this takes n+1 cycles, and the control signal is active during the �rstand last steps. Lyon's architecture very cleverly uses the same signal to overlap the last stepof one multiplication with the initialization of the processor for the next set of inputs.Irisa

Generating Regular Arithmetic Circuits with AlpHard 9full-adderTF FT

xj

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yirj

signextension full-adderFT(b) Type 2 cell

xjyirj

ps pspp ppFigure 4: Elementary cells of Lyon's multiplier: (a) cell of type I, used for computingXPn�2i=0 yi2i, (b) cell of type II, used for subtracting Xyn�12n�1The AlpHard description is given in appendix A. It directly re ects the structure of thearchitecture. The full-adder cell is described in subsection A.1. It is parametrized by its starttime, T, and the time for which it is active, Dur, and consists of the standard combinationallogic. Subsection A.2 shows the description of a type 1 cell (type 2 cell is omitted, but issimilar). Note how every declared variable in the program corresponds to a named signalin Fig. 4.a. This cell has three parameters: T1 corresponds to the arrival of y0, and T2 tothe time the processor becomes active (arrival of the control signal), and D is related to thetime for which it remains active on one set of numbers (i.e., n + 1). The cell contains afull-adder cell, instantiated by a use fullAdder statement (note how the initialization timeof the full-adder is set to T2+2 because one of the inputs of the full-adder comes from ppand thus the output X register { see 4.a) (Fig. 4.a shows how the pp input to. subsectionA.3 is the controller of the array. Finally, the entire design is shown in subsection A.4.4 Translation to Regular LayoutsWe now describe how theAlpHard program for the multiplier is systematically transformedinto a vlsi layout. We perform a \hand translation" here, though the ideas for automatingthe process are straightforward. The result of this translation is an input speci�cation forMADMACS [Per93], a regular layout editor developed at IRISA. The layout of the 8-bitbit-serial multiplier is given in Fig. 5. The translation proceeds in three steps.PI n�1001

10 P. Le Moenner, L. Perraudeau, P. Quinton, S. Rajopadhye, T. Risset

Figure 5: The layout of an 8-bit multiplier as generated by MADMACS. There are 7 cellsof type I and 1 cell of type IIFirst the netlist of a single cell is generated from the cellMultLyon1 and cellMultLyon2systems and the fullAdder cell that it instantiates. The connections between the cells arealso derived from the two systems, moduleMultLyon1.Next, MADMACS generates the layout of the cell using this netlist and a library ofstandard cells, connected by butting VDD and ground (see the vertical structures in Fig. 5).The placement of the standard cells is optimized to minimize the number of routing channelsinside the cell. The inputs of the cell are located at the top and the outputs are at the bottom.Finally, a number of cells (based on the parameters in the use statement in the toplevel AlpHard system) are placed and routed. The routing between each cell is realizedby the "snake-like" wires (see Fig. 5). This stage is trivial because the position of theinput/output connectors of the cell has been constrained during the previous step (to allowvertical abutment to be made).The advantages are the simpli�cation of the design due to regularity (design of only 2cells instead of 8) and the partial automation of the three steps that allow us to quicklyproduce various layouts and test di�erent topologies. For example, the layout of �g. 5 wasgenerated in a few seconds.Irisa

Generating Regular Arithmetic Circuits with AlpHard 115 ConclusionIn this paper we have presented the use of AlpHard, a new formalism for high level archi-tecture description, to model and design arithmetic circuits. AlpHard is intended to be astep in the semi automatic high level design process starting from an Alpha speci�cation,and generating vlsi layouts. We have detailed here the low level design part, and we haveillustrated our method by describing the design of a two's complement bit-serial multiplier,including the vlsi layout generation using the MADMACS tool [Per93].The main di�erence between our design process, as compared to other regular vlsisynthesis design methods and systems [CvRD92, EPP93], is that we preserve regularityinformation throughout the process. Because of this, the design is accelerated and theresulting layout is more compact (a completely automatic tool will not \�nd back" theregularity properties from a attened description of the architecture). Of course, this isachieved at the expense of narrowing the domain of applicability. Another positive aspectof this approach is the ability to simulate the functionality of the architecture and to testseveral algorithmic choices for the design. Finally, the high level approach allows one totarget di�erent architecture styles such as custom vlsi, FPGAs, etc.We have shown the result of this design process on Lyon's bit-serial multiplier. A similarresult could be obtained with layout editors that take regularity into account. We arecurrently investigating the translation ofAlpHard to a synthesizable subset of VHDL, usingthe generate instruction to express the regularity properties. This will allow AlpHard tocommunicate with existing logic synthesizers.It should be emphasized that AlpHard is more than "another Hardware DescriptionLanguage". Indeed, being a subset of Alpha, it can be used to describe the implementationof a component within a complete system whose behaviour can be expressed in full Alpha.This possibility allows various designs to be derived and simulated.The increasing demand for massive computations in embedded systems in general andsignal processing in particular, will soon require rapid design process for dedicated archi-tectures, including the possibility of exploring alternative implementations of arithmeticoperations. We believe that it can be obtained with semi-automatic high level synthesisapproach as such the case presented here.References[CvRD92] F. Catthoor, M. van Swaaij, J. Rosseel, and H. De Man. Array design methodolo-gies for real-time signal processing in the catthedral-iv synthesis environnement.In P. Quinton and Y. Robert, editors, Algorithms and Parallel VLSI ArchitecturesII, pages 211{222. Elseiver, Amsterdam, 1992.[Dez93] Catherine Dezan. G�en�eration automatique de circuits avec alpha du centaur.Th�ese de l'universit�e de Rennes I, February 1993.PI n�1001

12 P. Le Moenner, L. Perraudeau, P. Quinton, S. Rajopadhye, T. Risset[DQR95] F. Dupont De Dinechin, P. Quinton, and T. Risset. Structuration of the alphalanguage. In W.K Giloi, S. Jahnichen, and B.D. Shriver, editors, Massively Pa-rallel Programming Models, pages 18{24. IEEE Conmputer Society Press, 1995.[EPP93] Ed F. Deprettere, Peter Held, and Paul Wielage. Model and methods for regu-lar array design. International Journal of High Speed Electronics and Systems,4(2):133{201, 1993.[KL80] H. T. Kung and C. E. Leiserson. Algorithms for VLSI Processor Arrays, chapter8.3, `Introduction to VLSI Systems,' Mead, C. and Conway, L., pages 271{292.Addison-Wesley, Reading, Ma, 1980.[KMW67] R. M. Karp, R. E. Miller, and S. V. Winograd. The organization of computationsfor uniform recurrence equations. JACM, 14(3):563{590, July 1967.[Lyo76] R. F. Lyon. Two's complement pipeline multipliers. IEEE Trans. Comm., COM-24:418{425, April 1976.[Mau89] Christophe Mauras. Alpha : un langage �equationnel pour la conception et laprogrammation d'architectures systoliques. Th�ese de l'universit�e de Rennes I,December 1989.[Per93] Laurent Perraudeau. Madmacs : un outil pour le dessin des masques de r�eseauxr�eguliers int�egr�es. Th�ese de l'universit�e de Rennes I, September 1993.[Raj89] S. V. Rajopadhye. Synthesizing systolic arrays with control signals from recur-rence equations. Distributed Computing, 3:88{105, May 1989.[Si�e95] Oumarou Si�e. Generation automatique de dessins de masques de circuits r�eguliersint�egr�es. Th�ese de l'universit�e de Rennes I, January 1995.[TT91] J. Teich and L. Theile. Control generation in the design of processor arrays.Journal of VLSI Signal Processing, 3(1/2):77{92, June 1991.[WCC95] Q. Wu, C. Y. R. Chen, and B. S. Carlson. LILA: Layout generation of iterativelogic arrays. IEEE Trans. on Computer Aided Design of Integrated Circuits andSystems, 14(11):1359{1369, November 1995.[Xue92] J. Xue. The Formal Synthesis of Control Signals for Systolic Arrays. PhD thesis,University of Edinburgh, April 1992.A AlpHard Program for the Lyon MultiplierA.1 Full-Addersystem fullAdder:{T,Dur|} (AIn,BIn,DIn:{t|T<=t<=T+Dur} of boolean) Irisa

Generating Regular Arithmetic Circuits with AlpHard 13returns (SOut,DOut:{t|T<=t<=T+Dur} of boolean);letSOut[t]=AIn[t] xor BIn[t] xor DIn[t];DOut[t]=(AIn[t] and BIn[t]) or (AIn[t]and DIn[t]) or (BIn[t] and DIn[t]);tel;A.2 Type 1 cellsystem cellMultLyon1:{T1,T2,D|D>0~;T1<=T2}(YIn:{t|T1<=t<=T1+D-1} of boolean;XIn:{t|T2<=t<=T2+D}of boolean;RIn:{t|T2<=t<=T2+D+1}of boolean;PsIn:{t|T2+2<=t<=T2+2+D} of boolean)returns(YOut :{t|T1+1<=t<=T1+D} of boolean;XOut:{t|T2+2<=t<=T2+2+D}of boolean;ROut:{t|T2+2<=t<=T2+3+D}of boolean;PsOut:{t|T2+4<=t<=T2+4+D}of boolean);varCarBis,YMux:{t|T2+1<=t<=T2+1+D} of boolean;Car,CReg,YReg,mult,FA: {t|T2+2<=t<=T2+2+D} of boolean;RLoc:{t|T2+1<=t<=T2+2+D} of boolean;PsMux:{t|T2+3<=t<=T2+3+D} of boolean;let-- local values of the signalsRLoc[t] = RIn[t-1];-- mux and feedback for YYMux[t] =case{|t = T2+1} : if (not RLoc[t]) then YOut[t] else False[];{|T2+2<=t<=T2+D+1} : if RLoc[t] then YReg[t] else False[];esac;YReg[t] = YMux[t-1];-- bit level multiplicationmult[t] = YReg[t] and XOut[t];-- initialization and (indirect) feedback of the carryCarBis[t] =case{|T2+1=t} : if (not RLoc[t]) then RLoc[t] else False[];PI n�1001

14 P. Le Moenner, L. Perraudeau, P. Quinton, S. Rajopadhye, T. Risset{|T2+2<=t<=T2+D+1}: if RLoc[t] then Car[t] else False[];esac;CReg[t] = CarBis[t-1];-- full-adderuse fullAdder [T2+2,D] (mult,PsIn,CReg) returns (FA,Car);-- result of the full-adder or extension of last cell's addPsMux[t] =case{|T2+2<=t<=T2+2+D} : if ROut[t] then FA[t] else False[];{|T2+3+D = t} : if (not ROut[t])then PsOut[t] else False[];esac;-- outputs of the cellXOut[t] = XIn[t-2];YOut[t] = YIn[t-1];ROut[t] = RLoc[t-1];PsOut[t] = PsMux[t-1];tel;A.3 Initialization of the control of the multipliersystem controlMultLyon:{T,Dur|Dur>1} ()returns(RInit: {t|T<=t<=T+Dur+1} of boolean);letRInit[t]=case{| T=t} : False[];{| T+1<=t<=T+Dur} : True[];{| t = T+Dur+1} : False[] ;esac;tel;A.4 Lyon's multipliersystem moduleMultLyon:{T,NbP| NbP > 1}(Y:{t,p|T<=t<=T+NbP-1;p=1} of boolean;X:{t,p|T<=t<=T+NbP; p=1} of boolean)returns (P:{t,p| T+2NbP+1<=t<=T+3NbP; p=NbP}of boolean);var-- local variables of the system Irisa

Generating Regular Arithmetic Circuits with AlpHard 15YIn1:{t,p|T+p-1<=t<=T+p-2+NbP;1<=p<=NbP-1} of boolean;YOut1:{t,p|T+p<=t<=T+p-1+NbP; 1<=p<=NbP-1} of boolean;YIn2:{t,p|T+p-1<=t<=T+p-2+NbP; p=NbP} of boolean;YOut2:{t,p|T+p<=t<=T+p-1+NbP; p=NbP} of boolean;RInit:{t|T<=t<= T+NbP+1} of boolean;RIn1:{t,p|T+2p-2<=t<=T+2p-1+NbP; 1<=p<=NbP-1} of boolean;ROut1:{t,p|T+2p<=t<=T+2p+NbP+1; 1<=p<=NbP-1} of boolean;RIn2:{t,p|T+2p-2<=t<=T+2p-1+NbP; p=NbP} of boolean;ROut2:{t,p|T+2p<=t<=T+2p+NbP; p=NbP} of boolean;XIn1:{t,p|T+2p-2<=t<=T+2p-2+NbP; 1<=p<=NbP-1} of boolean;XOut1:{t,p|T+2p<=t<=T+2p+NbP; 1<=p<=NbP-1} of boolean;XIn2:{t,p| T+2p-2<=t<=T+2p-2+NbP; p=NbP} of boolean;XOut2:{t,p|T+2p<=t<=T+2p+NbP; p=NbP} of boolean;PsIn1:{t,p|T+2p<=t<=T+2p+NbP; 1<=p<=NbP-1} of boolean;PsOut1:{t,p|T+2p+2<=t<=T+2p+2+NbP; 1<=p<=NbP-1} of boolean;PsIn2:{t,p|T+2p<=t<=T+2p+NbP; p=NbP} of boolean;PsOut2:{t,p|T+2p+1<=t<=T+2p+NbP; p=NbP} of boolean;let-- instantiation of controluse controlMultLyon[T,NbP] () returns(RInit);--instantiation of NbP-1 cells of type Iuse{p|1<=p<=NbP-1} cellMultLyon1 [T+p-1,T+2p-2,NbP](YIn1,XIn1,RIn1,PsIn1) returns(YOut1,XOut1,ROut1,PsOut1);-- instantiation of one cell of type IIuse{p|NbP=p} cellMultLyon2 [T+p-1,T+2p-2,NbP](YIn2,XIn2,RIn2,PsIn2) returns(YOut2,XOut2,ROut2,PsOut2);-- control's connectionsRIn1[t,p] =case{| p=1} : RInit[t];{| 2<=p<=NbP-1} : ROut1[t,p-1];esac;RIn2[t,p] = ROut1[t,p-1];-- local connections between cellsXIn1[t,p] =case{| p=1} : X[t,p];{| 2<=p<=NbP-1} : XOut1[t,p-1];PI n�1001

16 P. Le Moenner, L. Perraudeau, P. Quinton, S. Rajopadhye, T. Rissetesac;YIn1[t,p] =case{| p=1} : Y[t,p];{| 2<=p<=NbP-1} : YOut1[t,p-1];esac;PsIn1[t,p] =case{| p=1} : 0[];{| 2<=p<=NbP-1} : PsOut1[t,p-1];esac;XIn2[t,p] = XOut1[t,p-1];YIn2[t,p] = YOut1[t,p-1];PsIn2[t,p] = PsOut1[t,p-1];-- identification of the circuit exitP[t,p]= PsOut2[t,p];tel;-- abstract description of links between the host and the circuit-- two numbers of NbD digits are given-- result is one number of NbD digitssystem interfaceMultLyon: {T,NbD|NbD>1}(y,x:{i| 0 <=i<= NbD-1} of boolean)returns(p:{i|NbD<=i<=2NbD-1}of boolean);varY:{t,p|T<=t<=T+NbD-1; p=1} of boolean;X:{t,p|T<=t<=T+NbD; p=1} of boolean;P:{t,p|T+2NbD+1<=t<=T+3NbD; p=NbD} of boolean;letuse moduleMultLyon[T,NbD] (Y,X) returns (P);Y[t,p] =case{|T <= t <= T+NbD-1}: y[t-T];{|T+NbD <= t} : 0[];esac;X[t,p] =case{|T <= t <= T+NbD-1}: x[t-T];{|T+NbD = t} : x[t-T-1];Irisa

Generating Regular Arithmetic Circuits with AlpHard 17{|T+NbD < t} : 0[];esac;p[i]={|NbD<=i<=2NbD-1}:P[T+NbD+1+i,NbD];tel;

PI n�1001