Logic Design - 2

جامعة المنوفية

Second Year (First Semester)

Dr. Hamdy M. Mousa

MENOUFIA UNIVERSITY

FACULTY OF COMPUTERS AND INFORMATION

LECTURE ONE

PROGRAMMABLE

LOGIC

LOGIC DESIGN-1

Remember & Review

Digital Logic

programmable logic device

• Programmable Logic Devices (PLDs) are

ICs with a large number of gates and flip

flops.

– that can be configured with basic software to

perform a specific logic function or perform

the logic for a complex circuit.

• Programmable Logic Device (PLD) is an

integrated circuit with internal logic gates

that are connected through electronic

fuses.

programmable logic device

• The gates in a PLD are divided into an

AND array and an OR array

– that are connected together to provide an

AND-OR sum of product implementation.

• PLD manufacturers include, among

others, Altera Corporation, Xilinx Inc., and

Lattice Semiconductor, Cypress

Semiconductor, Atmel, Actel, Lucent

Technologies, and Quick Logic.

Advantages to PLDs

Reduced complexity of circuit boards

• Lower power requirements

• Less board space

• Simpler testing procedures

Higher reliability

Design flexibility

Programmable Arrays

• All PLDs consist of programmable arrays.

• A programmable array is essentially a grid

of conductors that form rows and columns

with a fusible link at each crosspoint.

• Arrays can be either fixed or programmable.

The Most Popular Types Of PLDs

• Simple programmable logic devices (SPLDs)

• Programmable Read-Only Memory (PROM)

• Programmable array logic (PAL)

• Programmable logic array (PLA)

• Generic array logic (GAL)

• Complex programmable logic devices (CPLDs)

• FPGA (field-programmable gate arrays)

• FPIC (field-programmable interconnect)

Programmable Read-Only Memory

(PROM)

• The PROM consists of a set of fixed

(nonprogrammable) AND gates connected as a

decoder and a programmable OR array.

Programmable Logic Array (PLA)

• The PLA is a PLD that consists of:

– programmable AND array and

– programmable OR Array.

Programmable Array Logic (PAL)

• The PAL is a PLD that was developed to overcome

certain disadvantages of the PLA, such as longer delays

due to the additional fusible links that result from using

two programmable arrays and more circuit complexity.

• The basic PAL consists of a programmable AND array

and a fixed OR array with output logic,

Generic Array Logic (GAL)

• The recent development in PLDs is the GAL.

• The GAL, like the PAL, has a programmable AND array

and a fixed OR array with programmable output logic.

• Two main differences between GAL and PAL devices are:

(a) the GAL is reprogrammable

(b) the GAL has programmable output configurations.

PAL Operation

• The PAL consists of a programmable array of AND gates

that connects to a fixed array of OR gates.

• This structure allows any sum-of-products (SOP) logic

expression with a defined number of variables to be

implemented.

PALs have a one time programmable (OTP) array, in which fuses are

permanently blown, creating the product terms in an AND array.

Simplified Diagram

• PALs can be represented with a simplified diagram. A single line can represent multiple gate inputs.

X

X

X

X

2

2

Input buffer A A B B

Single line with slash

indicating multiple AND

gate inputs

Fuse blown

Fuse intact

AB

AB

AB + AB

Example

Indicate how a PAL is programmed for the following 3-

variable logic function:

ACBACBACBAX

Types of PAL Output Logic

• Combinational output:

– This output is used for an SOP function and is usually

available as either an active-LOW or an active-HIGH

output.

• Combinational input/output (I/O):

– This output is used when the output function must

feedback to be an input to the array or be used to make

the I/O pin an input only.

• Programmable polarity output:

– This output is used for selecting either the output

function or its complement by programming the

exclusive-OR gate for inversion or non-inversion.

PAL output logic

Combinational tristate output

Programmable polarity output

The fusible link is blown

open for inversion and

left intact for non

inversion.

Combinational input/output (active-LOW).

Standard PAL Numbering

Standard PALs come in a variety of configurations, each of which is identified by a unique part number. Example of a part number:

PAL10L8

Programmable

array logic Ten inputs

L—active-LOW,

H—active-HIGH, or

P—programmable polarity

Eight output

GAL Operation • The GAL consists of a reprogrammable array of AND

gates that connects to a fixed array of OR gates, , and

programmable output logic.

• This structure allows any sum-of-products(SOP) logic

expression with a defined number of variables to be

implemented.

Example

GAL is programmed to implement the following

2-variable logic function:

Input buffer

On

Example

GAL is programmed to implement the following 3-

variable logic function:

The GAL Block Diagram

• The AND array outputs go

to the Output Logic Macro

Cells (OLMCs),

– which contain the OR gates

and programmable logic.

– A typical GAL has n 8 and m

8.

• The OLMC is made up of

logic circuits that can be

programmed as either

combinational logic or as

registered logic.

• The OLMC provides much

more flexibility than the

fixed output logic in a PAL.

• OLMC can be configured either for

• combinational output or

• input or

• for a registered output.

– It can be programmed for either an active-

HIGH or an active-LOW output. Also, each

OLMC can be programmed as an input.

PALs & GALs

• The PAL16V8 is a typical SPLD. There are 16 pins that can be used as inputs and 8 pins that can be used as outputs. I/O pins are counted as both inputs and outputs.

7Macrocell

7Macrocell

7Macrocell

7Macrocell

7Macrocell

7Macrocell

7Macrocell

7Macrocell

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

O1

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

O2

Programmable

AND array

The GAL22V10 OLMC

The four OLMC configurations

Active-LOW output:

S1 =1, S0=0

Active-HIGH combinational:

S1 =1, S0=1

1. Combinational mode with active-LOW output

2. Combinational mode with active-HIGH output

3. Registered mode with active-LOW output

4. Registered mode with active-HIGH output

Two Main Categories PLDs

• Two main categories of the PLDs:

–the simple programmable logic devices

(SPLDs). {i.e. PAL, and GAL }

–the high capacity programmable logic

devices (HCPLD), which classified into

two main categories;

• CPLDs and

• field programmable gate arrays (FPGAs).

Complex Programmable Logic Devices

• CPLD is a logic device that consists of multiple SPLDs

interconnected on a single chip.

– CPLDs can be used to implement large logic functions, including shift

registers.

• A CPLD basically consists of multiple group of PAL/GAL-like

arrays with programmable interconnections

Logic Array Block

• Each PAL/GAL group is called a logic

array block (LAB).

– Each LAB contains several PAL/GAL-like

arrays called macrocells,

– can be interconnected with other LABs or to

other I/Os using the programmable

interconnect array (PIA) to form large complex

logic functions.

– The CPLD is based on SOP architecture.

CPLD A complex programmable logic device (CPLD) has multiple logic array blocks (LABs) that are actually SPLDs on a single IC.

LABs are connected via a programmable interconnect array (PIA). Various CPLDs have different structures for these elements.

The PIA is the

interconnection between

the LABs. Logic is fitted

to the CPLD and routing

is determined by a high-

level programming

language called a

hardware description

language (HDL).

I/O

PIA

I/O

I/O I/O

I/O I/O

Logic array

block (LAB)

SPLD

Logic array

block (LAB)

SPLD

Logic array

block (LAB)

SPLD

Logic array

block (LAB)

SPLD

Logic array

block (LAB)

SPLD

Logic array

block (LAB)

SPLD

CPLD Architecture

The architecture of a CPLD is the way in which the internal

elements are configured. A portion of the Altera MAX 7000

series is shown. This structure is typical for CPLDs

although densities, size, speed, and internal factors

(macrocells, etc) will vary between manufacturers.

I/O pins I/O pins

General-purpose inputs

8-168Ð16 36

16

I/Ocontrolblock

Logic array block(LAB A)

36

16

I/Ocontrolblock

Macrocell 1

Macrocell 2

Macrocell 16

Logic array block(LAB B)

Macrocell 1

Macrocell 2

Macrocell 16

8-168-16

PIA

Basic CPLD macrocell

Programmable interconnect array (PIA)

• The PIA consists of conductors that run

throughout the CPLD chip and to which

connections from the macrocells in each

LAB can be made.

• By using the PIA, any macrocell can be

connected to other macrocells within

the same LAB, to macrocells in other

LABs in the device, or to other I/Os.

Field Programmable Gate Array (FPGA)

• The FPGA basically consists of an array of logic

blocks with programmable row and column

interconnecting channels surrounded by

programmable I/O blocks

• Many FPGA architectures are based on a type

of memory called an LUT (look-up table) rather

than on SOP AND/OR array as CPLDs are.

• Another approach found on some FPGAs is the

use of multiplexers to generate logic functions.

FPGA Block Diagram

FPGA • A field programmable gate

array (FPGA) uses a different

architecture than a CPLD.

The configurable logic block

(CLB) is the basic element

which is replicated many

times.

• CLBs are arranged in a row

and column structure. Within

the CLBs are logic modules

joined by local interconnects.

• Generally, the logic modules

are composed of a look-up

table (LUT), a flip-flop, and a

MUX that can be used to

bypass the flip-flop for strictly

combinational logic.

CLB

Logic module

Localinterconnect

Global columninterconnect

Logic module

Logic module

Logic module

CLB

Logic module

Localinterconnect

Logic module

Logic module

Logic module

Global rowinterconnect

The Look-up table

• LUT used in FPGAs is actually a memory

device that can be programmed to perform

logic functions.

• The LUT essentially replaces the AND/OR

array logic in a CPLD.

Look-up Table based FPGA

• Look-up Table

– Truth table implemented in hardware

– Can implement arbitrary function with fixed number of inputs

(typically 4-5) by programming the storage bits (customizing the

truth table)

F = x1’x2’ + x1x2

x1 x2 F

0 0 1

0 1 0

1 0 0

1 1 1

2-Input LUT 0/1

x1 x2

0/1

0/1

0/1

F

1

0

0

1

Programming bit P

LUT

Example: – LUT can be used to perform a logic function,

– 8x1 memory programmed to produce the SOP function

8x2 LUT

Example: 8x2 LUT is programmed as a full adder