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TABLE OF CONTENTS
List of Figure......................................................................................................................iii
List of Table.........................................................................................................................v
CHAPTER 1........................................................................................................................1
INTRODUCTION.........................................................................................................1
1.1 Overview of CMOS Low- Noise Amplifier for Ultra- Wideband
Applications................................................................................................................................1
1.2 Problem statement...............................................................................................2
1.3 Objective...............................................................................................................3
1.4 Scope......................................................................................................................3
CHAPTER 2........................................................................................................................4
LITERATURE REVIEW.............................................................................................4
2.1 Ultra Wideband Applications.............................................................................4
2.2 Low- Noise Amplifier Blocks..............................................................................5
2.3 The Metal–oxide–semiconductor field-effect (MOSFET) Theory........................6
2.4 Noise Figure...........................................................................................................7
2.5 Filter.......................................................................................................................8
2.5.1 Types of filter...................................................................................................8
2.6 LNA Topology.....................................................................................................10
2.7 Comparison of Published LNA for UWB Application Works............................11
CHAPTER 3......................................................................................................................14
METHODOLOGY......................................................................................................14
3.1 General Utilizing of Virtuoso Schematic Editor..................................................14
3.2 Schematic Design Process Flow..........................................................................15
i
3.3 Schematic Design.................................................................................................17
3.4 Circuit Simulation Using Spectre RF...................................................................19
CHAPTER 4......................................................................................................................20
RESULT.......................................................................................................................20
4.1 S- Parameter Analysis..........................................................................................20
REFERENCE....................................................................................................................22
ii
LIST OF FIGURE
Figure 1.1: Low noise amplifier (LNA) location inside wireless circuit.............................2
Figure 2.1: Block Diagram of Functional LNA...................................................................5
Figure 2.3: Cross section of MOS structure........................................................................7
Figure 2.5: Basic filter responses…………………………………………………………9
Figure 2.6 : Schematic of cascade feedback LNA……………………………………….11
Figure 2.7: Circuit of two-stages cascade CMOS LNA……………………...………….12
Figure 3.3 : Designed schematic of LNA………………………………………………..17
Figure 3.4: Simulation setup in Spectre- RF……………………………………………..19
Figure 4.1: Simulated waveform…………………………………………………………20
iii
iv
LIST OF TABLE
Table 1.7: Comparisons of published works of UWB LNAs...........................................13
Table 2 : Summary of result waveforms...........................................................................21
v
CHAPTER 1
INTRODUCTION
1.1 Overview of CMOS Low- Noise Amplifier for Ultra- Wideband Applications.
Recently, there is growth in demand for ultra- wideband (UWB) which is a wireless
technology useful in delivering high digital data rate over wide spectrum of frequency bands [1].
The advantages offered by UWB are abilities to operate in distance of 230 feet at very low power
and it’s robustness in obstructed environments. The frequency set in America by Federal
Communications Commission (FCC) for UWB techniques is from 3.1GHz to 10.6GHz [2].
UWB’s spectrum can work in unison with other licensed spectrum users thus make it as an ideal
choice in a wide range of applications mainly in medical and military fields.
Low noise amplifier (LNA) is conventionally used in all wireless applications. Based on
Figure 1.1, LNA is placed in receiver most front ends in- between Band Selection Filter and
Image Rejection filter. The function of LNA is to provide signal amplifying without giving much
noise, as the name suggested. However, the flatness gain for LNA is quite difficult to achieve in
ultra wideband range. Therefore, high flatness gain LNA is very important to ensure constant
gain during transferring the signals.
1
Figure 1.1: Low noise amplifier (LNA) location inside wireless circuit.
In this project, a CMOS LNA with high gain flatness for UWB applications is
designed and simulated by using CMOS 0.13-um process. It is based on a cascade feedback
topology which has several advantages such as a higher gain and a wider bandwidth.
.
1.2 Problem statement
The Low Noise Amplifier (LNA) is a core block of an Ultra Wide Band (UWB) receiver
since it amplifies a very weak signal received at the antenna to acceptable levels while
introducing less self-generated noise and distortions. However, the LNA design poses a unique
challenge as it requires simultaneous optimization of various performance parameters like power
gain, input matching, noise figure, power consumption and linearity over the entire UWB band.
Furthermore, the flatness gain for LNA is quite difficult to achieve in ultra wideband range.
Therefore, high flatness gain LNA is very important to ensure a constant gain during transferring
the signals.
2
1.3 Objective
The main aim for this project is to design a low noise amplifier, which required to have a
low noise figure with good input matching and excellent gain flatness in the wide frequency
range of operation from 3- 5 GHz. The CMOS LNA will be designed and simulated by using
CMOS 0.13-um process. The objectives of the task undertaken are:
• To propose 3-5 GHz CMOS LNA for UWB applications.
• To design and simulate the proposed LNA using EDA tools.
• To analyse the LNA performance and compare it with previous LNA works.
• To design the layout for LNA’s chip size estimation
1.4 Scope
The project is based on circuit design which is the proposed LNA will be designed and
simulated using electronic design automation (EDA) tool. The simulation results will be
analysed by comparing with previously published works of UWB LNA. The layout is designed
for chip size estimation. The DRC and LVS of the circuit will not be performing in the project
due to the time limitation.
3
CHAPTER 2
LITERATURE REVIEW
2.1 Ultra Wideband Applications
UWB short-range wireless communication offered different characteristics compared to a
traditional carrier wave system. UWB waveforms are short time duration and have some rather
unique properties. In spreading signals over very wide bandwidths, the UWB concept is
particularly appealing since it facilitates optimal sharing of a given bandwidth between
distinctive systems and applications. Recent years, advanced developments have been
experimented on using UWB signals as communication technologies.
UWB technology offer major enhancements in three wireless application areas:
communications, radar and positioning or ranging. UWB also is used as the communication link
in a sensor network. A UWB sensor network frees the patient from the tangle of wired sensors.
Sensors are being used in medical situation to determine pulse rate, temperature, and other
critical life signs. UWB is used to transport the sensor information without wires, but also
function as a sensor of respiration, heartbeat, and medical imaging. In addition, UWB technology
can be delivered also over wire lines and cables such as CATV application. Each of these
applications outlined the distinctive advantages of UWB [9].
4
2.2 Low- Noise Amplifier Blocks
In wireless design, low- noise amplifier (LNA) is a critical interface between the antenna
and the electronic circuits. Positioned at the front end of the receiver channel, LNA amplifies
very weak signals so that the output signal has reduced of unwanted background noise. After the
extraction and amplification, the signal is now capable of being processed by the blocks that
located further down the receiver chain. Some aspects that must be take into account while
designing amplifier and measure performance amplification process are power dissipation,
supply voltage, linearity and noise. In addition, input and output impedance also play some role
to determine how the circuit interact leading and lagging stages. Figure 2.2 shows block
diagram of a functional LNA.
Figure 2.1: Block Diagram of Functional LNA
5
2.3 The Metal–oxide–semiconductor field-effect (MOSFET) Theory.
An MOS (Metal-oxide semiconductor) structure is created by utilizing several layers of
conducting and insulating materials to form a sandwich- like structure. Structure are build using
a series of chemical process steps involving oxidation of the silicon, the diffusion of impurities
into silicon to give it certain conduction characteristic and lastly deposition and etching of metals
to provide interconnection in the same way that a printed wiring board is constructed.
CMOS technology equip two type of transistor: an n-type transistor(nMOS) and p-type
transistor (pMOS). The operation of a transistor are based on electric fields. The cross section of
nMOS and pMOS are shown in Figure 2.3. Each transistor consists of conducting gate, silicon
wafer that called as bulk, substrate or body and insulating layer of silicon dioxide (SiO2). For
nMOS transistor it is built with a p-type body and has region of n-type semiconductor beside to
the gate called the source and drain. The bulk is typically grounded. While a pMOS transistor
opposite from nMOS construction, consisting of p-type source and drain regions with an n-type
body.
For an nMOS transistor operation, the body are grounded so the p-n junction of the
source and drain to body operate in reversed bias. The gate acts as control input. It controls the
flow of electrical current between the source and drain. The gate is not grounded so the current
can operate as mention above. So, the transistor are in OFF condition. For tune-up transistor so
it is in ON condition, gate voltage is raised, so it create an electric filed that start to attract free
electron to the side of Si-SiO2 interface.. If the voltage raised enough, the electrons outside the
holes and a thin region under the gate inverted to act as n-type semiconductor. A conducting path
of electron carrier is formed from source to drain so the current can flow and the transistor is in
ON condition.
The operation of pMOS transistor is opposite to the nMOS operation. The bulk or body
held at a high potential. When the gate is also at high potential, the source and drain junctions are
reversed biased and no current flows so the transistor is OFF. When the voltage at gate is
lowered, positive charge are attracted to the underside of Si-SiO2 interface. A sufficiently low
gate voltage inverts the channel and a conducting path of positives carrier is formed from source
to drain, so the transistor is in the ON condition.
6
Figure 2.3: Cross section of MOS structure
2.4 Noise Figure
A parameter called noise figure (NF) is a commonly used method of specifying the
additive noise inherent in a circuit or system. The parameter is used only in the situation which
the sources impedance is resistive. However, it is often the case in a front end, and so this
method of specifying noise is adopted here.
The noise figure is defined as how much the internal noise of an electronic element
degrades its SNR (signal noise ratio). It is often specified for a 1Hz bandwidth at a given
frequency. In this case, the noise figure is also called spot noise figure to emphasize the very
small bandwidth as opposed to the average noise figure, where the band of interest is taken into
account. The noise figure is defined as:
NF=SNR¿
SNRout=S¿N out
SoutN ¿ (2.1)
Where,
N ¿ : input power and always taken as the noise in the source resistance.
N out : output noise power including the circuit contribution and noise transmit from
the source resistance.
7
Combine Sout= GS in into equation above, where G is power gain of corresponding stage,
NF=NoutGN ¿
(2.2)
2.5 Filter.
A passive microwave filter is a circuit component consisting of lumped elements
(inductors, capacitors and resistor) only or distributed elements or both arranged in particular
configuration so that desired signal frequencies are allowed to pass with minimum possible
attenuation while undesired frequencies are attenuated. In the design of a filter, the important
specification one looks into are frequency range, bandwidth, insertion loss, stopband attenuation
and frequencies, input and output impedance levels, voltage standing- wave ratio (VSWR),
group delay, temperature range and transient response.
2.5.1 Types of filter
In analog IC design, essentially there are four types of filters used. They are low pass,
band-pass, band stop and high-pass. Their frequency response is shown in Figure 2.5.
8
Figure 2.5 : Basic filter responses (a) Low pass; (b) High-pass; (c) Bandpass and (d) Bandstop
An ideal filter would have zero insertion loss and constant group delay across the desired
function. All filters shows fake response where they have low loss where the rejection should be
high. The best way to accomplished are to have filter perform well over estimated frequency.
9
2.6 LNA Topology
To design a competitive LNA, selection of amplifier topology is very important step. The
topology should be selected such that it consumes less power, provides higher gain and contains
lesser number of components to avoid degradation in noise figure.
In common gate configuration, the LNA consumes very low power but provide minor
gain of less than 10dB. On the other hand, common source topology with shunt series feedback,
power consumption is low but stabilizing among noise figure, gain and input output matching is
a challenging task. Common source configuration with resistor termination adds extra noise to
LNA due to the thermal noise of resistor . Lastly, common source topology with inductive
degeneration with low power consumption and better stability is best choice for UWB
applications [9].
In order to achieve wideband amplification, the feedback configuration is preferred in IC
fabrication due to the uniformity and stability at frequencies below 12GHz. The cascade
configuration offered various advantages for wideband applications such as higher gain, wider
bandwidth, and better stability. Most importantly, by carefully choosing feedback resistance, the
requirements of wideband systems for both noise and power simultaneously satisfied. The
cascode configuration is also able to reduce high frequency roll- off of the input devices due to
Miller effect. The input and output matchings are able to performed independently. The stability
and circuit’s bandwidth is improved by using negative parallel feedback. A single- stage CMOS
cascode feedback LNA consists of a cascaded n- channel MOS and a resistive parallel feedback
as illustrated in Figure 2.6.
10
Figure 2.6 : Schematic of cascade feedback LNA.
2.7 Comparison of Published LNA for UWB Application Works.
In wireless receiver, LNA’s performance plays critical role in overall system sensitivity
as it is the first block to amplify the received signal from antenna. Hence, for the achievement
of high receiver sensitivity, the LNA Is required to have a low noise figure with good input
matching as well as sufficient gain with flatness in the wide frequency range of operation from 3
to 5 GHz.
Cascode configured UWB LNAs that has been investigated by Bevilacqua and Niknejad
has achieved a broadband input matching [3]. However, the amplifier’s design used LC band
pass filters and depended on the use of five inductors which in turn increases the size of the
circuit (1.1 mm2).
A 0-11 GHz distributed LNAs has also been reported [4]. But, the feasibility of this
design is also limited due to its large size (1.44 mm2) and high power consumption (100 mW).
Common-gate amplifiers exhibit excellent wideband input matching, but suffers from a relatively
large noise figure (NF).
Resistive-feedback amplifiers have very good wideband input matching characteristics.
However, low NF and low power consumption can be hardly achieved at the same time across a
large frequency range.
11
In [5], noise cancellation technique is used to relax this trade-off in resistive-feedback
amplifiers. Also, the bandwidth of a resistive-feedback amplifier with noise cancellation is
further extended by using the inductive shunt peaking and series peaking techniques. Therefore,
good input matching, low power consumption, and low NF can be achieved simultaneously over
a wide bandwidth.
The research in [7] showed the wideband LNA design by using combination of a
common source and a common gate stage for 3-5 GHz UWB applications. The two stage LNA
circuit rely on the use of current re-use RC feedback in order to achieve optimum noise figure
and gain while maintaining a wideband bandwidth.
A two- stage cascode CMOS LNA for UWB simulated in [8] used common- source
configuration, an input matching circuit for broadband operation, and shunt feedback as
illustrated in Figure 2.7. This stage tuning technique is used to yield a flatter and broader
bandwidth than could otherwise be obtained. The detailed comparisons between previous LNA
works has been summarized out in Table 2.7.
Figure 2.7 : Circuit of two- stages cascade CMOS LNA with common source configuration
12
Research Papers
[7] [7] [8] [3] [4] [5]
Topology Single stage Cascode LNA with current
re- used
Two stage LNA with
current re-used
Two stage LNA
Two stage LNA
Two stage LNA
Two stage LNA
Technology 0.18μm CMOS
0.18μm CMOS
----- 0.65μm CMOS
0.18μm CMOS
0.18μm CMOS
Frequency of Operation
3- 5 GHz 3- 6 GHz 3- 6 GHz 0.2 – 5.2 GHz
1- 5 GHz 3- 5 GHz
Supply Voltage
1.8 V 1.8 V 1.8 V 1.2 V 1.8 V 1.8 V
Gain 12.7 dB 24 dB 24 dB 13- 15.6 dB 11- 13.7 dB 8.6- 9.5 dBS11 < -6 dB <-10 <-10 ----- <-10dB <-10.3dBS22 < -8 dB <-10 <-10 ----- ----- -----S12 -26.8 dB -40db ----- ----- ----- -----NF 2.31 dB 2.9 dB 2.9 dB 3.5 dB 5-6.5 dB 2.7 dB
NFmin 2.158 dB ----- ----- ----- ----- -----P1db -6.46719 dB ----- ----- ----- ----- -----
Power Consumption
11.7 mW 51 mW 51 mW ----- 9mW 15 mW
Stability Un- dondtionally
Stable designs
----- ----- ----- ----- -----
Table 1.7: Comparisons of published works of UWB LNAs
13
CHAPTER 3
METHODOLOGY
3.1 General Utilizing of Virtuoso Schematic Editor
Cadence is an Electronic Design Automation (EDA) environment which allows different
applications and tools to integrate into a single framework. Cadence support all the stages of IC
design and verification from a single environment. In addition, These tools support different
fabrication technologies. Virtuose platform which can be used in Cadence environment, is a
schematic editor tool for designing full- custom integrated circuit. Virtuoso Analog Design
Environment is an industry standard platform that supports a variety of analog simulators, and
has the flexibility to use different simulators on the same design. The analog IC components used
in the schematic editor is compatible with Silterra foundry.
Firstly a schematic view of the circuit is created using the Virtuoso Schematic Editor.
Virtuoso Schematic Editor is capable of supporting digital, analog and RF integrated circuit
designs within the same environment. Alternatively, a text netlist input can be employed. Then,
the circuit is simulated using the Cadence Affirma analog simulation environment. Different
simulators can be employed such as Spectre RF and HSPICE which provide distinctive IC
simulation environment.
14
3.2 Schematic Design Process Flow.
The project is started by identifying the low noise amplifier specifications. The vital
characteristics of the amplifier are the noise figure (NF) and the gain at source impedance.
The trade-offs of the optimizations is the scarification of other important characteristics such
as gain, power consumption, gain flatness and input and output loss. These specifications are
defined early in the project as expected results of the amplifier.
The next step of the project is designing the circuit topology. In this step, network
interconnections of the circuit components will be produced. Distributed and feedback
configurations are the most commonly used as it has better uniformity and stability at
frequencies below 12GHz. In addition, the cascode structure is considered to be the best
topology for wideband applications because of advantages such as higher gain, wider
bandwidth, and better stability. Above all, it can satisfy the requirements of wideband
systems for both noise and power simultaneously through a careful choice of feedback
resistance [6].
The electronic design automation tool (EDA) will be used in the process of designing
the amplifier’s circuit schematics. The EDA tool chose for this project is Cadence. The tool
provided the users with the IC electronic components such as transistors and resistors to be
placed on circuit. The technology of IC is set to 0.13-um. The obtained simulated result will
be analysed and compared with desired specification before proceeding to last process.
Layout design will be done only for estimating the LNA chips size. The complete process
flow of this project is shown in Figure 3.2.
15
Y
ESY
ES
Figure 3.2: Flowchart of LNA design process
16
3.3 Schematic Design
In this work, the proposed LNA design rely on the use of current re- use RC feedback
in order to achieve optimum noise figure and gain while maintaining a wideband bandwidth.
The schematic uses two- stage cascode with RC feedback as current re- use and a
conventional common source amplifier as second stage to boost and to maintain gain flatness.
A source inductor, Lg (series gate inductor) is used in narrow band applications to resonate
the internal parasitic capacitance Cgs of the transistor, which in turns provides good
impedance matching at the designed frequency. A source inductor feedback can rotate S11 of
an LNA closer to Γopt, which can help obtaining a minimum Noise Figure and good Input
Return Loss simultaneously. The additional source inductance provides loss-less negative
series feedback, and also reduce the overall available gain of the network and can be used in
balancing trade-offs between parameters of the LNA such as gain and stability. The inductive
degeneration does not impact the LNA Noise Figure as much as resistive degeneration does.
The complete schematic design is shown on Figure 3.3.
Figure 3.3 : Designed schematic of LNA
By ignoring the miller effect of gate- drain capacitance (Cgd) of transistor M0, the
input impedance of Mo is given by :
17
Z¿=s (Ls+Lg )+ 1sCgs
+( gmCgs
) Ls
Where gm and Vgs are trans-conductance and gate- source capacitance of transistor
M0. Inductors Ls and Lg are the source degeneration inductor and gate terminal inductor. The
LNA used a cascode topology on first stage while second stage is a simple common source
stage without cascade transistor and Lg.
To determine current flow between transistor, the ID current formula is used. The size
of transistors also can be determined by using this formula:
IDD=12μnCox
WL
(V GS1−V t)2
By rearranging the formula, the gain of the amplifier can be pre- determined before a
simulation by using formula of:h
β=12μnCox
WL
For the second stage, the circuit is using simple source follower amplifier. In this
amplifier, a large transistor size is needed for high gain and output power of the amplifier at
higher frequencies. In this simulation the transistor size is set to 120 µm. The drawbacks of
the large transistor is higher parasitic capacitances and transconductance which increase
power consumption. For current simulation, the bias network is controlled by Rbias and two
independent voltage dc sources.
18
3.4 Circuit Simulation Using Spectre RF
The proposed design has been simulated and optimized with Cadence’s RF spectre
design tool with 0.13 um CMOS technology. Spectre is capable of handling large circuit and
performing tight simulation parameters. Two ports are used in simulation, which is input
(port0) and output (port1). The dc analysis has been performed to see the performance for 3
to 5 GHz band.
Figure 3.4 : Simulation setup in Spectre- RF.
19
CHAPTER 4
RESULT
4.1 S- Parameter Analysis
The LNA schematic drawn has been simulated using Spectre RF and shown in Figure
4.1. The result obtained is rigorously optimized to meet desired operating frequency from 3 to 5
GHz. The result waveform has lower operating frequency almost perfectly located around 3
GHz. The upper frequency has narrowly exceed 5 GHz, which is 5. 5GHz. The gain flatness is
obtained for frequency range between 3 and 4 Ghz and has a maximum flat gain of +15db. The
output s- parameters result is tabulated in Table 4.1
Figure 4.1 : Simulated Waveforms
20
Specifications Proposed LNA Design’s Value
Topology Single stage Cascode LNA with current re- used
Technology 0.13 CMOS
Frequency of Operation
3- 5.8 GHz
Supply Voltage
1.8 V
Gain 15.5 dB
S11 < -4.5 dB
S22 < -12 dB
S12 -38 dB
Table 2 : Summary of result waveforms
Figure 4.2 : Simulated Waveforms included S12
21
REFERENCE
[1] WhatIs.com, 'What is ultra wideband? - Definition from WhatIs.com', 2015. [Online]. Available: http://whatis.techtarget.com/definition/ultra-wideband. [Accessed: 23- Oct- 2015].
[2] J. Pan, 'Medical Applications of Ultra-Wideband (UWB)', Cse.wustl.edu, 2015. [Online]. Available: http://www.cse.wustl.edu/~jain/cse574-08/ftp/uwb/. [Accessed: 23- Oct- 2015].
[3] Bevilacqua A.,A.M. Niknejad, “An ultra-wideband CMOS low-noise amplifier for 3.1-10.6GHz wireless receivers,” IJSSCC, pp. 2259- 2269, Sept. 2007.
[4] Guan X, Nguyen C., “Low-power-consumption and high-gain CMOS distributed amplifiers using cascade of inductively coupled common-source gain cells for UWB systems,” IEEE Transactions on Microwave Theory and Techniques, vol.9, pp. 3278-3283,Sept.2006.
[5] F.Bruccoleri,E.A.M.Klumperink, Nauta, “Noise cancelling in wideband CMOS LNAs”, IEEE International Solid State Circuit Conference,2002.
[6] S.Jose, “A Tutorial in Transistor Microwave Amplifier Design- Part1”, San Jose State University.
[7] V. Bhale, "Design and Optimization of CMOS 0.18μm Low Noise Amplifier for Wireless Applications", International Journal of Information and Electronics Engineering, vol. 4, no. 2, 2014.
[8] S. Khemchandani, D. Ramos-Valido, H. García-Vázquez, R. Pulido-Medina and J. del Pino, "A low voltage folded cascode LNA for ultra-wideband applications", Microwave and Optical Technology Letters, vol. 52, no. 11, pp. 2495-2500, 2010.
[9] H. Rastegar and A. Hakimi, "A High linearity CMOS low noise amplifier for 3.66GHz applications using current-reused topology", Microelectronics Journal, vol. 44, no. 4, pp. 301-306, 2013.
[10] Rahayu, Y.; Rahman, T.A.; Ngah, R.; Hall, P.S., "Ultra wideband technology and its applications," in Wireless and Optical Communications Networks, 2008. WOCN '08. 5th IFIP International Conference on , vol., no., pp.1-5, 5-7 May 2008.
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