Proposal and Performance Analysis of Normally Off $ \hbox{n}^{++}$ GaN/InAlN/AlN/GaN HEMTs

$Page 1: Proposal and Performance Analysis of Normally Off $ \hbox{n}^{++}$ GaN/InAlN/AlN/GaN HEMTs$
2144 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 9, SEPTEMBER 2010

Proposal and Performance Analysis ofNormally Off n++ GaN/InAlN/AlN/GaNHEMTs With 1-nm-Thick InAlN Barrier

Jan Kuzmik, Clemens Ostermaier, G. Pozzovivo, Bernhard Basnar, Werner Schrenk, Jean-François Carlin,M. Gonschorek, Eric Feltin, Nicolas Grandjean, Y. Douvry, Christophe Gaquière, Jean-Claude De Jaeger,

K. Cico, Karol Fröhlich, J. Škriniarová, Jaroslav Kovác, Gottfried Strasser, Dionyz Pogany, and Erich Gornik

Abstract—Design considerations and performance of n++

GaN/InAlN/AlN/GaN normally off high-electron mobility transis-tors (HEMTs) are analyzed. Selective and damage-free dry etchingof the gate recess through the GaN cap down to a 1-nm-thickInAlN barrier secures positive threshold voltage, while the thick-ness and the doping of the GaN cap influence the HEMT directcurrent and microwave performance. The cap doping density wassuggested to be 2 × 1020 cm−3. To screen the channel from thesurface traps, the needed cap thickness was estimated to be only 6nm. Design is proved by an experiment showing a constant value ofthe HEMT dynamical access resistance, while a single-pulse exper-iment indicated almost collapse-free performance. On the otherhand, it is found that the n++ GaN cap does not contribute to theHEMT drain current conduction, nor does it provide a path for theOFF-state breakdown. HEMTs with a gate length of 0.25 μm anda 4-μm source-to-drain distance show a drain-to-source current of0.8 A/mm, a transconductance of 440 mS/mm, a threshold voltageof ∼0.4 V, and a cutoff frequency of 50 GHz. A thin and highlydoped GaN cap is also found to be suitable for the processing ofnormally on HEMTs by adopting the nonrecessed gate separatedfrom the cap by insulation.

Index Terms—Current collapse, gate recess, high-electron mo-bility transistors (HEMTs), InAlN/GaN, normally off, OFF-statebreakdown.

Manuscript received December 17, 2009; revised April 30, 2010; acceptedJune 18, 2010. Date of publication July 19, 2010; date of current versionAugust 20, 2010. This work was supported in part by the MORGaN EuropeanProject FP7 NMP IP 214610 and in part by the Gesellschaft für Mikro undNanoelektronik (GME). The review of this paper was arranged by EditorS. Bandyopadhyay.

J. Kuzmik is with the Institute for Solid State Electronics, Vienna Universityof Technology, 1040 Vienna, Austria, and also with the Institute of ElectricalEngineering, Slovak Academy of Sciences, 841 04 Bratislava, Slovakia.

C. Ostermaier, B. Basnar, W. Schrenk, G. Strasser, D. Pogany, andE. Gornik are with the Institute for Solid State Electronics, Vienna Universityof Technology, 1040 Vienna, Austria.

G. Pozzovivo is with the Infineon Technologies AG, 9500 Villach, Austria.J.-F. Carlin, M. Gonschorek, E. Feltin, and N. Grandjean are with the

Institute of Quantum Electronics and Photonics, Ecole Polytechnique Federalede Lausanne, 1015 Lausanne, Switzerland.

Y. Douvry, C. Gaquière, and J.-C. De Jaeger are with the Institutd’Electronique, de Microélectronique et de Nanotechnologie, 59652 Villeneuved’Ascq, France.

K. Cico and K. Fröhlich are with the Institute of Electrical Engineering,Slovak Academy of Sciences, 841 04 Bratislava, Slovakia.

J. Škriniarová and J. Kovác are with the Department of Microelectronics,Slovak University of Technology (STU), 812 19 Bratislava, Slovakia.

Digital Object Identifier 10.1109/TED.2010.2055292

I. INTRODUCTION

R ECENTLY, there has been a substantial interest in devel-oping normally off GaN-based transistors for high-power

[1] and logic [2] applications. Several approaches have beenpersuaded earlier to obtain the normally off GaN high-electronmobility transistor (HEMT) operation. Taking into account therelation for the threshold voltage value VT ∼ qdns0/ε, where εdenounces barrier permittivity, the normally off operation canbe obtained either by reducing the channel to gate distance d orby modifying the equilibrium charge ns0 in the quantum well(QW). The latter approach has been applied by using plasmatreatment when a large amount of F− ions modifies ns0 [2], [3],or by the channel depletion from the side of the AlGaN buffer[4]. The possible drawback of the approach of ns0 modificationcan be a limited maximal drain current density [2]–[4]. On theother hand, the main conceptual concern by reducing d canbe an increase in the HEMT access resistances [5]. The effectcan be explained by an excessive channel depletion inducedby the proximity of the surface potential [5], [6]. The possiblesolution is represented by putting a dielectric coating on thesurface between the contacts, and, consequently, the surfacepotential at access regions is reduced [5], [6]. However, a moreeffective solution for normally off GaN HEMTs seems to bea nonplanar approach by recessing the gate from the optionalthickness of the barrier layer [1], [4], [7], [8]. It is a challengingtask to develop a dry recess technique for normally off HEMTswith a negligible plasma-induced damage, i.e., with preferablyunspoiled ns0 [1], [8] and with a low gate leakage current afterthe plasma process [4]. For reproducibility of the process, it isalso highly desirable to use a selective etching when the final dof the normally off HEMT is well controlled, as described in arecent paper by Ostermaier et al. [8].

HEMTs based on an InAlN/GaN heterostructure systemoffer some additional advantage over the most conventionalAlGaN/GaN counterparts due to higher polarization charge inthe QW even without a strain in the barrier layer [9], [10]and extremely high thermal stability [11]. Nonexistence of thestrain in the barrier has been shown to enhance the devicereliability [12], while high polarization charge in the HEMTQW leads to high drain current density [11] and facilitatesextreme scalability of the device [13].

However, similarly as for AlGaN/GaN HEMTs [14],parasitic effects related to the traps on the surface can

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KUZMIK et al.: ANALYSIS OF N++ GaN/InAlN/AlN/GaN HEMTS WITH 1-NM-THICK INALN BARRIER 2145

deteriorate InAlN/GaN HEMT performance [15]. The drain-to-source current IDS collapse or a lag of the current in the pulsedmode behind the dc one is mainly due to the transient loadon the HEMT gate-to-drain region. The lag on unpassivatedInAlN/GaN HEMTs was manifested by a substantial shift ofthe knee voltage and by reduced IDS in the pulsed operation[15]. The density of unstable charge at the InAlN surface wasshown to be up to 90% of ns0; moreover, the collapse wasshown to be significant for the device pulsed on the gate frombelow the threshold voltage, while the drain-to-source quiescentbias VDS was sequentially increased [15]. On the other hand,the surface passivation of AlGaN/GaN HEMTs by SiN canreduce the current collapse; however, the lag effect may stillbecome unacceptably high for large gate-to-drain distancesdGD [14]. This is unfavorable, as larger dGD may be requiredfor a high OFF-state breakdown in InAlN/GaN HEMTs [16].Alternatively, the influence of the unstable surface charge onQW carriers can be mitigated by increasing the QW distanceto the surface at access regions, as described for AlGaN/GaNHEMTs with a 250-nm-thick undoped GaN cap layer [17].However, a deep three-step dry etching process for the gaterecess is needed in this case. Moreover, it was shown elsewherefor InAlN/GaN HEMTs that the undoped GaN capping doesnot affect the surface trap density, which is equal to the level ofthe counterpart polarization charge in the QW [15]. Thus, theGaN cap itself may not be considered as true passivation.

Additional detrimental effect in GaN HEMTs identified else-where was degradation of the dynamical source access resis-tance dRS [18]. An increase in dRS with increased drain biasdeteriorates transconductance gm, cutoff frequency fT , and theHEMT linearity [18]. The apparent early velocity saturation ofelectrons in the source access region due to the surface chargingmay explain the effect [19]. The n+ GaN cap layer (120 nmthick) on AlGaN/GaN HEMTs has been shown to eliminate thedRS increase [20]. Selective dry etching has been used to re-move n+ GaN in two-step gate lithography. n+ GaN was shownto also enhance dc HEMT parameters by reducing ohmic RS

[20]. However, the role of n+ GaN was not completely clear.Reported contact resistance RC was doubled after n+ GaNwas removed between the transmission line method (TLM) testpattern, and no explanation was suggested. The mechanismbehind the flat dRS (and the relation to the GaN cap) was alsonot completely described [20].

In this paper, we explain our motivations and considerationsin designing normally off InAlN/GaN HEMTs [8]. In the ex-perimental part of this paper, we focus on the effects related tothe n++ GaN capping layer, which turns out to be an importantpart of the structure. In particular, we analyze the impact ofthe GaN cap on parasitic effects related to the surface trapsand on the mechanism of the OFF-state breakdown. The roleof the gate length in the HEMT dc and small-signal microwaveperformance is also analyzed.

II. DESIGN OF THE NORMALLY OFF

GaN/InAlN/AlN/GaN HEMTS

The following ideas and conditions (C) drive our deviceproposal: InAlN/GaN QW is unique in high ns0, and this

Fig. 1. Schematic view of the normally off n++ GaN/InAlN/AlN/GaNHEMT. Depleted parts of the n++ GaN cap are highlighted by shading. Theundepleted part of the cap indicated as Nscreen is sandwiched between thedepleted parts. The assumed path of the drain current and a location of the pos-sible GaN buffer punchthrough are marked by bold arrows. The conductionband scheme on the left corresponds to the cross section of the epilayer startingfrom the free surface between the contacts.

property and the value of ns0 should be unaltered by processingnormally off HEMTs (C1), the design should secure low-accessresistances without parasitic effects of the dynamical access re-sistance and the HEMT collapse-free performance (C2), and thedesign and processing of the normally off InAlN/GaN HEMTsshould be simple, reproducible, and compatible with eventualprocessing of the normally on HEMTs to facilitate integration(C3). Condition C1 can be fulfilled by using the approach ofthe recessed gate, where the plasma process should be damage-free, and the thickness d should provide VT ≥ 0 V. To fulfillthe condition C2, InAlN should be covered with a doped GaNcap containing sufficient amount of free electrons to eliminatesurface depletion effects at access regions and to screen thechannel from surface traps. Finally, to fulfill C3, we need ahighly selective plasma process, one-level gate lithography, andan optional possibility to shift VT to reasonably low negativevalues in the processing chain by additional separation of thegate from the channel. In the following, we discuss the value ofd and mainly the parameters of the GaN cap: thickness dGaN

and volumetric doping NGaN.Earlier experimental results [10], [13] on dependence of VT

on d are in good agreement with values calculated by analyticalformula [9] (not shown), suggesting that for the normallyoff operation, it is reasonable to propose the channel-to-gateseparation d = 2 nm, consisting of a 1-nm InAlN barrier and a1-nm AlN spacer to enhance the QW electron mobility [21].

For the proposal of dGaN and NGaN of the GaN cap to securethe effective screening of the QW channel from the surfacetraps, we need to fulfill

Nscreen = (dGaN − dD1 − dD2) × NGaN ≥ NT (1)

where Nscreen is a sheet density of free carriers in the cap,dD1 and dD2 are the equilibrium interface depletion depthswithout considering traps at the GaN/InAlN junction and atthe GaN surface, respectively (see Fig. 1), and NT is the sheetdensity of surface traps. In other words, the volume of the GaNcap needs to provide enough free carriers to compensate thecharge variations at the GaN trapping surface additionally tothe interface depletion effects of the ideal interfaces.

Next, we estimate depletion effects in GaN as

dD1,2 = (2Vbi1,2ε/qNGaN)1/2 (2)


where Vbi1,2 is the built-in voltage at the GaN/InAlN and GaNsurface interface, respectively (see Fig. 1). Vbi1 appears due toa difference in a work function of GaN and InAlN and due toa negative polarization charge at the GaN/InAlN junction. Onthe other hand, Vbi2 is generated due to the Fermi level pinningat the GaN surface. We can estimate Vbi2 = 0.5 eV [22]. Thereare no relevant data on the GaN/InAlN interface, and, for sim-plicity, we assume that Vbi1 = Vbi2. In order to fulfill conditionC3 (reproducible and simple plasma processing with only one-level gate lithography, preparation of the normally on HEMT),we need to have sufficiently thin dGaN to be comparable to d.Consequently, taking into account (1), high NGaN is preferable.If we choose NGaN = 2 × 1020 cm−3 from (2), we get dD1,2 ∼1.5 nm. NT was estimated elsewhere to be 2 × 1013 cm−2 [15],and, thus, this represents the minimum acceptable value forNscreen. Consequently, assuming NGaN = 2 × 1020 cm−3 anddD1,2 ∼ 1.5 nm, from (1), we get dGaN ≥ 4 nm. Taking intoaccount an unknown value of Vbi1, in the following, we estimatea “safe” value of the cap thickness to be 6 nm.

III. EXPERIMENT

Six-nanometer GaN:Si (2 × 1020 cm−3)/1-nm lattice-matched InAlN/1-nm AlN/2-μm GaN was grown on sapphireby metal organic chemical vapor deposition [10], [21]. Afterthe growth, the apparent free carrier concentration profile ismeasured using the electrochemical C–V method. The surfaceof the electrolyte (three droplets of H3PO4 diluted in 100 mlwater) in contact with a semiconductor is 0.1 cm−2. At thejunction, the solution may form a thin protective oxide, andno etch of GaN is performed. The energy difference betweenthe electrolyte and the bulk GaN was extracted earlier from the1/C2 versus V plot to be around 1 eV, and that is more thanwhat we expect for the free surface (Vbi2).

The Mesa insulation was performed by reactive ion etching(RIE) in Ar gas. Ohmic contacts are formed by electron-beamevaporation of Ti/Al/Ni/Au and rapid thermal annealing at800 ◦C for 30 s. The source-to-drain distance dSD was variedfrom 4 to 16 μm, and the source-to-gate distance dSG was fixedat 1 μm. HEMTs with a gate length LG = 0.5 and 0.25 μmand a 2 × 25 μm gate width were patterned by e-beaminto poly(methyl methacrylate) (PMMA) resist. Initially, thePMMA exposure was optimized for a negative slope of the sidewall (see Fig. 2) of a typical shape. Simple one-step lithographywas used for the gate recess selective dry etching and thelift-off. SiCl4/SF6 was used to perform a damage-free RIEof GaN over InAlN in the regime of the inductively coupledplasma, similarly as reported for GaN/AlGaN/GaN [23]. Theselectivity of the etching was 15; self-induced bias was keptbelow 100 V to limit the plasma-induced damage. We believethat the shape of the PMMA side wall (see Fig. 2) and assumedpartial isotropic etching of GaN because of the low self-inducedbias may provide a gap between the gate metal (which isdefined by the upper PMMA opening) and the n++ GaN edge(defined by the PMMA masking at the bottom). The gate ton++ GaN distance was preliminarily checked by an atomic-force microscopy, and the gap seems to be in order of a few tensof nanometers; however, a transmission-electron microscopy

Fig. 2. Scanning electron microscopy image of the PMMA resist side wallafter the test exposure and development. (Vertical lines) PMMA thickness(∼200 nm) and the resist undercut. The thickness of the resist for the HEMTprocessing was 400 nm (not shown).

Fig. 3. Lumped resistance circuit scheme of the access region of the HEMT.For simplicity, only the SG region is shown.

image is needed in the future to be more conclusive. Afterthe RIE process, the sample was loaded into the evaporatorto deposit 15-nm Ni/150-nm Au thick gate stack. More on theprocess optimization will be described in our next paper.

We may assume that the carrier depletion at the GaN/InAlNjunction and a termination of the current path in the GaN capby the gate recess may prevent participation of the GaN capto IDS along the HEMT access regions. The situation can beschematically described by a lumped resistance circuit schemeof the HEMT access region shown in Fig. 3. Here, rC1,2

represents elements of the contact resistance, rB constitutesthe lumped resistance across the depletion region dD1 and thebarrier, rGaN and rQW are the elements representing the accessresistance along the GaN cap and QW, respectively, and RCHI

is the intrinsic channel resistance. Obviously, if rB � rQW,then the GaN cap may participate in the carrier transport of theaccess region similarly as it does in the planar structure withoutthe recess. On the other hand, if rB � rQW, then the GaNcap is practically not contributing to the channel conductiondue to the termination at the gate recess. To study the role ofthe GaN cap layer, we adopt two modifications of the TLM:without and with the gate recess, respectively. In the first case,the contact resistance RC and the channel resistance RCH are


extracted using the conventional transmission line model [24],with the TLM1 test structure having ohmic contacts on theGaN cap in different distances dTLM (RC and RCH are labeledwith “TLM1”). In the modified measuring sequence (referredas TLM2), we use various default HEMTs with different dSD

instead of the TLM1 test structure. The TLM2 sequence iscomposed of two steps. Initially, the total source-to-drain re-sistance RT = RS + RD + RCHI of each HEMT is measuredas a function of Vx = 1/{1 −

√[(Vbi − VGS/(Vbi − VT )]},

where RD is a drain access resistance, and Vbi is a Schottkycontact barrier height. In the acquired linear dependence, agraph extrapolation to Vx = 0 gives RS + RD; the slope ofthe line provides the open intrinsic channel resistance RCHI0

[25]. In the second step, the values of RS + RD are plottedas a function of (dSD − LG). RC(TLM2) and RCH(TLM2)are extracted from the graph similarly as for the conventionaltransmission line model. However, in comparison to the valuesof TLM1, RCH(TLM2) and RC(TLM2) are determined directlyfrom the access regions of HEMTs.

dRS is investigated by the method described in [18] byforcing 20-mA/mm forward current on the gate using Agilent4155B. The drain contact bias VDS is increased in the method,the gate-to-source voltage VGS is sensed, and dRS is calculatedas dVGS/dIDS [18]. The current source was used also byusing the drain current injection technique [26] to measurethe HEMT OFF-state breakdown voltage Vbr. In this method,we force a defined current on the drain; the HEMT is drivento the OFF-state by changing VGS , while Vbr is measured asincreased VDS at the pinch-off. Vbr depends on the set currentinjection value; however, the method can be nondestructive.The “physical” hard breakdown, on the other hand, is obtainedby a simple increase in VDS by measuring the HEMT outputcharacteristic under the pinch-off conditions. To evaluate thedrain current collapse effect, we use Keithley 4200-SCF/F bypulsing the gate alone from VGS = −3 V, while dc drainbias is sequentially increased so that the last quiescent pointwas VGS = −3 V/VDS = 20 V. The single pulse durationwas 200 ns with the OFF-state period of 100 μs. Finally, thecutoff frequency performance and the maximal frequency ofoperation fmax were established from small signal s-parametersfor different LG.

IV. PERFORMANCE ANALYSIS OF THE NORMALLY OFF

GaN/InAlN/AlN/GaN HEMTS

A. Role of the n++ GaN CAP

Fig. 4 shows the free carrier concentration profile in theepistructure. We note that the profile is apparent, and theresolution of the C–V method is limited mainly because ofthe averaging of the profile over the certain distance as thealternating-current voltage signal is 0.3 V peak-to-peak, be-cause of the spatial extent of the electron wave function fromthe QW, and because of other sources of error mentionedelsewhere [27]. In the GaN cap, the profile reaches NGaN >1 × 1020 cm−3. As expected, the free carriers in the 6-nm-thick GaN cap are depleted from both sides, with the morepronounced depletion effect from the GaN/InAlN junction. InFig. 4, the depletion from the surface represents the space-

Fig. 4. Apparent free carrier concentration profile and a total charge (inte-grated from the surface) in the n++ GaN/InAlN/AlN/GaN epitaxial structure.

charge region of the electrolyte/GaN junction, and, thus, thisdoes not provide any justification for Vbi2. On the other hand, itseems that the depletion in GaN from the side of InAlN (dD1 ∼3 nm) is about twice of what we expected for Vbi1 ∼ 0.5 Vand NGaN = 2 × 1020 cm−3. Consequently, by using (2), wemay estimate Vbi1 ∼ 1 - 2 eV. The pronounced depletion fromthe InAlN side is probably due to the high polarization chargeat the GaN/InAlN junction, which can be −2.7 × 1013 cm−2

[28]. However, more importantly, by integrating the free carrierconcentration profile over the cap, we proved the correctness ofour design by reaching the total free charge Nscreen in GaNto be 2 × 1013 cm−2 (see the right y-axis in Fig. 4, in thedepth of 6 nm). In other words, the suggested increase in thethickness dGaN from calculated 4 nm to “safe” 6 nm (seepart II) satisfactorily balanced pronounced Vbi1. Thus, we mayexpect effective screening of the HEMT QW channel from theunstable surface charge. The QW is clearly detected by thesecond concentration peak in the depth of 8 nm (see Fig. 4).

Fig. 5(a) shows the results of the conventional TLM1, whereparallel combination of the conduction in the GaN cap and theQW channel is measured. On the other hand, the results of theTLM2 method shown in Fig. 5(b) are extracted directly fromHEMTs, and the comparison with TLM1 indicates substantialincrease in relevant values. RC increases from 0.3 Ω · mmfor TLM1 to RC(TLM2) = 0.85 Ω · mm. Similarly, RCH in-creases from RCH(TLM1) = 289 Ω/square to RCH(TLM2) =475 Ω/square. The difference can be explained by high rB

(see Fig. 3). Consequently, in our case, we may conclude thatn++ GaN is effectively separated from the QW channel, andit does not provide any lateral conduction in HEMTs; seeFig. 1 with the suggested IDS path marked by arrows. Thus,the conventional TLM1 does not provide correct values, andthe modified TLM2 must be used to extract RC and RCH.Our finding also indicates that in the dc regime full contact-to-contact separations, dSG and dGD define the HEMT accessregions and not just a narrow separation of the gate to n++

GaN. That finding may not be favorable for the values of RS

and RD. On the other hand, as will be shown below, exclusionof the GaN cap from the conduction process may favorablyinfluence the HEMT OFF-state breakdown mechanism. We notethat the TLM2 initial measurement step [see inset of Fig. 5(b)for dSD = 4 μm] provided a value of RCHI0 ∼ 440 Ω/square,well in agreement with RCH(TLM2) = 475 Ω/square. That


Fig. 5. Extraction of (a) RC (TLM1) and RCH(TLM1) using the conventionaltest structure and (b) RC (TLM2) and RCH(TLM2) using default HEMTs withdifferent dSD distance. Inset (b) shows a foregoing measurement step on theHEMT with dSD = 4 μm. Here, RT = RS + RD + RCHI, and Vx is a

numeric value given by 1/{1 −√

[Vbi − VGS/(Vbi − VT )]}. Arrow pointsto RS + RD , which is given by a graph extrapolation to Vx = 0; the slope ofthe line provides RCHI0.

Fig. 6. Two-terminal gate-to-drain breakdown behavior of HEMTs withLG = 0.5 μm and dSD = 4 and 16 μm.

also clearly confirms assumed exclusion of the GaN cap fromthe current transport.

Fig. 6 shows the two-terminal gate-to-drain breakdownon devices with LG = 0.5 μm and with different dSD =4 and 16 μm. The breakdown appears at gate-to-drain voltageVGD = −45 V for dSD = 4 μm and increases with increaseddSD. This together with strong dependence of the two-terminalgate-to-drain IGD leakage on dSD indicates that the breakdownprocess is not initiated in the InAlN region between the gateand n++ GaN. We assume that the depletion of carriers at theInAlN/n++ GaN junction (see Figs. 1 and 4), the nonplanarnature of the device, and the gap between the gate and n++

GaN account for exclusion of the n++ GaN from the breakdown

Fig. 7. Determination of Vbr by using the drain current injection techniquefor VGS down to (a) −0.5 V and (b) −35 V. The HEMT with LG = 0.5 μm isbiased by ID = 40 mA/mm; dSD = 4 μm. Inset (a) shows the current betweenTLM contacts placed on the GaN buffer with different contact distance, from 4to 16 μm.

process. On the other hand, as will be explained below, theGaN buffer breakdown seems to be indicated by measuringVbr in the three-terminal configuration using the drain injectiontechnique; see Fig. 7 for LG = 0.5 μm and dSD = 4 μm. Inthe three-terminal breakdown experiments, current symbols aremarked with only one-letter indexes (i.e., as IG, ID, and IS).This is to emphasize a fact that contrary to the HEMT two-terminal or low-voltage three-terminal output characteristics,where, for example, IDS is assumed to be generated due to theconduction between the drain (D) and the source (S) contactonly and the indexes may be indicative, the current path underthe breakdown experiment may be ambiguous, as it may becomposed of significant current contributions from both of therest contacts. To set the proper injection current, we checkedthe GaN buffer leakage initially. The inset in Fig. 7(a) showsthe I–V characteristics of the TLM test pattern, which wasplaced directly on the GaN buffer. As shown for the contactsof distance 4 μm, the leakage is relatively high reaching almost10 mA/mm at 15-V bias, and that indicates the nonoptimizedquality of the GaN. That finding correlates also with interde-vice isolation (two neighboring HEMTs 50 μm apart), whichwas only in the order of tens of kilo-ohms. Consequently,the high injection level of the drain current ID = 40 mA/mmwas needed in the experiment to overpass the conduction inthe buffer. If the injection current was not high enough, theexperiment could only trigger the resident low-field conductionin the buffer and could not reveal the breakdown processes.The injection current ID = 40 mA/mm is much higher as anindustry standard value of 1 mA/mm, and that makes the result


interpretation difficult; still, the measurement was not destruc-tive and was repetitive. Initially [see Fig. 7(a)], at VGS > 0.4 V,the gate contact is forward-biased, and the gate current is up to20 mA/mm because of the high tunneling component throughthe thin barrier. On the other hand, after VGS decreases toVT ∼ 0.4 V, VDS starts to increase rapidly, and the gate currentchanges orientation. For VGS ∼ 0 V and VDS = Vbr ∼ 20 V,the slope of the VDS rise gradually decreases, and that may indi-cate the channel breakdown. For VGS < VT , as the space chargepenetrates into the GaN buffer, the IG tunneling current seemsto be limited by the buffer conduction, and it starts to saturate atabout 8 mA/mm [see the right y-axis in Fig. 7(a)]. Nevertheless,under the breakdown condition (VDS > 20 V), IG � ID, i.e.,most of the leakage under the breakdown is provided by theGaN buffer between the source and the drain. Fig. 1 showsan assumed breakdown path marked with a bold arrow underthe gate. Vbr ∼ 20 V was obtained also for dSD = 16 μm inthe similar experiment (not shown), although IG was reduced.To check if the eventual gate-to-drain breakdown may alsoappear, we performed additional drain injection measurementdown to VGS = −35 V [see Fig. 7(b)]. Before VGS reaches∼ −22 V when the device instantaneously degraded, we seeIG < ID, i.e., the breakdown leakage was, again, dominatedby the source-to-drain breakdown of the buffer. Still, VDS

saturates at the level of 34 V for −1 V < VGS < −10 V anddecreases for VGS < −10 V probably because of the increasedcontribution of the gate leakage and probably due to the impactionization in the buffer.

Dependence of the OFF-state breakdown on dSD and LG

is shown also in Fig. 8 for the hard breakdown experimentin the three-terminal configuration. Fig. 8(a) shows outputcharacteristics at various VGS together with the hard breakdownat VGS = 0 V for the device with LG = 0.5 μm and dSD =4 μm. Currents through the drain and source contacts ID andIS indicate nonlinear increase at VDS ∼ 20 V and the hardbreakdown at around 40 V. IG indicates that the leakage currentis not dominantly provided by the gate as IG � ID and IS ,and, thus, the soft breakdown at VDS ∼ 20 V may be linkedto the punchthrough effect through the GaN buffer [16], [29].That finding agrees well with the conclusions of the above-described drain injection technique, where Vbr ∼ 20 V. Similarbehavior was obtained also for dSD = 16 μm [see Fig. 8(b)],i.e., the value of the three-terminal OFF-state breakdown is notchanged with dSD. Different performance was obtained onlyafter reducing LG when soft breakdown (nonlinear increase inID and IS) appears at VDS ∼ 10 V, and the hard breakdownis seen at VDS ∼ 30 V; see Fig. 8(c) for LG = 0.25 μm anddSD = 4 μm. We can suggest that for better quality of the GaNbuffer, the reduction of the leakage currents below the industrialstandard 1 mA/mm and the increase in the breakdown voltagescan be expected. Optimization of the recess geometry and ofthe GaN capping for even higher breakdown values may be alsoenvisaged for better quality of the GaN buffer. We need to notethat the TLM buffer leakage indicated in the inset in Fig. 7(a)was not homogeneous across the wafer, and that influencesthe breakdown voltage. Nevertheless, in this paper, we presenttypical values of four to five HEMTs of each type, which wereall placed in the vicinity of the TLM structure with a reference

Fig. 8. Three-terminal hard breakdown experiment on HEMTs with(a) LG = 0.5 μm and dSD = 4 μm, (b) LG = 0.5 μm and dSD = 16 μm,and (c) LG = 0.25 μm and dSD = 4 μm. ID , IS , and IG denounce thecurrent measured at the drain, the source, or the gate contact, respectively;(a) shows also the output characteristics at various VGS .

leakage. In that case, we observed only ±10% margin in theHEMT values.

Fig. 9 shows evolution of dRS with VDS (and with IDS ; seethe right y-axis) for LG = 0.5 μm and dSD = 6 μm. Practi-cally, a constant value of dRS ∼ 1.5 Ω · mm of our sample isin a clear contrast with a similar experiment on the normallyon device without n++ GaN but with 10-nm-thick InAlN [16],where dRS multiplies with VDS (see the inset in Fig. 9).Thus, our design with the n++ GaN cap is found effective ineliminating the parasitic effect of dRS . We note that in ourpresent sample, the constant dRS is obtained for any dSD (notshown).

In Fig. 10, we show the pulsed and dc output characteristicsof the HEMT with dSD = 4 μm and LG = 0.5 μm. VDS wassequentially increased up to the last quiescent point VGS =−3 V/VDS = 20 V. Under similar pulsing conditions, the


Fig. 9. Determination of dRS for the n++ GaN/InAlN/AlN/GaN HEMTwith LG = 0.5 μm and dSD = 6 μm. The gate is forward-biased at20 mA/mm. (Inset) dRS on normally on HEMTs without the n++ GaN cap.

Fig. 10. Pulsed and dc output characteristics of n++ GaN/InAlN/AlN/GaNHEMTs with LG = 0.5 μm and dSD = 4 μm. The gate is pulsed from VGS =−3 V to 0–3 V; the drain is dc-biased up to 20 V. The duration of the pulse is200 ns.

Fig. 11. Pulsed and dc characteristics of n++ GaN/InAlN/AlN/GaN HEMTswith LG = 0.5 μm and different dSD = 4, 6, and 16 μm. The gate is pulsedfrom VGS = −3 V to 2 V; the drain is dc-biased up to 10 V. The duration ofthe pulse is 200 ns.

conventional normally on InAlN/GaN HEMT was reported toshow significant lag effect [15], while our device seems to bealmost collapse free. We performed single-pulse experimentalso with the OFF-state period duration up to 1 s showing similardecent performance (not shown). Additionally, the n++ GaNcap is found effective by reducing the IDS collapse phenomenaindependently on dSD; see HEMT pulsed and dc measurementsin Fig. 11 for devices with LG = 0.5 μm and different dSD.IDS decreases with increased dSD from 4 to 16 μm by about40%. However, no lag of the pulsed IDS behind the dc one

Fig. 12. Transfer and gm characteristics of n++ GaN/InAlN/AlN/GaNHEMTs with dSD = 4 μm and for different LG = 0.25 and 0.5 μm. VDS =8 V. Current axes are shown in (a) linear and (b) logarithmic scale; (b) showsalso gate IDG.

appears even for the largest dSD. This is in contrast to reportedAlGaN/GaN HEMTs passivated with SiN, where increaseddGD increases the lag and the level of the current collapse [14].Thus, the screening effect of the n++ GaN cap seems to bevery effective; nevertheless, two-pulse experiment with both thedrain and the gate contact pulsed along the HEMT load lineand the rf power measurements is needed in the future for theultimate justification.

Finally, we note that our design with the extremely thindGaN facilitates also processing of the normally on GaN/InAlN/AlN/GaN HEMTs without the gate recess [8]. A 10-nm-thick Al2O3 dielectric layer deposited on the GaN cap wasused to prepare MOS HEMTs with VT = −3.5 V and gm =220 mS/mm (not shown).

B. Impact of the Gate Length on the HEMT DC andSmall-Signal Millimeter-Wave Performance

Fig. 12 shows typical transfer and gm characteristics ofnormally off GaN/InAlN/AlN/GaN HEMTs for LG = 0.25and 0.5 μm, with constant dSD = 4 μm at VDS = 8 V. Graphsare shown both with the (a) linear and (b) logarithmic scale ofthe current axes. gm ∼ 420−440 mS/mm for both LG; IDS

reaches 0.85 A/mm. Following the analytical model of theHEMT [9], we can expect IDS ∼ (VGS − VT ) if the influ-ence of RS is marginal [9]. Consequently, Fig. 12(a) showsdetermination of VT =∼ 0.4 V for both devices using linearextrapolation of the transfer characteristics to IDS = 0 A/mmin the part of the highest slope of the IDS versus VGS plot.


Fig. 13. Cutoff frequency for n++ GaN/InAlN/AlN/GaN HEMTs withdSD = 4 μm and for different LG = 0.25 and 0.5 μm.

The IDS leakage values shown in Fig. 12(b) are in agreementwith previous observations (see Fig. 8), and it remains at themilliamperes per millimeter range for VGS < VT ∼ 0.4 V. Onthe other hand, as shown in Fig. 12(b), IDG reaches the range ofmilliamperes per millimeter only at the forward bias conditionsat around VGS ∼ 2.5 V. The turning points of the polarity ofthe gate I–V ’s are at VGS ∼ 1 V because of the voltage drop onthe source resistance [30]. Apart from the gate leakage, whichreduces with decreased LG, the other HEMT dc parameters donot seem to be substantially influenced by changed LG. This isprobably due to carrier velocity saturation over the most part ofthe intrinsic channel for both investigated LG [31]. However, asseen in Fig. 13, fT is clearly enhanced by reducing LG, fromfT = 34 GHz for LG = 0.5 μm to fT = 50 GHz for LG =0.25 μm. This can be explained by assumed reduction of thegate capacitance. The determined fmax values were 35 GHz forLG = 0.5 μm and 52 GHz for LG = 0.25 μm (not shown). Lowfmax/fT ratios may be explained by the nonoptimized GaNbuffer and are probably not influenced by the gate resistanceor by the HEMT design, as the ratio is practically not changedwith LG or with dSD (see below). Nevertheless, we can notethat our devices with only 2-nm gate-to-channel distance maykeep a high LG/d ratio even for a nanometer-scale LG, andthat will be important for future high-speed devices by avoidingshort-channel effects [32].

Finally, we note that taking into account possible capacitivecoupling of the n++ GaN cap to the QW channel, the describedapproach of the HEMT with a recess may lead also to a gatealignment-free technology [33]. However, for our samples, theincrease in the source-to-drain distance causes fT and fmax todecrease (down to fT = 21 GHz and fmax = 22 GHz, respec-tively, for dSD = 16 μm and LG = 0.5 μm). At the same timefT and fmax were proportional to gm, which is a dc value.Thus, although the rf capacitive coupling may improve ourdevice performance, for the present conditions, it seems not todominate.

V. CONCLUSION

We have presented design consideration of the normallyoff unpassivated GaN/InAlN/AlN/GaN HEMTs with the gaterecess through the n++ GaN cap and with only 1-nm-thickInAlN barrier. The analysis explains why the extremely highly

doped GaN cap is needed to provide screening of the HEMTQW from the charge variations at the surface. Simultaneously,the thickness of the GaN cap must be low enough to simplify thedevice processing. Performance analyses of HEMTs indicatethat the n++ GaN cap is effective to eliminate the parasiticeffect of the dynamical access resistance and may substantiallyreduce the HEMT lag effect, although the n++ GaN capdoes not contribute to the IDS current transport. Similarly,for the present device, n++ GaN does not provide excessiveleakage to the gate, and the device breakdown is found tobe governed by the GaN buffer. Devices with LG = 0.25 μmshow IDS = 0.8 A/mm, VT ∼ 0.4 V, gm ∼ 440 mS/mm, andfT = 50 GHz. Further device performance improvements canbe expected by improving the GaN buffer quality, by reducingdSD and LG, and by adopting T-gate. The concept of n++

GaN/InAlN/AlN/GaN normally off HEMTs with a very highaspect ratio LG/d is shown to be promising for very highspeed performance and is feasible also for the integration withnormally on GaN/InAlN/AlN/GaN MOS HEMTs.

REFERENCES

[1] S. Maroldt, C. Haupt, W. Pletschen, S. Müller, R. Quay, O. Ambacher,C. Schippel, and F. Schwierz, “Gate-recessed AlGaN/GaN basedenhancement-mode high electron mobility transistors for high frequencyoperation,” Jpn. J. Appl. Phys., vol. 48, no. 4, p. 04C 083, 2009.

[2] R. Wang, Y. Cai, W. C. W. Tang, K. M. Lau, and K. J. Chen, “Device isola-tion by plasma treatment for planar integration of enhancement/depletion-mode ALGAN/GaN high electron mobility transistors,” Jpn. J. Appl.Phys., vol. 46, no. 4B, pp. 2330–2333, 2007.

[3] F. Medjdoub, M. Alomari, J.-F. Carlin, M. Gonschorek, E. Feltin,M. A. Py, C. Gaquière, N. Grandjean, and E. Kohn, “Effect of fluorideplasma treatment on InAlN/GaN HEMTs,” Electron. Lett., vol. 44, no. 11,pp. 696–698, May 2008.

[4] R. Chu, Z. Chen, S. P. DenBaars, and U. K. Mishra, “V-gate GaN HEMTswith engineered buffer for normally off operation,” IEEE Electron DeviceLett., vol. 29, no. 11, pp. 1184–1186, Nov. 2008.

[5] Y. Ohmaki, M. Tanimoto, S. Akamatsu, and T. Mukai, “Enhancement-mode AlGaN/AlN/GaN high electron mobility transistor with low on-state resistance and high breakdown voltage,” Jpn. J. Appl. Phys., vol. 45,no. 44, pp. L1 168–L1 170, 2006.

[6] M. Higashiwaki, T. Mimura, and T. Matsui, “Development of millimeter-wave GaN HFET technology,” Phys. Stat. Sol. (A), vol. 204, no. 6,pp. 2042–2048, Jun. 2007.

[7] V. Kumar, A. Kuliev, T. Tanaka, Y. Otoki, and I. Adesida, “High transcon-ductance enhancement-mode AlGaN/GaN HEMTs on SiC substrate,”Electron. Lett., vol. 39, no. 24, pp. 1758–1760, Nov. 2003.

[8] C. Ostermaier, G. Pozzovivo, J.-F. Carlin, B. Basnar, W. Schrenk,Y. Douvry, C. Gaquière, J.-C. De Jaeger, K. Cico, K. Fröhlich,M. Gonschorek, N. Grandjean, G. Strasser, D. Pogany, and J. Kuzmik,“Ultra-thin InAlN/AlN barrier HEMT with high performance in normally-off operation,” IEEE Electron Device Lett., vol. 30, no. 10, pp. 1030–1032, Oct. 2009.

[9] J. Kuzmik, “InAlN/(In)GaN high electron mobility transistors: Someaspects of the quantum well heterostructure proposal,” Semicond. Sci.Technol., vol. 17, no. 6, pp. 540–544, Jun. 2002.

[10] M. Gonschorek, J.-F. Carlin, E. Feltin, M. A. Py, N. Grandjean,V. Darakchieva, B. Monemar, M. Lorenz, and G. Ramm, “Two-dimensional electron gas density in Al1−xInxN/AlN/GaN heterostruc-tures (0.03 ≤ x ≤ 0.23),” J. Appl. Phys., vol. 103, no. 9, p. 093 714,May 2008.

[11] F. Medjdoub, J.-F. Carlin, M. Gonschorek, E. Feltin, M. A. Py,D. Ducatteau, C. Gaquière, N. Grandjean, and E. Kohn, “Can InAlN/GaNbe an alternative to high power/high temperature AlGaN/GaN devices?,”in IEDM Tech. Dig., 2006, pp. 1–4.

[12] J. Kuzmik, G. Pozzovivo, C. Ostermaier, G. Strasser, D. Pogany,E. Gornik, J.-F. Carlin, M. Gonschorek, E. Feltin, and N. Grandjean,“Analysis of degradation mechanisms in lattice-matched InAlN/GaNhigh-electron-mobility transistors,” J. Appl. Phys., vol. 106, no. 12,p. 124 503, Dec. 2009.


[13] F. Medjdoub, M. Alomari, J.-F. Carlin, M. Gonschorek, E. Feltin,M. A. Py, N. Grandjean, and E. Kohn, “Barrier-layer scaling ofInAlN/GaN HEMTs,” IEEE Electron Device Lett., vol. 29, no. 5, pp. 422–425, May 2008.

[14] J.-W. Lee, V. Kulmar, and I. Adesida, “High-power-density 0.25 μm gate-length AlGaN/GaN high-electron-mobility transistors on semi-insulating6H-SiC substrates,” Jpn. J. Appl. Phys., vol. 45, no. 1A, pp. 13–17,2006.

[15] J. Kuzmik, J.-F. Carlin, M. Gonschorek, A. Kostopoulos, G. Konstantini-dis, G. Pozzovivo, S. Golka, A. Georgakilas, N. Grandjean, G. Strasser,and D. Pogany, “Gate-lag and drain-lag effects in (GaN)/InAlN/GaN andInAlN/AlN/GaN HEMTs,” Phys. Stat. Sol. (A), vol. 204, no. 6, pp. 2019–2022, Jun. 2007.

[16] J. Kuzmik, G. Pozzovivo, J.-F. Carlin, M. Gonschorek, E. Feltin,N. Grandjean, G. Strasser, D. Pogany, and E. Gornik, “Off-state break-down in InAlN/AlN/GaN high electron mobility transistors,” Phys. Stat.Sol. (C), vol. 6, no. S2, pp. S925–S928, Jun. 2009.

[17] R. Chu, L. Shen, N. Fichtenbaum, D. Brown, Z. Chen, S. Keller,S. P. DenBaars, and U. K. Mishra, “V-gate GaN HEMTs for X-band powerapplications,” IEEE Electron Device Lett., vol. 29, no. 9, pp. 974–976,Sep. 2008.

[18] T. Palacios, S. Siddharth, A. Chakroborty, S. Heikmann, S. Keller,S. P. DenBaars, and U. K. Mishra, “Influence of the dynamic ac-cess resistance in the gm and fT linearity of AlGaN/GaN HEMTs,”IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2117–2123,Oct. 2005.

[19] J. Kuzmik, S. Bychikhin, D. Pogany, C. Gaquière, and E. Morvan, “Cur-rent conduction and saturation mechanism in AlGaN/GaN ungated struc-ture,” J. Appl. Phys., vol. 99, no. 12, p. 123 720, Jun. 2006.

[20] Y. Pei, L. Shen, T. Palacios, N. A. Fichtenbaum, L. S. McCarthy,S. Keller, S. P. DenBaars, and U. K. Mishra, “Study of the n+ GaN capin AlGaN/GaN high electron mobility transistors with reduced source-drain resistance,” Jpn. J. Appl. Phys., vol. 46, no. 35, pp. L842–L844,2007.

[21] M. Gonschorek, J.-F. Carlin, E. Feltin, M. A. Py, and N. Grandjean,“High electron mobility lattice-matched AlInN/GaN field-effect tran-sistors heterostructures,” Appl. Phys. Lett., vol. 89, no. 6, p. 062 106,Aug. 2006.

[22] Y.-J. Lin, Q. Ker, C.-Y. Ho, H.-C. Chang, and F.-T. Chien,“Nitrogen-vacancy-related defects and Fermi level pinning in n-GaNSchottky diodes,” J. Appl. Phys., vol. 94, no. 3, pp. 1819–1822,Aug. 2003.

[23] R. T. Green, I. J. Luxmoore, P. A. Houston, F. Ranalli, T. Wang,P. J. Parbrook, M. J. Uren, D. J. Wallis, and T. Martin, “Comparison ofdamage introduced into GaN/AlGaN/GaN heterostructures using selectivedry etch recipes,” Semicond. Sci. Technol., vol. 24, no. 7, p. 075 020,Jul. 2009.

[24] D. K. Schroder, Semiconductor Material and Device Characterization,2nd ed. New York: Wiley, 1998, pp. 143–166.

[25] M. Shur, GaAs Devices and Circuits. New York: Plenum, 1987,pp. 369–372.

[26] S. R. Bahl and J. A. del Alamo, “A new drain-current injection techniquefor the measurement of off-state breakdown voltage in FET,” IEEE Trans.Electron Devices, vol. 40, no. 8, pp. 1558–1560, Aug. 1993.

[27] D. K. Schroder, Semiconductor Material and Device Characterization,2nd ed. New York: Wiley, 1998, pp. 84–100.

[28] J. Kuzmik, “Power electronics on InAlN/(In)GaN: Prospect for a recordperformance,” IEEE Electron Device Lett., vol. 22, no. 11, pp. 510–512,Nov. 2001.

[29] E. Bahat-Treidel, O. Hilt, F. Brunner, J. Würfl, and G. Tränkle,“Punchthrough-voltage enhancement of AlGaN/GaN HEMTs usingAlGaN double-heterojunction confinement,” IEEE Trans. Electron De-vices, vol. 55, no. 12, pp. 3354–3359, Dec. 2008.

[30] J. Kuzmik, A. Kostopoulos, G. Konstantinidis, J.-F. Carlin,A. Georgakilas, and D. Pogany, “InAlN/GaN HEMTs: A first insightinto technological optimization,” IEEE Trans. Electron Devices, vol. 53,no. 3, pp. 422–426, Mar. 2006.

[31] M. Shur, GaAs Devices and Circuits. New York: Plenum, 1987,pp. 309–324.

[32] G. H. Jessen, R. C. Fitch, J. K. Gillespie, G. Via, A. Crespo, D. Langley,D. J. Denninghoff, M. Trejo, Jr., and E. R. Heller, “Short-channel ef-fect limitations on high-frequency operation of AlGaN/GaN HEMTs forT-gate devices,” IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 2589–2597, Oct. 2007.

[33] G. Simin, Z.-J. Yang, A. Koudymov, V. Adivarahan, J. Yang, andM. A. Khan, “III-nitride transistors with capacitively coupled contacts,”Appl. Phys. Lett., vol. 89, no. 3, p. 033 510, Jul. 2006.

Jan Kuzmik received the Ph.D. degree from theSlovak Academy of Sciences (SAS), Bratislava,Slovakia, in 1991.

From 1991 to 1994, he was a Research Fellowwith the Institute of Electronic Structure and Laser,Heraklion, Greece. Since 1994, he has been with theSAS. From 1996 to 1998, he was awarded a JapanSociety for the Promotion of Science Fellowshipat the Kyoto Institute of Technology, Kyoto, Japan.Since 2002, he has also been with the Institute forSolid State Electronics, Vienna University of Tech-

nology (TU Vienna), Vienna, Austria, where he is responsible for the develop-ment of the GaN HEMT technology and characterization. He is a member of theprogram committee of the International Workshop on Nitride Semiconductors2010, Florida. He has authored or coauthored more than 80 scientific papers.He initiated a European project and pioneered topics of InAlN/GaN HEMTelectronics and GaN HEMT thermal characterization techniques. His otherinterests include also physics, technology, and characterization of SiC devices.

Clemens Ostermaier was born in Vienna, Austria, in 1981. He received theB.S. degree from Vienna University of Technology (TU Vienna), Vienna, wherehe is currently working toward the Ph.D. degree in the Institute for Solid StateElectronics, and the M.S. degree from the Kyungpook National University,Daegu, Korea.

His interests include the technology, fabrication, characterization, and simu-lation of III–V devices focusing on GaN HEMTs.

G. Pozzovivo was born in Policoro (MT), Italy, in1976. He received the Laurea degree in electronic en-gineering from the Polytechnic of Bari, Bari, Italy, in2005 and the Ph.D. degree in electrical and electronicengineering from the University of TechnologyVienna (TU Vienna), Vienna, Austria, in 2009.

From February to August 2005, he carried out thefinal graduation thesis at the University of Glasgow,Glasgow, U.K., where he worked on the fabricationand characterization of III–V MQW lasers. Since2010, he has been with Infineon Technologies AG,

Villach, Austria. His interests include the technology and the fabrication ofIII–V devices, GaN HEMTs, and nitride intersubband devices at telecommu-nication wavelengths.

Bernhard Basnar was born in Vienna. He receivedthe Ph.D. degree in analytical chemistry from ViennaUniversity of Technology (TU Vienna), Vienna,Austria, on his works related to atomic forcemicroscopy.

During his first postdoctoral employment at TUVienna, he shifted his focus toward nanostructur-ing and characterization of semiconductor materials.From there, he went to join the group of Prof. Willnerat The Hebrew University of Jerusalem, Jerusalem,Israel, where he conducted research in the areas of

biosensing and switchable surfaces. He is currently working with the Centerfor Micro- and Nanostructures, TU Vienna, where he focuses on modificationof surface properties of semiconductors for optical and electronic applications.

Werner Schrenk received the Dipl.-Ing. and Ph.D.degrees from Vienna University of Technology(TU Vienna), Vienna, Austria, in 1997 and 2001,respectively.

Since 2001, he has been the Technical Director ofthe cleanroom of the Center for Micro- and Nanos-tructures, TU Vienna. He has authored or coauthoredmore than 100 publications.


Jean-François Carlin was born in Nice, France,in 1962. He received the B.S. degree from theEcole Centrale de Lyon, Ecully, France, in 1986 andthe Ph.D. degree in physics from the Ecole Poly-technique Fédérale de Lausanne (EPFL), Lausanne,Switzerland, in 1993.

He has been working on the growth and charac-terization of long wavelength vertical cavity lasersand microcavity light-emitting diodes, and has de-veloped dual-wavelength coupled-cavity surface-emitting lasers. Since 2002, he has been in charge

of the MOCVD growth facilities for wide bandgap nitride semiconductorswith the L’Institut de Photonique et d’Electronique Quantiques, EPFL. Hiscurrent research interests include GaN-based electronics and optoelectronics,in particular, the development of blue VCSELs.

M. Gonschorek, photograph and biography not available at the time ofpublication.

Eric Feltin received the Ph.D. degree in physicsfrom the University of Nice-Sophia Antipolis, Nice,France, in 2003. His doctoral research at the CentreNational de la Recherche Scientifique, Centre deRecherche sur l’Hétéroépitaxie et ses Applications,allowed new developments in the growth of GaN onsilicon substrates by MOVPE for the realization oflight-emitting diodes.

He developed a new method for producing high-quality free-standing GaN substrates currently usedin the industry. Since 2004, he has been with the

Laboratory of Advanced Semiconductors for Photonics and Electronics, EcolePolytechnique Fédérale de Lausanne, Lausanne, Switzerland, where he isworking on the growth and technology of wide bandgap semiconductors (GaNand its alloys) with particular emphasis on microcavities, VCSELs, and highelectron mobility transistors. In 2009, he founded NOVAGAN, a companymanufacturing III–nitride epitaxial wafers designed for UV-blue laser diodesand high-frequency/power electronics. He has authored or coauthored morethan 80 publications in peer-reviewed international journals. He is the holderof one patent.

Nicolas Grandjean was born in France. He re-ceived the Ph.D. degree in physics from the Uni-versity of Nice-Sophia Antipolis, Nice, France, in1994. During his Ph.D. thesis, he worked on III–Vsemiconductor-based heterostructures.

From 1994 to 2003, he was a member of thepermanent staff with the Centre National de laRecherche Scientifique. His research activities werefocused on the physical properties of nitride-basednanostructures, as well as on the realization of short-wavelength light emitters and UV detectors. In 2004,

he was appointed as a “Tenure-Track” Assistant Professor with the Instituteof Quantum Photonics and Electronics, Ecole Polytechnique Fédérale deLausanne, Lausanne, Switzerland, where, in 2009, he was promoted as a FullProfessor. He is currently the Director of the Laboratory of Advanced Semicon-ductors for Photonics and Electronics. He has authored or coauthored more than300 publications in peer-reviewed international journals and four book chapters.He is the holder of four patents. His current research activities are centered onthe growth, physics, and technology of wide bandgap semiconductors (GaNand its alloys), in particular, on microcavities, quantum dots, intersubbandtransitions, and 2-D electron gas heterostructures.

Dr. Grandjean was a recipient of the Sandoz Family Foundation Grant forAcademic Promotion.

Y. Douvry, photograph and biography not available at the time of publication.

Christophe Gaquière received the Ph.D. degree inelectronics from the University of Lille, Villeneuved’Ascq, France, in 1995.

From 2003 to 2007, he was responsible for the mi-crowave characterization part of the common labora-tory between Thales TRT and Institut d’Electroniquede Microélectronique et de Nanotechnology (IEMN)focus on wide bandgap semiconductor (GaN, SiC,and diamond). He is currently a Professor withthe University of Lille (Polytech’Lille) and carriesout his research activity at the IEMN, Villeneuve

d’Ascq, France. The topics concern design, fabrication, and characterization ofHEMTs and HBT devices. He works on GaAs, InP, and metamorphic HEMTs,and he is currently involved in GaN activities. He is currently in charge of thesilicon millimeter-wave advanced technology part of the common lab betweenST Microelectronics and the IEMN. He has collaborations with the U.S.A.,Russia, Germany, Italy, Spain, Austria, and the U.K. in the frame of Europeancontracts. He has authored or coauthored more than 100 publications and200 communications. His main activities are microwave characterizations(small and large signal between 1 and 220 GHz) in order to correlate themicrowave performance with the technological and topology parameters. Hiscurrent activities concern mainly the investigation of 2-D electronic plas-mons for terahertz solid-state GaN-based detectors and emitters, AlGaN/GaNnanowires for microwave applications, and MEMS activities based alsoon GaN.

Jean-Claude De Jaeger was born in Lille, France, in1952. He received the third-cycle Doctorate degreeand the Doctorate in physics degree from the Uni-versity of Lille, Villeneuve d’Ascq, France, in 1977and 1985, respectively.

In 1974, he joined the Active Components Groupof the Centre Hyperfréquences et Semiconducteurs,University of Lille. From 1990 to 1999, he was theHead of the Physical Simulation Devices Group,Institut d’Electronique et de Microélectronique duNord (IEMN), University of Lille. He worked on

physical modeling and analysis of III–V field-effect transistors for powerapplications and mixers. Since 1999, he has been the Head of the MicrowavePower Devices Research Group, IEMN. From 2002 to 2007, he was the DeputyManager with the Thales IEMN GaN Electronics Research, a common labora-tory between the IEMN and the Alcatel-Thales III–V Lab, where he worked onwide bandgap semiconductors for microwave power applications. Since 1991,he has been a Professor of electronics. He has authored or coauthored about 270publications and communications. His current research and developed projectsconcern the simulation, the design, the fabrication, and the measurement ofmicrowave-power HEMTs based on GaAs, InP, and mainly GaN, working from3 to 94 GHz as well as devices based on wide bandgap semiconductors such asBN, AlN, and diamond.

K. Cico was born in Trencin, Slovakia, in 1980. Hereceived the Dipl.-Ing. degree in electronic engineer-ing from Slovak Technical University, Bratislava,Slovakia, in 2004 and the Ph.D. degree from theSlovak Academy of Sciences, Bratislava, in 2010.

His interests include the deposition of thin di-electric films, the technology and the fabrication ofIII–V devices, GaN HEMTs, as well as electricalcharacterization of GaN HEMT devices.


Karol Fröhlich was born in 1954. He received thePh.D. degree in material science from the SlovakAcademy of Sciences (SAS), Bratislava, Slovakia.

He is the leader of the group working on prepara-tion of thin oxide films by chemical vapor deposition.Since 2002, he has been appointed the Director ofthe Institute of Electrical Engineering, SAS. He hasauthored or coauthored about 100 publications inpeer-reviewed international journals. His researchactivities were focused on preparation and character-ization of thin oxide films, as well as on application

of thin oxide films in microelectronics. His current research includes appli-cations of thin oxide films as insulating and passivating layers in GaN-baseddevices and development of new types of oxide-based memory elements forsilicon technology.

J. Škriniarová, photograph and biography not available at the time ofpublication.

Jaroslav Kovác was born in Tornala, Slovakia, in1947. He received the B.S., Ph.D., and Professordegrees from the Slovak University of Technology(STU), Bratislava, Slovakia, in 1970, 1983, and2001, respectively.

Since 1971, he has been engaged in the researchof optoelectronic device technology with the Depart-ment of Microelectronics, Faculty of Electrical En-gineering and Information Technology, STU, where,since 1991, he has been the Team Leader of theOptoelectronic and Microwave Group. His interest

includes technology and characterization of optical and electrical properties ofIII–V devices.

Gottfried Strasser received the Ph.D. degree inphysics from the University of Innsbruck, Innsbruck,Austria, in 1991 and the State Doctorate from ViennaUniversity of Technology (TU Vienna), Vienna,Austria.

From 1988 to 1992, he was a Research Assis-tant with the Technical University Munich, Munich,Germany. In 1992, he became an Assistant Professorwith the TU Vienna, where, since March 2009, hehas been a Full Professor. In 2007, he accepted aprofessorship with the State University of New York,

Buffalo, where he was an Empire Innovation Professor with the Departmentof Electrical Engineering and the Department of Physics. He has 20 years ofexperience in the field of nanostructure science and technology, and is headinga group developing optoelectronic materials and demonstrating nanostructuresfor electronic, optoelectronic, and photonic applications. He has authored orcoauthored more than 300 journal papers and 250 conference papers in therelated areas.

Dionyz Pogany received the Dipl.-Ing. degree insolid-state engineering from the Slovak TechnicalUniversity, Bratislava, Slovakia, in 1987 and thePh.D. degree from the Institut National des SciencesAppliquées de Lyon, Lyon, France, in 1994.

In 1994–1995, he was a Postdoctoral Researcherwith France Telecom, CNET-Grenoble. Since 1995,he has been with the Institute of Solid State Electron-ics, Vienna University of Technology (TU Vienna),Vienna, Austria, where he leads a research teamand, since 2003, has been an Associate Professor.

He published on defect states in semiconductors, low-frequency noise, devicereliability physics, and optical methods for noninvasive device characterization.He has authored or coauthored more than 250 scientific contributions. Hiscurrent research interest includes ESD phenomena, self-heating effects, thermalmodeling, current filamentation, breakdown phenomena, power electronics,GaN HEMTs, failure analysis, and device reliability.

Erich Gornik received the Ph.D. degree fromthe Technical University of Vienna (TU Vienna),Vienna, Austria, in 1972.

From 1975 to 1977, he was a Postdoctoral Re-searcher with Bell Laboratories. From 1979 to 1988,he was a Full Professor for experimental physicswith the University of Innsbruck, Innsbruck, Austria,from where he moved to the Technical University ofMunich, Munich, Germany, as the Director of theWalter Schottky Institute. Since 1993, he has beena Full Professor for semiconductor electronics with

the TU Vienna and the Head of the Microstructure Center. He has authored orcoauthored more than 400 publications in scientific journals mainly in the fieldof semiconductor physics with emphasis on terahertz spectroscopy, physics oflow-dimensional structures, transport studies of nanostructures, optoelectronicdevices, characterization of devices with optical in situ techniques, and quan-tum cascade lasers for the infrared.

Documents

Proposal and Performance Analysis of Normally Off $ \hbox{n}^{++}$ GaN/InAlN/AlN/GaN HEMTs