IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014 5129

Letter

Self-Powered Gate Driver for Normally-ON SiC JFETs: Design Considerationsand System Limitations

Dimosthenis Peftitsis, Member, IEEE, Jacek Rabkowski, Senior Member, IEEE,and Hans-Peter Nee, Senior Member, IEEE

Abstract—A circuit solution to the normally-ON property ofthe normally-ON silicon carbide junction field-effect transistor,namely the self-powered gate driver, has been recently proposed.This letter sheds some light on the design process of the self-powered gate driver concept as well as limitations from the sys-tem perspective. It is experimentally shown that the parameters ofthe self-powered gate driver must be chosen taking into account atradeoff between a fast response and stable operation of the driver.Moreover, the influence of the shoot-through current in the fastactivation of the self-powered gate driver is also presented.

Index Terms—Gate drivers, normally-ON silicon carbide junc-tion field-effect transistor, protection circuit.

I. INTRODUCTION

R ECENTLY, Silicon Carbide (SiC) power transistors havedeveloped from being potential to very promising alter-

native candidates to silicon counterparts in several power elec-tronics applications [1]–[10]. The reasons for this can be foundnot only in the quality improvement of the SiC material as such,but also in the design and development of more robust and moreefficient devices, as well as, in the larger fabrication yields.

Today, there are several SiC power transistors which are avail-able as either commercial products or as engineering samplesfor evaluation. The most successful SiC devices today are theSiC metal–oxide–semiconductor field-effect transistors, the SiCbipolar junction transistors, and the SiC junction-field-effecttransistors (JFETs) [7], [11]–[14]. However, individual advan-tages and disadvantages for each type of these devices havebeen reported by several highly qualified scientists [11]–[13],[15]. Today, it is only the SiC MOSFET which is currently massproduced, while the other can be found as engineering samplesfor evaluation.

The third aforementioned SiC power device, namely theJFET, can be designed as either a normally-OFF or a normally-ON device [16]. At first sight, both versions are voltage-controlled devices. However, if low ON-state resistance is

Manuscript received October 24, 2013; revised February 28, 2014; acceptedApril 15, 2014. Date of current version May 30, 2014. Recommended forpublication by Associate Editor K. Sheng.

D. Peftitsis and H.-P. Nee are with the Department of Electrical EnergyConversion, KTH Royal Institute of Technology SE-10044, Stockholm, Sweden(e-mail: dimost@kth.se; hansi@kth.se).

J. Rabkowski is with the Institute of Control and Industrial Electron-ics, Warsaw University of Technology, 00-662 Warsaw, Poland (e-mail:jrabkows@ee.pw.edu.pl).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org

Digital Object Identifier 10.1109/TPEL.2014.2320360

targeted for the normally-OFF JFET, a large amount of the gatecurrent is necessary [17]. Moreover, the normally-ON deviceis optimized for lower specific ON-state resistance and highersaturation currents compared to the normally-OFF counterpart[16].

The short description presented previously reveals that theSiC JFET, especially the normally-ON design, is a verypromising SiC device for power electronics applications if thenormally-ON property can be accepted. A circuit solution to the“normally-ON problem,” namely the self-powered gate driver(SPGD) for normally-ON SiC JFETs has recently been pre-sented in [18]. Both the startup process and steady-state opera-tion of the normally-ON SiC JFETs can be handled by the startupand the steady-state converters of the SPGD, respectively. Thisletter sheds some light on design issues of the startup converterwhich is believed to be the most vital component of the SPGD.Moreover, limitations from the system perspective are alsodiscussed.

II. SPGD CONCEPT

Two design constraints must be taken into consideration ifa “smart” gate driver for normally-ON SiC JFETs is designed.The term “smart” refers to an automatic startup process of thedevice provided by the gate driver, as well as to the steady-state operation of the gate-drive unit. These two design con-straints can be fulfilled by using the SPGD [18]. The SPGDconsists of two low-power dc/dc converters: the startup andthe steady-state converters, which are connected in parallel tothe normally-ON SiC JFET, as shown in Fig. 1. The first con-verter (dashed, bold lines) handles the shoot-through currentswhen the normally-ON SiC JFET is subjected to a direct volt-age, while the steady-state converter (solid, normal lines) isable to supply the steady-state power to the gate driver. Anintegrated-circuit driver (IC-driver), optocoupler, and a low-voltage diode D3 are also involved in the operation of the SPGD.Moreover, a capacitor (Cic ) is connected to the supply termi-nals of the IC-driver, which is parallel-connected with the outputcapacitor of the startup converter, C1 and the gate–source ca-pacitance of Jm and Jaux , Cgs,m and Cgs,aux , respectively. Forsimplicity, in the following text, these capacitors will be denotedas Ctot = Cic + C1 + Cgs,m + Cgs,aux .

A detailed analysis of the operating sequence of these twoconverters is presented in [18] and, thus, it is not treated in thisletter. It must be noted that the switching device of the startupconverter is also a normally-ON SiC JFET, Jaux , which under

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5130 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014

Fig. 1. Detailed schematic diagram of the SPGD [18].

no gate power, lets the shoot-through current to flow through theprimary winding of T/F1 . The energy provided by this current isutilized in order to supply an adequately negative voltage to thegates of Jm and Jaux . As soon as, Jm and Jaux are turned OFF,the steady-state converter operates and continuously suppliespower to the gate circuits.

When the steady-state converter supplies an adequately nega-tive voltage to the gate drivers, the SPGD operates, regardless ofthe type of power electronics converter, as any other gate-drivecircuit. The main difference, however, compared to conven-tional gate-drive circuits, is found in the startup process of thenormally-ON JFETs, as well as in the elimination of the externalpower supply.

III. DESIGN OF THE STARTUP CONVERTER

Taking into account the presented analysis of the SPGD in[18] reveals that the startup converter is the most vital part ofthe whole concept. The reason for this is that the steady-stateconverter is unable to start operating unless Jm and Jaux havebeen turned OFF by the startup converter.

Before presenting the design process of the startup converter,it makes sense to itemize the most important design constraintsof the SPGD. The first design constraint is related to the amountof shoot-through current which is necessary in order for thestartup converter to supply an adequately negative voltage, Vsu .However, the peak value of the shoot-through current must bewell limited, such that it keeps the normally-ON JFETs far fromthermal destruction. In a real-power electronics application, theshoot-through current is usually limited by means of a startupresistor, while during the steady-state operation this resistor isshort-circuited.

The second design limitation is associated with a delay in theactivation of the steady-state converter due to the soft-startingfeature of M1 and the magnetization process of T/F2 . Thismeans that the startup converter must be able to keep both JFETsin the OFF-state until the steady-state converter starts supply-

Fig. 2. (a) Detailed schematic diagram of the startup converter and (b) equiv-alent detailed schematic diagram of the startup converter.

ing an adequately negative voltage. Thus, the output voltage ofthe startup converter, Vsu , must be kept lower than the pinchoffvoltage during the whole delay time. During the OFF-state, thegate driver must also be able to supply power in order to com-pensate for the power losses in the gate-drive circuit. Therefore,the energy stored in Ctot should be sufficient to compensate forthe various losses.

Last, but not the least, the SPGD should also be able to turnOFF the shoot-through current within reasonable times. If theshoot-through current flows for long time periods, the junctiontemperature will significantly increase and the normally-ONSiC JFETs might be thermally destroyed.

A. Equivalent Circuit of the Startup Converter

The startup converter is basically a low-power dc/dc forwardconverter without a freewheeling diode in the output stage. Adetailed schematic diagram of the startup converter connectedin parallel with the main SiC JFET is shown in Fig. 2(a). Letus assume that Jm is employed in a phase-leg of a three-phaseinverter. When the dc-breaker (or dc-switch) is turned ON, andwithout supplying power to the gate, the shoot-through currentsIJm

and IJa u x start flowing through Jm and Jaux , respectively[see Fig. 2(a)].

The operation of the startup converter can be analyzed basedon the equivalent schematic diagram shown in Fig. 2(b). At firstsight, the startup converter appears to be a dc/dc forward con-verter. However, a closer examination reveals that it resemblesa parallel L2–Ctot resonant circuit with the switch SW repre-senting the function of Jaux . The current i2 flows until SW isturned OFF (or, in other words, Vsu becomes more negative thanthe pinchoff voltage of Jaux and, thus, Jaux is turned OFF). Agraphical representation of the waveform Vsu during the startupprocess is shown in Fig. 3. Assuming that the startup process isinitialized at t0 , the voltage vsu starts to appear across Ctot at t1due to time delays associated with the magnetization process of

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Fig. 3. Waveform of vsu during the startup process.

T/F1 . The resonant circuit operates and vsu is given by

vsu (t) =√

L1

Ctot· IJa u x · sin

(1√

L2 · Ctot· t

). (1)

In this equation, L1 and L2 are the inductances of the primaryand secondary windings of T/F1 , respectively, and t is the time.At t2 , vsu becomes more negative than the pinchoff voltage ofthe JFET, Vpi , and Jaux is turned OFF. Hence, there is no currenti2 flowing in the circuit. Between the time instants t2 and t3 , vsuis still decreasing. This is due to the slow turn-OFF transient ofJaux during the startup process. Even though vsu has exceededVpi , for a very short time there is a continuously decreasingcurrent i2 which contributes to the charging of Ctot . At the timeinstant t3 , vsu starts to increase slightly, since there is no morecurrent i2 flowing in the circuit and charging Ctot , and thus Ctotis being discharged. After this moment, the startup converter isnot supplying more power to the gates of Jm and Jaux , but thepower to the gates is only supplied using the stored energy inCtot .

Equation (1) can be simplified using Maclaurin expansion ofthe term sin(ωo · t), where ωo is the resonant angular frequencyof the L2 – Ctot circuit (ωo= 1/

√L2 · Ctot). Accordingly

vsu (t) =N1

N2· 1Ctot

· IJa u x · t. (2)

It is obvious that the resonant circuit operates without com-pleting a full cycle of the output voltage vsu , since Jaux is turnedOFF after the first quarter period, when vsu is lower than Vpi . Atthis time instant, the shoot-through current IJa u x stops supply-ing any more energy to the output capacitor. Hence, the value ofC1 must be properly chosen in order to store a sufficient amountof energy to supply the losses of the driver circuit and the energyrequired to charge the Miller capacitance during the turn-OFFtransition, i.e.,

ΔWm =12· Cgd · V 2

dc . (3)

For a safe turn-OFF, the energy

ΔWcrit =12· (Ctot) · V̂su

2− 1

2· (Ctot) · V 2

pi (4)

must be larger than ΔWm , where V̂su is the peak negative valueof Vsu .

In addition to the design considerations presented so far, italso makes sense to investigate the required time for the startup

Fig. 4. Schematic diagram of the half-bridge converter with the SPGDs.(Cdc is employed for the experimental investigation presented in Section III,while C ′

dc is used for the tests shown in Section IV.)

converter to clear the shoot-through current. Assuming fixednumbers of primary and secondary turns in T/F1 and a certaincore type (the corresponding values of L1 and L2 equal 16.7 μHand 167 mH, respectively), the time required for vsu to reach acertain value is proportional to the value of C1 . The required timefor the startup converter to supply an output voltage vsu whichexceeds Vpi for Ctot=123 nF (Cic=100 nF, C1=17 nF, andCgs,m = Cgs,aux = 3 nF) equals approximately 5.5 μs, while inthe case of Ctot = 830 nF (C1 = 720 nF), the corresponding timewas found to be 42 μs. The turn-OFF time mainly depends on thetime constant of the resonant circuit. If the design of T/F1 is keptconstant, the turn-OFF time, toff , of the JFETs depends only on√

Ctot . As expected, the response of the startup converter witha low value of Ctot is significantly faster compared to largervalues. However, the stored energy in a low-value C1 might notbe sufficient for keeping Jm and Jaux in the OFF state.

B. Experimental Results

The performance of the SPGD and especially the response ofthe startup converter were experimentally evaluated using a half-bridge converter rated at 2.5 kW [18]. This converter consistsof two normally-ON SiC JFETs and operates as a dc/dc step-down converter (see Fig. 4). Depletion-mode vertical-trenchJFETs have been employed as both main and auxiliary JFETs.However, other types of normally-ON SiC JFETs, as for instancethe lateral-channel JFETs, could have also been used if propermodifications are performed (i.e., proper dimensioning of thestartup converter, adjusting of the output voltage of the steady-state converter, etc.). The shoot-through currents, IJm

and IJa u x

are limited by means of the startup resistor Rstartup , while asilicon insulated-gate bipolar transistor (IGBT) emulates thefunction of the dc-breaker. The parameters of the half-bridgetest circuit, as well as the most crucial device parameters of thenormally-ON SiC JFETs, are summarized in Table I. It mustbe noted that for the current investigation, the dc-breaker isconnected between Cdc and the SiC JFETs.

5132 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014

TABLE IPARAMETERS OF THE HALF-BRIDGE TEST CIRCUITS

Direct voltage, Vd c 300 VCapacitor Cd c and C ′

d c 160 μFStartup resistor, R s t a r t−u p 18 ΩMaximum duty ratio, Dm a x 0.5Main and auxiliary SiC JFETs, SJDP120R085Jm 1 , Jm 2 , and Ja u x (1200 V/ 27 A)Pinchoff voltage of Jm 1 , Jm 2 , and Ja u x −5 VReverse breakdown voltage of the gates, Vb r , g 24.2 V, −22.6 Vof Jm 1 ,Jm 2 , and Ja u x and −23.2 VON-state resistance of Jm 1 and Jm 2 85 mΩ

at room temperatureChip area of Jm 1 and Jm 2 4.3 mm2

In order to investigate the influence of the startup converterparameters, two sets of measurements were performed. Duringthe first one, the shoot-through current IJa u x was kept constant,while two different values of C1 were used. On the other hand,the second set of measurements was made using a constant valueof the output capacitor, while IJa u x was adjusted to three dif-ferent values by means of different startup resistors, Rstartup .It must be noted that the values of the remaining passive com-ponents of the startup converter were kept constant during thesecond investigation.

Figs. 5(a) and (b) shows the startup process when the outputcapacitor of the startup converter, C1 , equals 17 and 720 nF,respectively. The two values of C1 were chosen in order to showthat the function of the startup converter is not very sensitiveto the choice of C1 . Lower values than 17 nF or higher than720 nF could also have been chosen. It can be seen that usingthe lowest value for C1 , lowest value for Ctot , the shoot-throughcurrent IJa u x (shown with the green line) is turned OFF withinapproximately 15 μs, while in the case of C1 = 720 nF, thecorresponding turn-OFF time is approximately 70 μs.

During the startup process, the temperature rise of the chips isalso crucial to be found. Assuming an adiabatic process duringthe heat up of the JFET chips, the temperature rises for the pro-cesses shown in Figs. 5(a) and (b) have been estimated. Takinginto account that the active chip area and the thickness of thechips equal 3.06 mm2 and 265 μm, respectively, the specificheat coefficient is equal to 750 J/kg · K and by calculating theenergy dissipation in the chips from the experimental wave-forms, the expected temperature rises were found to be 1.05 ◦Cin the case of Fig. 5(a) and 5.23 ◦C in the case of Fig. 5(b). Itmust be highlighted that for these calculations, it was assumedthat the total shoot-through current during the startup processflows through only one JFET (either Jm or Jaux ), which canbe considered as a worst-case analysis. Even though this is aworst-case scenario, the temperature rise of the chips is verymoderate.

Apart from the required time to turn OFF the SiC JFETs andthe expected temperature rise of the chips, the output voltage ofthe startup converter must be kept sufficiently negative until thesteady-state converter is enabled. Figs. 6(a) and (b) illustratesthe complete startup sequence when C1 equals 17 and 720 nF,respectively. A slight increase of the gate–source voltage (yellow

Fig. 5. Measured gate–source voltage of the main SiC JFET: Jm (yellowline, 5 V/div), drain–source voltage of Jm (pink line, 50 V/div), shoot-throughcurrent IJ a u x (green line, 10 A/div), sum of the short-circuit currents flowingthrough Jm and Jaux , (purple line, 10 A/div) for (a) C1 = 17 nF (time base 10μs/div) and (b) C1 = 720 nF (time base 100 μs/div).

line) is observed in the case of C1 = 17 nF, while for C1 = 720nF, Vgs is constant.

Based on the information shown in Figs. 5 and 6, it is obviousthat a low value of the output capacitance might result in afaster turn-OFF process of the shoot-through current, but also ina faster discharge of Ctot . If the value of C1 is chosen to be verylow, the normally-ON SiC JFETs might accidentally turn ONbecause ΔWm > ΔWcrit . If, on the other hand, a sufficientlylarge capacitor value is chosen the corresponding toff time mightbe long, which might also result in excess heat dissipation inthe JFET chips. All in all, choosing the value of C1 is a tradeoffbetween the response time and the stable operation of the startupconverter.

A second set of measurements using three different valuesof Rstartup (i.e., three different shoot-through currents) and aconstant value of C1 = 200 nF have also been performed. Theturn-OFF times of the shoot-through currents, as well as the ex-pected worst-case temperature rise of the chips are summarizedin Table II.

According to Table II, the turn-OFF time, toff becomes longeras the sum of the shoot-through currents is decreasing. In asimilar way, the expected worst-case temperature rise of the

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Fig. 6. Measured startup sequence for (a) C1 = 17 nF and (b) C1 = 720 nF.[Gate–source voltage of the main SiC JFET Jm (yellow line, 5 V/div)], drain–source voltage of Jm (pink line, 50 V/div), and sum of the short-circuit currentsflowing through Jm and Jaux , (purple line, 10 A/div) (time base 5 ms/div).

TABLE IIEXPERIMENTAL RESULTS FOR THREE DIFFERENT SHOOT-THROUGH CURRENTS

AND C1 = 200 NF (Ctot = 306 NF)

Experiment R s t a r t−u p [Ω] IJ m + IJ a u x [A] to f f [μs] ΔT [◦C]

1 18 17 25 1.632 36 8.5 55 1.233 54 5 80 1.15

chips, shown on the last column of this table, is also decreasingwhen the shoot-through currents are reduced. Moreover, it mustbe highlighted that the startup converter is activated even if thesum of IJm

+IJa u x is low (i.e., 5 A).An additional design constraint of the SPGD deals with the

rising time of the shoot-through current, which is associatedwith the line impedance of the circuit. A slow rising rate of theshoot-through current might result in longer activation times forthe startup converter. However, the heat dissipation during thisprocess is not impairing the expected lifetime of the chips. As-sume a cable of 100 m which has an inductance of approximately100 μH [19] and Rstartup=18 Ω. The corresponding time con-stant equals 5.56 μs and during this time the expected, worst-case temperature rise of the chips is calculated to be merely

Fig. 7. Measured gate–source voltage of the main SiC JFET: Jm

(yellow line, 5 V/div), drain–source voltage of Jm (pink line, 50 V/div) andsum of the short-circuit currents flowing through Jm and Jaux , (purple line, 5A/div) (time base 2 ms/div).

Fig. 8. Measured gate–source voltage of the main SiC JFET: Jm (yellowline, 5 V/div), drain–source voltage of Jm (pink line, 50 V/div) and sum of theshort-circuit currents flowing through Jm and Jaux , (purple line, 5 A/div) (timebase 5 ms/div).

0.007 ◦C. Instead, the significant heat dissipation occurs duringthe turn-OFF process of the shoot-through current, where thechips are operating in the active region. Even in this case, it hasbeen shown that the maximum temperature rise is approximately5 ◦C in the worst case. Even though this is a rough estimation ofthe temperature rise in the chip, the robustness of the SiC JFETsunder short-circuit mode and at elevated temperatures has beenexperimentally shown in [20].

IV. SYSTEM LIMITATIONS

The performance of the proposed SPGD for normally-ON SiCJFETs along with design limitations from a system perspectivehave been presented in [18]. The most crucial limitations fromthe converter point-of-view are the low input-impedance path(has been shown in the previous section) for the shoot-throughcurrent and the careful design of the shut-down process of theSPGDs.

Apart from these two limitations, an additional limitation isassociated with the placement of the silicon IGBT (dc-breaker)

5134 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014

in the test circuit shown in Fig. 4. In the half-bridge converterused to show the performance of the SPGD concept in [18],the dc-breaker was connected after Cdc . Thus, when the startupwas initialized, the dc-link capacitor had already been chargedand the shoot-through currents were only flowing through thenormally-ON SiC JFETs. In a real-power electronics converter,however, the dc-breaker is usually connected between the dcsource, Vdc and the dc-link capacitor, Cdc . In such a case, thecharging time of Cdc must also be taken into account whendesigning the SPGD. If this time is very long, the time requiredfor Cdc to reach the dc-link voltage will also be long, and thus,the steady-state converter will not be able to operate the same asfast as in the case where the dc-breaker is connected after Cdc .Under this situation, it is again the startup converter which mustbe properly dimensioned.

The test circuit has been modified such that the dc-breakeris connected between the direct voltage source and the dc-linkcapacitor, C ′

dc , as shown in Fig. 4 with the dashed lines. Whenthe startup process is initialized, apart from the sum of the shoot-through currents of Jm and Jaux , an inrush current Irs is flowingthrough the dc-link capacitor and C ′

dc is charged.Fig. 7 shows the startup process when the modified test circuit

was used. A longer time, which approximately equals 12 ms,is required for the drain–source voltage in order to reach theblocking voltage of the JFET compared to the previous caseshown in Section III.

Last but not the least, in the case where Cdc is connected afterthe dc-breaker, the shut-down process must also be considered.During the shut-down process of the converter, the SPGD mustcontinue operating with a proper pulse width modulation signal,so that the energy of C ′

dc will be dissipated to the load. However,if the stored energy on Ctot and C2 is lost before C ′

dc is fullydischarged, C ′

dc must be discharged by means of an externaldischarging circuit. An example where the energy stored in theoutput capacitors of the startup and steady-state converters ofthe SPGD is lost before C ′

dc is fully discharged is shown inFig. 8. As a result, the shoot-through current is flowing throughthe SiC JFETs as shown with the purple line in this figure whichmight be severe for the expected lifetime of the devices. Thisissue, however, is not treated in the current letter, but it is leftfor future investigation.

Even though the high-temperature packaging technology forSiC power devices is still at an early development stage, afew design considerations for high-temperature operation ofthe SPGD can be made. Vital components of the SPGD, asfor instance, the IC-driver, optocoupler, and low-voltage diodesrequire special high-temperature packaging. Additionally, pas-sive components, e.g., capacitors, transformers, etc. need to beproperly dimensioned since their performance are temperaturedependent, and the same also applies for the resistors. In con-junction with these, the temperature variations of various deviceparameters (e.g., Vpi , Vbr,g , etc.) must also be taken into account.In particular, Vpi has shown to be temperature unaffected, whilethe temperature dependence of Vbr,g is different for differentSiC JFET designs [21].

V. CONCLUSION

In this letter, design considerations for the SPGD fornormally-ON SiC JFETs along with limitations from a systemperspective are presented. It has been shown that the most vitalpart of the SPGD is the startup converter, which must be prop-erly designed in order to ensure a stable operation of the SPGD.A theoretical analysis of the startup converter reveals that thisis basically a parallel LC resonant circuit that only operates forthe first quarter of the first time period. From experiments, ithas been shown that the selection of the passive components isgoverned by a tradeoff between the time required for turningOFF the shoot-through currents and the stable operation of theSPGD. Moreover, it has been proven that even with a very lowvalue of the shoot-through current, the startup converter is alsoable to supply an adequately negative voltage in order to turnOFF the SiC JFETs.

Finally, the SPGD was also evaluated in a more realisticconverter case, where the dc-link capacitor is not charged priorto the startup process. It was experimentally shown that theSPGD is also able to operate under this condition. However, thecorresponding time in order to clear the shoot-through currentsis slightly longer.

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