IEEE TRANSACTIONS ON EDUCATION, VOL. 49, NO. 3, AUGUST 2006 321

RACFP: A Training Tool to Work WithFloating-Point Representation, Algorithms,

and Circuits in Undergraduate CoursesRafael Ubal, Juan-Carlos Cano, Salvador Petit, and Julio Sahuquillo, Member, IEEE

Abstract—The design of pedagogical tools to train students isan interesting challenge for academic instructors in any educa-tional area. Some approaches have appeared focusing on computerarithmetic, both integer and floating point. Floating-point arith-metic involves much more complexity; nevertheless, little time isusually devoted to this topic in computer engineering undergrad-uate courses. In this paper, RACFP is proposed as a pedagogicaltool to work with floating-point in undergraduate courses. The toolhas been designed with three abstraction levels according to thefollowing learning outcomes: representation, arithmetic operationalgorithms, and manufactured hardware circuits. The abstractionlevels work independently, allowing for the use of RACFP in othercourses, such as discrete mathematics or numerical methods, inwhich floating representation and related issues are also learningtopics. RACFP design pursues two main goals: to minimize thecomplexity of the learning process and to encourage students whenworking with floating point. The first goal is achieved as a result ofthe multilevel design of the tool, while the second goal is achievedas RACFP shows how manufactured hardware implements genericalgorithms.

Index Terms—Computer arithmetic, computer curricula,floating point, numerical information, numerical representation.

I. INTRODUCTION

COMPUTER arithmetic is a fundamental discipline under-lying many modern digital technologies. Many scientific

and engineering fields, such as networks security, encryp-tion, signal processing, or video streaming, make extensiveuse of software algorithms and hardware implementations,which work with numerical computing as essential basis [1].Furthermore, a countless number of scientific problems de-pends on efficient computer arithmetic algorithms to be solvedproductively.

Computer scientists and engineers should acquire a soundfoundation about those computer arithmetic issues since theymay affect both precision and performance. Not paying thor-ough attention to numerical analysis or arithmetic circuit designcould be a costly mistake. In [2], Huckle presents a detailed col-lection of both software and hardware bugs attributable to er-roneous numerical computing. Some of those bugs shocked the

Manuscript received March 21, 2005; revised March 28, 2006. Thiswork has been partially supported by the Generalitat Valenciana undergrants GV06/326 and GV05/245, and by the Spanish CICYT under GrantTIC2003-08154-C06-01.

The authors are with the Polytechnic University of Valencia, 46022 Valencia,Spain (e-mail: raurte@inf.upv.es; jucano@disca.upv.es; spetit@disca.upv.es;jsahuqui@disca.upv.es)

Digital Object Identifier 10.1109/TE.2006.879240

world and caused real-life disasters. For instance, the VancouverStock Exchange [3] in 1982 caused a financial catastrophe withthe introduction of a new economic index, and the Patriot Mis-sile failure in Saudi Arabia [4] in 1991 during the Gulf Warresulted in 28 deaths. Most of the critical mistakes because ofnumerical computing bugs appeared because of inaccurate al-gorithm analysis, although other important errors were a resultof inaccurate arithmetic circuit design. For instance, in 1997, aserious design flaw was found in the floating-point unit of theIntel Pentium II and Pentium Pro microprocessors [5], whichmight lead to inaccurate results in some common mathematicalfunctions (e.g., sin, cos, and tan).

Numerical representation inside computers mainly includesnatural, integer, and real numbers. Natural or unsigned integernumbers are straightforwardly encoded to binary. The mostcommon technique to represent integer or signed integer num-bers is two’s complement representation. This alternative hasbeen adopted since 1965, because it makes hardware imple-mentation simple [6]. To represent real numbers or numberswith fractions, several representations have been used. Twentyyears ago, the IEEE proposed the IEEE 754 standard forfloating-point arithmetic [7], which became the reference forhardware designers.

Unlike integer representation, in which each number is ex-actly represented, floating-point representation is inaccurate bynature, because there are infinite real numbers between any tworeal numbers, and computers use a finite number of bits (e.g.,32 or 64 bits) to represent them. Consequently, most numberscannot be exactly represented, and rounding methods are usedto get a close representation of the actual number.

Numerical computing is primarily related with floating point.Its study involves a large variety of topics, ranging from in-ternal representation to the design of complex circuits, e.g., asquare root Radix-2 circuit. Because of the complexity involvedin floating point, a tradeoff is available for instructors to in-troduce these subjects to undergraduate students. In this sense,some approaches have been proposed to work with this tradeoff.

Earlier works [8]–[10] proposed the use of pedagogicalcomputer programs to check floating-point arithmetic issues,including properties like cancellation and stability. For ex-ample, Overton’s book [11] provides C programs to illustratethe IEEE 754 standard properties. This approach is useful tostudy numerical analysis topics, which are mainly covered ingraduate courses. More recently, an important set of litera-ture has focused on simulation tools to help students acquirefloating-point skills. In this context, Fernández et al. proposed

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322 IEEE TRANSACTIONS ON EDUCATION, VOL. 49, NO. 3, AUGUST 2006

an educational tool [12] to handle numerical representationand computer arithmetic addressed to undergraduate courses.Koren proposed a simulation tool to work with arithmeticalgorithms [13] that implements a wide range of floating-pointoperators. Although this simulator is primarily addressed tograduate courses [14], its basic function can also be used inundergraduate courses.

In this paper, RAC is presented as a software tool aimedat helping students with FP representation, algorithms, and cir-cuits. This pedagogical training tool is addressed to undergrad-uate courses in computer science and computer engineering.The tool has been designed by emphasizing pedagogical pur-poses as a whole. For this purpose, the floating-point issues havebeen classified into three abstraction levels according to the ex-pected learning outcomes. The first level includes internal repre-sentation and related issues. The intermediate level works withgeneric algorithms, e.g., the operation of addition and multipli-cation. The third level introduces students to the real world withexamples illustrating how manufactured operators work.

The main novel aspect of this approach lies in the factthat RAC shows how manufactured hardware implementsgeneric algorithms for common arithmetic operations. Themain aim behind this approach is to help students gain soundknowledge about generic algorithms and their related hardwareimplementation.

The rest of this paper is organized as follows. Section II sum-marizes IEEE 754 floating-point representation, presents inter-national guidelines, and discusses how RAC matches them.Section III describes the proposed pedagogical training tool.Section IV includes a set of practical exercises to cover thelearning objectives and describes how RAC can be used tosolve them. Section V presents the teaching context and eval-uates the effectiveness of RAC . Finally, Section VI presentssome concluding remarks.

II. TEACHING FLOATING POINT: REPRESENTATION,ARITHMETIC AND CIRCUITS

A. IEEE 754 Floating-Point Representation

During the early 1980s, the IEEE 754 standard was the firstsuccessful effort to standardize floating-point representationacross systems. The standard was so successful that it wasimmediately followed by the main chip manufacturers of thattime, Intel and Motorola.

Floating-point representation is based on the scientific nota-tion of real numbers. In scientific notation, a real number iswritten as , where is a real number, is a fixednatural number, and is an integer. The variables , , andare called mantissa, base, and exponent, respectively. A givenreal number can be written in different ways by varying the valueof . For example, the decimal number 362.25 can be writtenas , , , or .The last two notations, where the decimal point is just after orjust before the first nonzero digit, have been used as normalizednotations. When using the binary base, which is the one used incomputers, a real number is written as . IEEE754 standard uses a nonzero digit before the binary point as the

TABLE ISINGLE AND DOUBLE-PRECISION FLOATING-POINT FORMATS

TABLE IIIEEE 754 ENCODING OF FLOATING-POINT NUMBERS. N REFERS TO THE

NUMBER OF BITS OF THE EXPONENT

normalized notation for the mantissa. Therefore, the most sig-nificant bit of the mantissa is always 1, and is expanded as

.When using the standard, a real number is encoded as a se-

quence of bits split into three fields: sign of the mantissa, ex-ponent, and mantissa. The sign of the mantissa is set to zeroor one, to represent positive or negative numbers, respectively.The exponent is encoded in integer-biased representation. Onlythe fractional part of the mantissa is represented, thus the termfraction is also used to refer to this field. The standard pro-vides different formats to encode real numbers; the two mostwidely used, single precision and double precision, are shownin Table I.

IEEE 754 standard reserves two values of the exponent torepresent special events, i.e., or (for single precision and for double precision). In bothcases, the represented number depends on the value of fraction

. Table II summarizes the IEEE 754 encoding of floating-pointnumbers.

B. Floating-Point in International Curricula

Academic institutions worldwide consider curricula recom-mendations from international professional societies when de-signing in order to choose the topics of the offered courses.The most important curricula recommendations are those pro-posed by the Joint IEEE Computer Society and the Associa-tion for Computing Machinery Task Force on Computing Cur-ricula [15]–[17]. Each curriculum guideline defines the body ofknowledge for that field, that is, the topics the field should cover,and the number of courses proposed to cover them. Each coursecan be core or elective, with core courses considered as essen-tial to anyone obtaining the undergraduate degree.

The recently published 2004 guidelines break down theguidelines for undergraduate degree programs in four com-puting disciplines: Computer Science, Computer Engineering,

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Software Engineering, and Information Systems. Each com-puting discipline has its own identity and learning objectives,with floating point being a common topic in all the disciplines.Computer Engineering is the computing discipline that mostemphasizes floating point because it involves, among others, thetechnology for the design, construction, implementation, andmaintenance of the hardware and the software components ofmodern computing systems. Computer Engineering curriculumguidelines [16] include the Computer Arithmetic core. Topicsof this core related to floating point are as follows.

1) representation of real numbers (standards for floating-pointarithmetic);

2) multiprecision arithmetic;3) algorithms for carrying out common floating-point opera-

tions;4) significance of range, precision, and accuracy in computer

arithmetic;5) hardware and software implementation of arithmetic units.These topics pursue the following learning outcomes:• to appreciate how numerical values are represented in dig-

ital computers;• to understand the limitations of computer arithmetic and

the effects of errors on calculations;• to appreciate the effect of the processor arithmetic unit on

its overall performance.The floating-point learning outcomes of the other disciplines,

i.e., Computer Science, Software Engineering, and InformationSystems, can be seen as a subset of this one.

C. Matching the International Curricula

This section discuses, level by level, how RAC matchesthe learning outcomes and topics of the Computer Engineering2004 curriculum.

1) Numerical representation and notation conversion: Thislevel permits students to practice with representation andnotation-conversion exercises. RAC works both withIEEE 754 floating-point representation (both single anddouble precision) and with custom formats. Representa-tions of special values (e.g., zero, infinity, NaN, etc.) havealso been taken into account. Both standard and customformats can be input in three different notations: decimal,binary, and hexadecimal. For example, a single-precisionIEEE number can be input using 32 bits, eight hexadecimaldigits, or in decimal notation. The implemented customformats follow the standard to represent the mantissa andthe exponent, but they allow the user to choose the numberof bits of these fields. This feature permits practice withsmaller formats, which facilitates the understanding ofthe subtleties of the IEEE 754 standard. An example isto analyze the range–precision tradeoff. Therefore, thisfunctionality becomes a valuable educational help. Thislevel covers topics 1 and 2 of the Computer Engineeringcurriculum.

2) Arithmetic algorithms: This level permits students to prac-tice with algorithms for arithmetic operations. It allows stu-dents to follow step by step how the algorithm works. For abetter understanding of the algorithm, the tool also displaysintermediate results. To practice with a given algorithm,

Fig. 1. Main window of the RAC application.

students must select the desired algorithm (e.g., additionor multiplication), the rounding method (e.g., towardor toward zero), and the corresponding operands. The tooldraws the algorithm flow diagram as described in Pattersonand Hennessy’s book [6], widely referenced in computerorganization courses. These diagrams have been imple-mented because of their teaching value. This level coverstopics 2–4 of the Computer Engineering curriculum.

3) Hardware circuits: Once students understand how genericalgorithms work, they can follow on this level, which intro-duces students to the real world. Therefore, this level usesblock diagrams to emulate manufactured operators. As inthe previous level, the tool also displays step-by-step inter-mediate results, thus helping students to understand howhardware implementation matches generic algorithms. TheHewlett-Packard (HP) floating-point adder and multiplier[18] were selected because their simplicity, functionality,and straightforwardness follow the generic algorithms [1].Both circuits are implemented on a single VLSI chip andused in several systems. This level mainly covers topic 5of the Computer Engineering curriculum.

III. RAC TOOL

RAC has been implemented using the visual programmingenvironment Borland Delphi Enterprise version 7.1 The currentversion has been tested under Windows and Linux operatingsystems. This section describes the user interface. Fig. 1 showsthe main window, which displays the main functionalities ofthe tool and gives access to the desired abstraction level (seeSection II-C). Below, the steps that the user must follow to prac-tice with each level are described.

A. Numerical Representation and Notation Conversion

To work with floating-point representation or conversion,users should click on the Conversion button in the main

1Borland Sofware Corporation, Borland Delphi 2005 Enterprise Version,available: http://www.Borland.com

324 IEEE TRANSACTIONS ON EDUCATION, VOL. 49, NO. 3, AUGUST 2006

Fig. 2. Example of representation and conversion.

window. A working example illustrates how this part of theapplication functions. Suppose that one wants to convert thenumber 2.5 to the single-precision IEEE 754 format. Fig. 2shows how this number is entered by selecting decimal notationthrough the Enter the number dialog. The fields for the selectionof the number of bits of the exponent and mantissa are onlyavailable when the custom format is selected. When the userclicks on the Ok button, the program opens a new dialog calledInformation about the number, which shows the details of theinternal representation and displays the number as representedin the three implemented notations (i.e., binary, decimal, andhexadecimal). Looking at Fig. 2, one can observe how the toolcan be easily used to convert real numbers written in decimalnotation to the IEEE standard (or custom) format, and viceversa.

B. Arithmetic Algorithms

To practice with arithmetic algorithms students should clickon the button corresponding to the desired algorithm in the mainwindow. Two algorithms are currently available which imple-ment common arithmetic operations, i.e., addition/subtractionor multiplication/division. In a working example, suppose thatone wants to add the real numbers 2.5 and 1.2. To do so,one should select the Addition/Subtraction button in the mainwindow. Then, RAC opens a new dialog that displays thecontrol flow diagram of the selected algorithm.

Before running the algorithm, the user should enter the infor-mation needed to complete the operation, i.e., the operands, therounding method, and the operation itself. Fig. 3 shows both theOperation input dialog available to enter this information andthe flow diagram corresponding to the algorithm. The tool im-plements the four rounding methods of the IEEE 754 standard:round toward the nearest even number (default), toward 0, to-ward , and toward .

Once the required information has been entered, the algo-rithm runs step by step by clicking on the Next button. Fig. 4shows the output of steps 1 and 4, corresponding to the previousexample. A text box at the bottom of the window provides de-tails concerning intermediate results.

Finally, note that the mantissa adder/subtractor can be im-plemented working in two’s complement or in sign-and-mag-nitude [1]. This fact can be fully transparent when studyingfloating point or one can emphasize the working details of thiscomponent. For instance, in an implemented sign-and-magni-tude adder/substractor, the effective operation carried out maydiffer from the encoded operation; e.g., an encoded sum of twooperands could be carried out as a mantissa subtraction [19].RAC provides this functionality through the Tables button inthe main window.

C. Hardware Circuits

Students can practice with hardware implementation byclicking on the corresponding button in the main window.Fig. 5 (left side) shows the block diagram of the selected HPadder. First, the circuit compares the exponents. Next, themantissa of the number with the smallest exponent is shifted,and both mantissas are added. In the next step, the circuitnormalizes supernormal mantissa results. Then, it normalizesthe result, including the normalization of possible subnormalmantissa results. The last step consists of checking for under-flow and overflow exceptions.

Once the operands are entered and the rounding method is se-lected, RAC emulates step by step the adder/subtractor, pro-viding details for each component in an interactive way. As theuser moves the mouse pointer over a given component, an emer-gent Element description dialog provides information about thecomponent functionality and the results produced by the com-ponent. As example, Fig. 5 (right side) shows the information

UBAL et al.: RAC : A TRAINING TOOL 325

Fig. 3. Control flow diagram and input dialog of the addition/subtraction algorithm.

Fig. 4. Step-by-step execution of the addition/subtraction algorithm.

provided by three components: the right swap, the priority en-coder, and the generate constant, corresponding to the additionof 2.5 and 1.2.

The case study for the adder is a single chip developed by HP[18].

Fig. 6 shows the block diagram of the selected HP multiplier/divider, which works as follows. In the first step, the operandsare unpacked and masked to the proper precision. Next, the mul-

tiplier adds the exponents, recodes the mantissa of the multiplieroperand in a signed bit notation, and multiplies the mantissasusing a CSA (Carry Save Adder) array. Then, the sign is cor-rected, and the partial sum and carry bits from the CSA arrayare assimilated. Next, the result is normalized and rounded. Fi-nally, as in the adder example, the last step consists of checkingthe exponent for underflow and overflow exceptions. (See [1]and [18] for further details.)

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Fig. 5. Block diagram of the HP floating-point adder and some information dialogs.

Fig. 6. Block diagram of the HP floating-point multiplier.

IV. PRACTICAL EXERCISES

This section presents a number of practical exercises aimedat illustrating RAC pedagogical features. The exercises are

designed to show instructors how RAC can be used for edu-cational purposes. Below, exercises are grouped into three cate-gories according to the three abstraction levels.

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TABLE IIISUMMARY OF PRACTICAL EXERCISES DEALING WITH REPRESENTATION

A. Practical Exercises Working With Numerical Representationand Conversion

Exercises in this category focus on floating-point (bothstandard and custom formats) representation and related issues.Table III summarizes the learning objectives of this categoryand includes some examples of exercises that could be carriedout with RAC to reach these objectives. For illustrativepurposes, a subset of these exercises is discussed below.

• Determine the minimum number of bits in the exponentfield, when using the custom format, to represent 16.0.The largest representable mantissa is always less than 2.0since it is , independently of the number of bits inthe mantissa. The equation should be expressed as

, where exp is the represented exponent. Tosolve the equation, exp should be at least 4. Therefore, thequestion is, How many bits in the exponent field are re-quired to represent the number 4? As the exponent is rep-resented in biased notation excess , the rangecovered by the exponent field is [ excess, excess] (ex-cluding special events). Therefore, it must be fulfilled that

; thus, at least 4 bits are needed.Table IV shows the maximum representable value whenvarying the number of bits in the exponent and assuming

TABLE IVMAXIMUM REPRESENTABLE NUMBER FOR A 5-BIT MANTISSA AND VARYING

THE NUMBER OF BITS OF THE EXPONENT

TABLE VANALYSIS OF THE REPRESENTATION PRECISION WHEN INCREASING THE

NUMBER OF BITS IN THE MANTISSA

a 5-bit mantissa, as calculated by RAC . As observed,the range exponentially rises with the number of bits in theexponent.

• Represent 1.2 assuming a 10-bit exponent field andvarying the number of bits of the mantissa from 5, 7, 9, to11. Calculate the precision of the representation on eachcase. This kind of exercise is useful to understand howthe number of bits in the mantissa affect the precision ofthe representation. Table V shows the results provided byRAC . As observed, precision increases as the numberof mantissa bits also increases.

• Represent 8.25 and in the IEEE 754 single-precisionformat. Present the results in hexadecimal notation. Thismodel of exercise represents the basis for the teaching ofthe IEEE 754 standard representation. After representingthe number using paper and pencil, RAC can be used tocheck the solution. The tool provides the IEEE representa-tion of the real number and the details of the representationprocess.

• Indicate which is the largest representable decimal numberwhen using IEEE 754 single precision. Obtain the corre-sponding decimal value using RAC . The largest repre-sentable value will be given by both the greatest exponentand mantissa. The greatest exponent for normalized num-bers is 11111110 (since 11111111 is reserved for specialevents), and the greatest mantissa is 11 11. The resultprovided by RAC is .

• There are infinite numbers whose decimal representa-tion has finite length, but whose binary representation isperiodic (i.e., infinite). For example, the binary represen-tation of 1.7 is periodic. Represent this number usingthe IEEE 754 standard single precision and calculate therepresentation error (in percentage). Assume the defaultrounding method. The error because of the representationis .

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TABLE VISUMMARY OF PRACTICAL EXERCISES DEALING WITH ARITHMETIC

Other exercises also useful for representation teaching pur-poses are as follows.

• Numbers 1, 8, 64, 1, 8, and 64 are exactly rep-resented by the IEEE standard. For each number, obtainthe closest greater number representable by the standardand its corresponding distance. Why are not all distancesequally long?

• Can the number be represented in the IEEE 754double-precision format?

B. Practical Exercises Working With Arithmetic

Table VI summarizes the learning objectives and some ex-amples of practical exercises dealing with generic algorithmsfor common arithmetic operations. Below a subset of these ex-ercises is described.

• Calculate step by step and, where the numbers are rep-

resented in IEEE 754 single-precision format. Use RACto check the working details and the intermediate results ofthe different stages of the algorithm. This type of exercisecan be used to reinforce the understanding of a particularstep of the algorithm.

• Using paper and pencil, calculate the sum . UseRAC to check the result. This type of exercise combinesboth representation and arithmetic topics.

• Table VII shows some examples of arithmetic operationscausing exceptions. Identify the corresponding exceptionand check the result provided by RAC . By observing thelarge exponents of the operands used in the addition andmultiplication operations, one can deduce that the resultwill be too large to fit in the range covered by the standard.Therefore, RAC detects overflow and represents the re-sult as infinity. In the division, operation underflow occurs

TABLE VIIEXAMPLES OF ARITHMETIC OPERATIONS CAUSING EXCEPTIONS

since the result is too close to zero to be represented in thestandard.

Other exercises falling into this category are as follows.• Follow the addition algorithm to calculate . Use

RAC until the algorithm reaches the fourth step (roundthe mantissa). In this step, using paper and pencil, calculatethe results for the four rounding methods (i.e., toward ,toward , toward zero, and toward the nearest even).Check your results with those provided by the tool.

• Using paper and pencil, carry out the addition. Calculate which

of the four rounding methods will cause overflow. UseRAC to check the results.

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TABLE VIIISUMMARY OF PRACTICAL EXERCISES DEALING WITH CIRCUIT IMPLEMENTATION

C. Practical Exercises Working With Circuit Implementation

In spite of the undoubtable importance of the hardware, mostcurrent undergraduate courses do not include exercises fallinginto this category. As a consequence, in general, students feelthat arithmetic exercises in undergraduate courses have no re-lation with manufactured hardware. One of the main goals ofRAC is to introduce students to manufactured hardware be-cause the authors believe this introduction is the best way to en-courage students to work with floating point. Table VIII summa-rizes the learning objectives and some exercises working withhardware implementation. Below a subset of these exercises isdescribed.

• A component of the normalization stage in the HPadder/subtractor circuit is the priority encoder. Calcu-late its output value when performing the subtraction

. How is this value used in the next stage? Thevalue calculated by the priority encoder for this subtractionis 000011. This part of the circuit identifies the positionof the first significant bit, i.e., its output states how manybits the mantissa must be shifted to be normalized andhow much the exponent must be decreased. Therefore, theencoder output value is used both by the left shifter andthe decrement components of the following stage.

• Which stages are in charge of the mantissa multiplicationin the HP multiplier circuit? Why is there more than onestage for this task? Stages four and five carry out the man-tissa multiplication. Two stages are necessary for this taskbecause of its complexity. Stage four is in charge of cal-culating and adding the intermediate products of the mul-tiplication, a step that can be done immediately. This stageprovides an addition bit array and a carry bit array, whichare added in stage five.

Other exercises designed for the study of hardware imple-mentation are as follows.

• Calculate step-by-step the addition . Use RACto check the results for the different circuit stages.

• Use RAC with the operands offered in Table VII andcheck the stages where underflow or overflow occur in thecorresponding operators.

V. TEACHING CONTEXT AND EVALUATION

The proposed RAC tool has been used in the three-yearBachelor’s degree in computer engineering of the Polytechnic

University of Valencia (UPV), Valencia, Spain. Lecture topicsin computer organization are organized into two courses: Com-puter Fundamentals and Computer Organization. Both coursesare core subjects offered in the first and second year of the de-gree, respectively. Each course is attended by more than 600students, a number that strongly affects classroom and labora-tory organization since 12 instructors are currently involved ineach course.

The main topics covered by Computer Fundamentals are dig-ital logic (35%), data representation (15%), assembly language(25%), and simple processors (25%); while topics covered byComputer Organization are memory unit (25%), input–outputunit (25%), arithmetic-logic unit (25%), and pipelined proces-sors (25%). Floating-point representation is studied in the firstcourse, while floating-point arithmetic (algorithms and hard-ware) is studied in the second-year course.

An initial version of RAC was developed and used for nu-merical representation in the Computer Fundamentals course.The main reason to develop RAC was that the time allottedto arithmetic representation is limited. When students usedRAC , learning effectiveness increased considerably, and stu-dents improved their grades (i.e., those related to floating point)by about 25% with respect to the students grades of the previousacademic year. In addition, instructors also observed that theyspent much less time solving floating-point questions duringtheir office hours. This fact encouraged the instructors to extendRAC to cover floating-point arithmetic. This academic yearRAC has been used for the first time in the second-yearcourse, in which the complexity of the floating-point topicsis higher. Again, the results have been encouraging becausestudents grades have improved (by about 30%) with respect tothe first-year course.

An evaluation study based on self-assessment was also devel-oped. For this purpose, at the end of the 2004–2005 academicyear (June 2005), a brief questionnaire was used. About halfof the students completed and returned the questionnaire. Theaim of the questionnaire was to assess how the RAC fea-tures help students through their learning process. The questionsfocused on both how RAC improves the understanding offloating-point topics and how RAC motivates students whenattending classes or when studying these topics.

Table IX summarizes the most relevant items of the question-naire. Responses were on a 10-point scale, where 10 and 1 in-

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TABLE IXSOME RESULTS FROM THE QUESTIONNAIRE

dicate a strong acceptance or rejection of the RAC tool, re-spectively. A response of 5 means the student’s indifference.As expected, the tool encourages students to do more exercisessince floating-point exercises are, in general, long and difficultto do when using paper and pencil. Furthermore, their confi-dence improves although the amount of time spent by studentsin the exercises does not apparently increase. Finally, in spite ofRAC , encouraging students to work with floating point, re-sults do not evidence higher motivation when attending classes.

VI. CONCLUSION

This paper has presented RAC , a pedagogical training toolto teach floating-point representation and arithmetic in under-graduate courses. This tool was designed by emphasizing ped-agogical purposes as a whole. To this end, floating-point issueswere classified into three abstraction levels: numerical represen-tation, algorithms, and hardware implementation. These levelsmatch all the learning topics and outcomes proposed by the JointTask Force on Computing Curricula [17]. For each level, a repre-sentative compilation of practical exercises has been provided,with a short description of how the tool can be used to solvethem.

RAC permits the representation of floating-point num-bers, using IEEE 754 standard and custom formats. This featurepermits students to learn the subtleties of the standard using asmaller number of bits. The tool also implements a step-by-steprunning mode allowing students to be guided through all thelearning process. This running mode favors the use of RACfor self-training purposes. Therefore, instructors should preparea list of exercises with minimum documentation support.

In general, students feel that arithmetic exercises in under-graduate courses have no relation with manufactured hardware.To alleviate this misunderstanding and to encourage studentsto work with floating point, RAC shows how manufacturedhardware implements generic algorithms, the main novelty ofthe tool. To determine the success of this approach, an assess-ment study was performed by using a questionnaire. This studyshowed that, in general, the tool has good acceptance among thestudents. In fact, they are using RAC to do their homework,obtaining encouraging results. In this sense, the instructors haveseen how their grades have improved with respect to the pre-vious academic year.

The current version of RAC supports both English andSpanish and has been tested on Windows and Linux operatingsystems using the wine library (http://www.winehq.org/). TheRAC source code is available at http://www.disca.upv.es/jucano/utilidades.htm. Users can directly run the tool by usingits binary file and modifying its source code to add new func-tionalities (e.g., new algorithms). To facilitate this process,a programmer handbook [20] summarizes the main steps tofollow for the implementation of new components.

ACKNOWLEDGMENT

The authors would like to thank the anonymous reviewers fortheir useful comments.

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Rafael Ubal received the B.S. and M.S. degrees in computer engineering fromthe Polytechnic University of Valencia (UPV), Valencia, Spain, in 2004 and2006, respectively. Currently, he is working towards the Ph.D. degree in theDepartment of Computer Engineering at UPV. His Ph.D. research focuses onmultiprocessor architectures. He has worked so far in two main topics: floating-point and processor cache architecture, specifically in low-power designs.

Juan-Carlos Cano received the M.S. and Ph.D. degrees in computer engi-neering from the Polytechnic University of Valencia (UPV), Valencia, Spain,in 1994 and 2002, respectively.

From 1995 to 1997, he worked as a Programming Analyst at IBM’s manufac-turing division, Valencia, Spain. Currently, he is an Associate Professor in theDepartment of Computer Engineering at UPV. His current research interests in-clude power-aware routing protocols for mobile ad hoc networks and pervasivecomputing. His teaching interests include computer organization and computernetworks.

Salvador Petit received the Ph.D. degree in computer engineering from thePolytechnic University of Valencia (UPV), Valencia, Spain.

Currently, he is an Assistant Professor in the Computer Engineering De-partment of UPV. His main research topics of interest are distributed memorysystems, multiprocessor architectures, cache memories, core processor, andlow-power architectures design. His teaching interests include computerorganization and computer architecture.

Julio Sahuquillo (M’06) received the B.S., M.S., and Ph.D. degrees in com-puter engineering from the Polytechnic University of Valencia (UPV), Valencia,Spain.

Since 2002, he has been an Associate Professor in the Computer EngineeringDepartment at the UPV. His current research topics have included clustered mi-croarchitectures, multiprocessor systems, distributed memory systems, cachememories, processor core, and low-power architectures design. A part of hisresearch has also concentrated on the Web performance field. His teaching in-terests include computer organization and computer architecture.