2017.6 3

Issues in enlarging silicon wafer 1

12” 8” 6” 4”

80chips 180chips

300chips

1975~ 1980~

1991~

2001~

18”

700chips MAGA-trend

2020? 1600chips

Estimated by a chip size of 1cm2

(1) Huge investment

(2) Enormous waste

(3) Valley of death in R&D

[ハイテクものづくり.ppt]

(3) The Valley of Death in R&D

Mega Manufacturing

Minimal Way

[基礎の谷.ai]

Valley of Death

Facto

ry

Ind

ustria

l Re

sea

rch

Sectio

n

Pure

Scie

nce a

nd

Engin

eerin

g

Hig

h L

ost

Wide Gap

Hig

h In

ve

stm

en

t co

st

Lo

w In

ve

stm

en

t co

st

Industrial Implementation

Directly to the research facility

Research = Manufacture

3

Market

(1) Research sample size

(2) High quality control

by local clean technology

In this Minimal way, we can shrink the fab size.

To what degree do we shrink the fab size? 4

Number of WIP product types at a certain moment

In device fabs,

→ ～ 1,000 types @ a moment

1 type at a certain moment is an ideal fab.

Therefore, we make a fab of 1/1,000.

We call this fab of 1/1,000 “Minimal Fab”.

→ We use a tiny wafer intentionally.

Trend to enlarge silicon wafer 5

12” 8” 6” 4”

80chips 180chips

300chips

1975~ 1980~

1991~

2001~

18”

700chips MAGA-trend

0.5”

1chip

2010~

Minimal way

2020? 1600chips

Estimated by a chip size of 1cm2

Room-sized Minimal FAB

Traditional MAGA FAB

Scaling down of fabrication factory 6

200m 2m

10m 0.3m

wafer size: 0.5”

Fab investment 5B$

Fab investment 5M$

wafer size: 12”

1/1

,000

1/1

,000

No clean room

7

1 10 100 1,000 10,000 100,000 million 10million 100million

Ch

ip P

rices [

$/c

m2]

Life Production Volumes of Chips

Pri

ces o

f C

on

su

mer

Pro

du

cts

[$]

Price zone of

Major products

No one wants to

produce under

10,000 chips

Fabrication Design rules

40nm

60nm

90nm

130nm

180nm

250nm

Low

er

limit o

f consum

er

pro

duct

volu

me

Yearly capacity of Minimal fab

Primary

Target

Volume

Target Advanced

Target

Cost trends for production volumes

10

100

1,000

10

10

10

10

10

4

5

6

7

8

1

10

100

10

10

10

10

10

3

4

5

6

7

100B$/year 100B$/year

Variable Cost

Global Market

Minimal Hermetic-Seal Transfer System

Standardized Wafer Transfer system

Minimal

Lithography

Minimal

Plasma

Minimal

I/I

Minimal

･･････

Minimal

Analyzer

Minimal

High-tech.

Analyzer

Minimal

High-tech.

Process

minimal PLAD minimal PLAD minimal PLAD

Minimal

Inspection

minimal PLAD

Minimal

High-tech.

Fabrication

minimal PLAD

PLAD：Particle Lock Air-tight Docking

minimal PLAD minimal PLAD

Minimal

Specific

process

Minimal

Specific

Process

Research

MInimal

Coat./Dev. Minimal CVD

Minimal

Wet Cleaner

minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD minimal PLAD

Production / Development 30cm

8

Ultra rapid RD, and P

Minimal Shuttle

PLAD: Particle Lock Air-tight Docking system

Minimal Tool, Wafer, Shuttle 9

Half inch wafer: φ12.5mm

Minimal Shuttle

1440

PLAD: Particle Lock Air-tight Docking

A front chamber where particles are absolutely protected during opening

process of a shuttle

Process compartment

control compartment

PLAD

Minimal shuttle

Localized clean system for minimal fab

absolutely sealed wafer carrier

人

PLAD

Localized clean system （EPS：Encapsulated Production System)

no cleanwear

no cleanroom

Process machine

前室 PLAD

Machine No.1 Machine No.2 Machine No.3

UV cut carrier (shutle)

Process machine Process

machine

10

Measured Clean level of the system 11

September 17, 2011

Depositio

n

Coatin

g

Exposure

Develo

pm

ent

Etc

hin

g

Resis

t R

em

oval

Wet

Cle

anin

g

Mask-less DLP Exposure

Process Unit

Control Unit

Imperfect process Area

0.50mm

Non coating area

0.28mm

Resist pattern after exposure

No particle without clean room.

12

Resist: TOK, OFPR-5000 4000rpm, 25sec ~1.00micron, Develop: NMD-3 35sec

R&D&P subjects of minimal fab 13

[3] Process technologies

[1] Materials, Parts, Modules

[2] Process equipment

We have to develop:

[5] Factory system

[4] Devices

In order to construct a minimal fab,

Back-end

DISCO

Adwelds

Kumamoto Bosei

Ishii Tool & Eng.

Apic Yamada

Ishida Sangyo

SS Techno Shibuya Kogyo

KAIJO

Invented Local Clean Technology

System Design

Nanotech Design Network

KOYU Sanyo Systec Inoue

Digital Electronics Phenomena Entertainment

Passage Yamaha Motor

Oki Engineering

Algo system

Factory construction

Taisei Asahikogyosha UEKI corporation

Rikenkeiki Epoch transport

Solution Ochanomizu PAT

Sano PAT Takewa PAT

TOOL Azbil

Yokogawa Solution Service

Rigaku

NTT DATA Mathematical Systems DAIWA

Mitsubishi UFJ Lease & Finance

Hugle Electronics

TRL

Meico Electronic

University, Public Sector

Yokohama Nat. Univ.

Waseda Univ.

Nagano PGIRC.

Hokkaido Univ.

Kyushu Univ. Yamaguchi Univ.

Nagoya Univ.

Akita Ind. Tech. Center

Kanazawa Univ.

Micromachine Center

Tohoku Univ.

Osaka Univ. Kyoto Univ.

Nara Inst. Sci. Tech. Toyohashi Univ. Tech.

Sanmei

Okamoto Glass CKD Fujikin

PRE-TECH Litho Tech Japan

PMT

Shin-Etsu Polymer

Dainichi Shoji

JEM

Fujikoshi machinery

FUJI IMVAC

Komatsuseiki

Beamtron

Riseone

VIYIA

Koyo Thermo

Kashiyama

Horiba STEC

TAZMO

Sakaguchi E.H VOC

STK technology

Yonekura MFG

Aichi system

KKE TCK

Seinan Industries VTEX

Hakuto

YGK

Oriental motor

SPP technologies

SMC

Sanyou

Nitto Reinetsu

Hirose Electric Japan Science Eng.

Epiquest

Surpass Industry

Taiyo Nissan

Tateyama Machine Kanto Chemical

ULVAC

Wide Techno Xevios

Cotec Shinkouseiki

Equipment, Parts, materials

Fab-less Logic Research

RF device tech.

Innovation Platform

R&D: 10 times faster Investment: 1/1,000

Device makers, Minimal Fab Users

Murata Manufacturing Renesas Semi. Manufacturing

Hitachi Toshiba Omron NEC Yokogawa EL

Kyowa Electric Instruments

Hamamatsu Photonic JTEKT TOKAI RIKA TDK

TAMURA Panasonic Factory Solutions

Fab System Research Consortium, AIST

RIX

Haruki Seisakusho

Edwards Japan

YAZAKI

NEDIA

NIMS

NAGASE

FUJI Tech.

Tomoe Shokai

JFE Shoji Electronics

Materials

Parts, Units

Flextronics Keiso Kogyo

Equipment

August 21, 2016.

Docking Port

Minimal Foundry

NEITAS

Kanagawa Ind. Tech. Center

TEI Solutions

PMT

Eco-system in minimal fab 14

Minimal fab＠AIST

Gate Oxidation

Oxide Etcher

Resist Remover

Al wet etcher

Etcher

Developer Coater

Etcher Sputter

Maskless exposure

DRIE

Wafer Scanner

Packaging line

RCAstation

P Diffusion furnace

B Diffusion furnace

15

Ring Oscillator

PMOS

CMOS

Cantilever

MEMS core： cantilever

Hybrid

pMOSFET

nMOSFET

CMOSFET

CMOSFET

Minimal Device Fabrication History

2012

2013

2015

Ring Oscillator

Ring Oscillator

16

BGA package

Hybrid

Hybrid

Full Minimal

Full Minimal

Full Minimal

Hybrid

2016

Full Minimal

17 MOSFET by Full minimal processes

6mm

SiO2

Boron-doped P Boron-doped P

n-Si

DrainSource Gate60nm

8mm

Al 350nm

0 -2 -4 -6 -8 -10

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

-1.8

p -channel MOSFET

Vg = -3V

Vg = -4V

Vg = -5V

Vg = -6V

Vg = -2V D

rain

Curr

ent

I d [m

A]

Drain Voltage V d [V]

Vg = -1V, 0V

Wafer no. 17 L/W = 14/100micron, Tox = 62nm

Wafer no. 17 L/W = 14/100micron, Tox = 62nm

fabricated at Semicon Japan 2013.

Gate Source

Drain GND

7wafers, 35Tr. → Yeild100%

S. Khumpuang F. Imura, and S. Hara, "Analyses on Cleanroom-Free Performance and Transistor Manufacturing Cycle Time of Minimal Fab," IEEE Transactions on Semiconductor Manufacturing, 28(4), 551-556 (2015).

Interface states: Dit 7.7×1010states/cm2

Utilizing rate＠Semicon Japan 2013

・wafer transfer time to machine process chamber → 30s

● Avg. total process completed time : 10h25m ● Avg. process availability : 60%

Typical developing line ・Fabrication time 1 month ・process availability ～1%

Process Avalability

60%

Process Idle

38%

Transfer time Between machine

2 %

● No. of wafers : 7 ● 30 processes (excl.alignment mark forming)

Raw Time complete time

Process availability(%)

=

18

S. Khumpuang F. Imura, and S. Hara, "Analyses on Cleanroom-Free Performance and Transistor Manufacturing Cycle Time of Minimal Fab," IEEE Transactions on Semiconductor Manufacturing, 28(4), 551-556 (2015).

2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023

19

June 3, 2017.

FY

MEMS Core Structure

Discrete CMOS Device and Process

LSI Process

LSI trial Fab (160 tools)

LSI production Fab

Specific Tools Prototype

MEMS Process

Discrete Process Discrete Fab

MEMS Fab

Core Tools Prototype Advancing Tool Performance High Throughput,

Low Cost

Commercialize Core Tools

Commercialize Specific Tools

hybrid

MEMS

Discrete

LSI

Analog Process Analog Fab

Industria

lize

Min

imal T

ools

87%

Energ

y

Savin

g

Sm

all P

roductio

n F

ab

Industria

lize F

ab

for S

imple

devic

es

99%

Energ

y

Savin

g

Rea

lize

“M

y Io

T d

evic

e”

Susta

inable

Industry

1st : Tool Dev. 2nd : Fundamental Fab 3rd : LSI Fab

hybrid

CMOSFET

full minimal full minimal

nMOSFET pMOSFET

MEMS core： cantilever

Roadmap for minimal fab

Minimal Tools

Device & Fab

・Small Business, Small Factory（Minimal Fab） ・High-variation low-volume Production ・Contribute to local area, distribute the risk, ICT・Networking ・Smart business, customer-oriented, ・Less Valley of Death

・Monolithic Fab（Mega Fab） ・Low-variation large-volume production ・Centralized business group, Intensive risk ・Old tradition business, maker-oriented, ・Deep Valley of Death → Paradigm Shifts to 21st century

20th Century, Industrial Engines:

21st Century, Industrial Engines:

Industrie 4.0 Advanced Manufacturing (3D printer)

20 Industrial aspect of minimal fab

Minimal Fab is a good model.