© 2001 ® Embedded Processor Solutions 2

1 © 2001 ®

Embedded Processor Solutions

2 © 2001 ®

20002000

Altera® SOPC Innovation

19991999

High-Density,Feature-Rich SOPC Delivery Vehicle

Methodology forSOPC Development

Building Blocks& Design Reuse inSOPC Applications

Processor Core& CompilerLicensees

Wide-OpenRoyalty-FreeBusiness Model

Embedded ProcessorSolutions

3 © 2001 ®

Altera® SOPC Innovation

20012001Complete SOPC Design Environment

ACEX TM

1K

APEX TM 20K/E/C

FLEX TM

10K

GNUPro Development Tools

Expansive Device Selection

uCLinux

EXCALIBUR TM

XAEXCALIBUR TM XM

4 © 2001 ®

ACEX™ EP1K100

APEX EP20K200E

Excalibur XA10

Low-CostEmbedded Processor

High-PerformanceCustom DSP

Multi-ProcessorSystem

75K Gates Available 150K Gates

Available

500K GatesAvailable

DSPDSP

ES

BE

SB

ES

BE

SB

ES

BE

SB

ES

BE

SB

ES

BE

SB

ES

BE

SB

ES

BE

SB

ES

BE

SB

ES

BE

SB

ES

BE

SB

ES

BE

SB

ES

BE

SB

Excalibur Nios Flexibility & Scalability

Excalibur ARM 922T + Memory

5 © 2001 ®

Nios Soft CoreEmbedded Processor

6 © 2001 ®

Timer

IRQ

PB

M

CPU

UART

Your DesignHere

FLASH

SRAM

SerialPort

Excalibur Nios Embedded Processor Core

Configurable Soft Core Processor 32-Bit Pipelined RISC Architecture

– 16-Bit Instructions

– Most Instructions Take 1 Clock

Large Internal Register File Configurable Data Path

– 16-bit (1100 LEs)

– 32-bit (1700 LEs)

Dynamic Bus Sizing 30 to 80 MIPS Performance

Altera PLD

Volume Price Point

$5for 50 MIPs

12% ofEP20K200E

7 © 2001 ®

Nios RISC Processor Block Diagram

Standard RISC Components Fully-Synchronous Interface

8 © 2001 ®

Windowed Register File

Common Technique Used by High-Performance CPUs– Provides Fast Subroutine Calls

Up to 512 General-Purpose Registers

Movable Window With Access to 32 Registers– 24 Register Window (Movable)

– 8 Global Registers (Fixed)

Automatically Used by C Compiler

9 © 2001 ®

Bit Shift Speed

Provides Multiple Bit Shift in a Single Clock Cycle– Increments of up to 3, 5, 7, 15, or 31 Bits Per Clock

Example:– Bit Shift Speed Set to 7:

i << 9; /* Shift Left by 9 Bits */

– Executes in 2 Clocks

0

Clock 1 (Shift 7 bits)

Clock 2 (Shift 2 bits)

10

© 2001 ®

Multiplication Options Software

– Uses GNU Math Library for Multiply Operations MSTEP

– Hardware Multiplier - Option 1– One-Bit Per Clock Multiply– Improvement of ~ 4X over Software Multiplication Routines

MUL– Hardware Multiplier - Option 2– 16 x 16 32 in 2 Clocks

Multiplier

None (Software)

MSTEP

MUL

Clock Cycles16x16>32

Clock Cycles32x32>32

Additional LogicElements Used

80

18

2

0

+200

+400

250

80

16

11

© 2001 ®

Development Tool Flow

12

© 2001 ®

Processor Design

(Verilog / VHDL)

Simulation Test Bench

C Header files

Custom Library

Boot monitor

Synthesis Place & Route

Cygnus/Red HatGNUPro

AlteraPLD

JTAGSerial

Ethernet

User Design

Purchased IP

ExecutableCode

HardwareConfiguration

File

Configure Processor

Select Peripherals

Generate

Hardware Software

Download& Debug

Nios System Builder Software

User Code

S/W Libraries

RTOS

Peripheral Library

13

© 2001 ®

Nios System BuilderNios System Builder

CPU

Nios

HDL

Peripheral

Peripheral

HDL

Nios System Builder Software

Generate:• Hardware - HDL Files• Software - Custom Library• Simulation - Test Bench

Peripheral

Routine

Custom

Library

14

© 2001 ®

ExcaliburDevelopment KitFeaturing Nios

$995

Excalibur Development Kit Altera 32-Bit RISC CPU Peripherals

– UART– Timer– Serial Peripheral I/F (SPI)– Parallel I/O (PIO)– Memory I/F– Generic Port I/F– On-Chip Bus

Development Board – Reference Designs

Development Tools– Quartus Excalibur Edition– LeonardoSpectrum– FPGA Express– Cygnus GNUPro

15

© 2001 ®

Software Generation GNUPro C Development Kit

– Compiler

– Assembler

– Linker

– Debugger

– Nios Software Libraries

Nios Development Utilities– Compile, Assemble, Link

– Download to SRAM and Flash

– Disassemble Executable Code

– Prepare Executable for Boot ROM

Example Code (C & Assembly)– Peripheral I/O

– Interrupt Service Routines

Cygnus GNUPro

Toolkit

Cygnus GNUPro

Toolkit

16

© 2001 ®

System Reference Design

17

© 2001 ®

Nios Development Board

18

© 2001 ®

Reference Design Block Diagram

19

© 2001 ®

Nios Software Development Utilities

BASH: Standard UNIX-like Command Line Shell

Nios Development Utilities– nios-build: Compile, Assemble & Link– nios-run: Download Executable & Run– srec2flash: Create Flash-bootable Code

Generic UNIX Utilities Such As:– Make: make– Concatenate: cat

20

© 2001 ®

Creating an SOPC Hardware Design

21

© 2001 ®

Run Quartus

Default Design: nios_reference32

22

© 2001 ®

Adding a Nios Processor

Double-Click the Schematic Choose: MegaWizard Plug-In Manager... Create New Custom Megafunction Variation

23

© 2001 ®

Configure a Nios Processor

File Type: Verilog HDL Output File Name: nios

24

© 2001 ®

Processor Architecture– ALU, Registers, Data & Address Bus

• 16-Bit• 32-Bit


25

© 2001 ®

Address Bus Width


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© 2001 ®

General-Purpose Register File Size– 128, 256, or 512 Registers– Uses Embedded System Blocks (ESB)

Internal Shifter Speed– Maximum Number of Bits

Shifted in a Single Clock


Reg Nios-32 Nios-16128 4 2256 8 4512 16 8

ESB Usage

27

© 2001 ®

Multiplication Options– None

• Software Math Library• No Additional Logic

– MSTEP • 1-bit per Clock• Adds ~200 LEs

– MUL • 16 x 16 32 in 2 Clocks• Adds ~400 LEs


28

© 2001 ®

Nios System Builder

Displays System Configuration Add Peripheral Content

29

© 2001 ®

UART Peripheral

30

© 2001 ®

Peripheral Name: uart1 Type of Peripheral:

Inside Nios System Module

UART (RS-232 serial port)

Adding a UART Peripheral

31

© 2001 ®

Timer Peripheral

32

© 2001 ®

Timer Peripheral

32-Bit Interval Timer – Counts Down to 0 from Preset Value – 16-Bit Peripheral (Compatible with Nios-16)– Two 16-Bit Registers (High / Low Half-Word)

Polled Operation– Periodically Read Coherent “Snapshot” of Counter Value

Interrupt Operation– Generate a Single (Mask-able) Interrupt on Time Out

Uses Single Master Clock Input (Clk)

33

© 2001 ®

Parallel I/O (PIO) Peripheral

34

© 2001 ®

PIO Peripheral 1 to 32-bit Parallel I/O Port

– Input Only– Output Only– Bi-directional Port

• On-chip: Separate Ports for Input & Output• Off-chip: Tri-State Control

Edge Detection on Inputs Interrupt Generation

– Mask-able– IRQ Source

• Input Level• Edge Detection Register

35

© 2001 ®

On-Chip Memory

36

© 2001 ®

On-Chip Memory

Configure as ROM or RAM Uses Embedded System Blocks (ESB) Can Be Initialized With Boot Code

– GERMS Monitor Code Included (Source and Executable)– Boot Code Development Utility (srec2mif)

• Converts Compiler Output (srec) to APEX ROM Format (mif)

37

© 2001 ®

Serial Peripheral Interface (SPI)

38

© 2001 ®

SPI Port Full Duplex, Synchronous Serial Interface

– Interface to:

• A/D, D/A

• Microcontrollers

• Serial EPROM

3-Wire Serial Communications Bus With Slave Select– Master Out Slave In - MOSI

– Master In Slave Out - MISO

– SPI Clock - SCLK

– Slave Select - SS_n (Optional)

Master or Slave Operation Supports Up to 16 Slave Devices Programmable Word Size (1 to 16 bits) Programmable Delay Slot (Enable-to-Active)

39

© 2001 ®

Ethernet Interface

40

© 2001 ®

Ethernet Port

10baseT External MAC/Phy Device– ISA Bus Interface– Supports All Programmable Logic Device Families

Includes TCP/IP Stack– Library of C Routines

Nios

CPU

Ava

lon

Bu

s

ISA

BusNios System

Module

External

MAC/Phy

I/O

I/O

I/O

I/O

Altera PLD

41

© 2001 ®

User-Defined Interface

42

© 2001 ®

User-Defined Interface Interface to Other Peripherals

– On-Chip & Off-Chip

Configures Busses and Timing Adds Port Signals to Design

Nios

CPU

Ava

lon

Bu

s

User

I/FNios System

Module

External

Device

I/O

I/O

I/O

I/O

Altera PLD

43

© 2001 ®

External Memory Interface

44

© 2001 ®

Adding a Memory Interface: SRAM

Peripheral Name: sram Type of Peripheral:

Outside Nios System Module

32-Bit SRAM (256Kbytes In two IDT71V016 chips)

45

© 2001 ®

System Configuration

46

© 2001 ®

System Configuration Main Program Memory

– Code Execution

Main Data Memory– Variables & stack

Host Communication– Monitor STDIO

Debug Communication– GDB Port

Boot ID Message– Monitor Prints at Start-up

47

© 2001 ®

System Configuration Boot Device

– Optional Offset

Interrupt Vector Table– Optional Offset

Highest Performance Bus– Fastest Access

Synthesis Target Family– APEX– FLEX 10K– ACEX– Mercury– Excalibur ARM– Excalibur MIPS

48

© 2001 ®

Generate the Design

Software Development Kit (SDK)– Header File

• Address Map

• Peripheral Structures

– Custom Library

– Monitor Code

Hardware Design– HDL Source Files

Synthesis– EDIF Netlist With HDL “Wrapper”

– Test Bench

49

© 2001 ®

Configuring The Development Board

50

© 2001 ®

User

APEX Image

User User SoftwareSoftware

1Mb Flash

APEX

ROMData

Co

ntro

l

Address

7064

Nios Hardware Configuration Process

Single Image Flash– APEX Hardware Configuration

• Factory Image

• User Image

– User Software

APEX Configured from Flash – EPM7064 Configures APEX from

Flash

– During Configuration, EPM7064:

• Loads “User” APEX Image

• If Failure, Loads “Factory” APEX Image

Factory Factory APEX ImageAPEX Image

51

© 2001 ®

SRAM

256Kb

DataA

dd

ress

1Mb Flash

APEX

ROM

Nios Processor Boot Process

Boots from “Reset” Address – Default Reset Address 0x0000

• On-Chip ROM• 512 16-Bit Instructions• Contains GERMS Monitor

During Boot– Monitor Checks User Software

Space• Runs Code Found at Address

0x140000

Factory Factory APEX ImageAPEX Image

User

APEX Image

User User SoftwareSoftware

140000

52

© 2001 ®

Software Development with GNUPro for Nios

53

© 2001 ®

Monitor Program Runs from On-Chip ROM Communicates to Host Via Serial Port (or Ethernet) Basic Development Facilities:

– Download Code– Burn Flash– Examine/Modify Memory– Run Programs

Serial

GERMS Monitor

54

© 2001 ®

Nios SDK & HDKFiles and Folders

55

© 2001 ®

Nios SDK Contents

GNUPro Toolkit for Nios: <drive:>\cygwinCompiler, linker, etc.

Nios tools: \usr\Altera\Excalibur\Nios-SDK\bin\nios-build

nios-run

nios-elf-gdb

GNUPro Documentation: \cygwin\html\…– Extensive Documentation for: general, compiler, debug, libraries, and

utilities

– html format

56

© 2001 ®

GNU Debugger(GDB)

57

© 2001 ®

GNU Debugger

Code download Run control Break points Watch points Memory examination

and modification

58

© 2001 ®

GDB Operation

DebugMonitor

Serial

Connection

Debugger Runs on Host– PC or UNIX Platform

Debug Monitor Runs on Target– Interprets Commands From Host

– Controls the Target Application

Serial Link to Between Host and Target– RS-232 and Ethernet

Debugger

59

© 2001 ®

Nios Development KitAdd-On Packages

60

© 2001 ®

Ethernet Development Kit Supports Wide Range of Applications

– Factory Floor Automation– Basic Ethernet Connectivity– Internet Upgradeable Hardware

Supports All PLD Families Development Board

– External 10Mbyte MAC/Phy– Support for 2 Ports

Software– TCP/IP Stack

Reference Design– Hardware (Quartus™ Development

Tool Project) – Software (Web Server Application)

Available July 2001 Price $495

61

© 2001 ®

Linux Development Kit

Open-Source uCLinux Operating System

Development Kit Contents– uCLinux Source Code

– Host Daughter Board

– SDRAM Controller Core

– SDRAM / Flash Memory Module

– Ethernet Development Kit

– Reference Design

• Hardware (Quartus Project)

• Software (Web Server Application)

Available July 2001

Price $2,495

Documents

© 2001 ® Embedded Processor Solutions 2