© 2003 Xilinx, Inc. All Rights Reserved Multi-rate Systems

© 2003 Xilinx, Inc. All Rights Reserved

Multi-rate Systems

Multi-rate Systems - 7 - 2 For Academic Use Only

Objectives

After completing this module, you will be able to:

• Define multi-channel and multi-rate systems• Identify sample rate changing blocks• Describe Simulink propagation rules• Explain the hardware realization for rate changing blocks


Outline

• Multi-rate Systems• Sample Rate Changing Blocks• Simulink Propagation Rules• Hardware• Simulink Tips and Tricks

– Solvers


BPFLPF

LPF

LPF

LPFEqualization Demodulation

BPFLPF

LPF

LPF


R.F.

40-150 MHz 5-40 MHz 500 kHz - 10 MHzSample Rates

Multi-rate Systems

• Looking at a typical wireless base-station receiver application, we can see that filters can form a major part of the DSP functionality

• Because the object of such a system is to down convert from high frequencies to lower frequencies, however, this is also coupled with many different sample rates…


BPFLPF

LPF

LPF


BPFLPF

LPF

LPF


R.F.

40-150 MHz 5-40 MHz 500 kHz - 10 MHzSample Rates

Multi-rate Systems

• How are sample rate changes performed in System Generator? • What tools are available to build multi-rate systems and what are the

difficulties and problems involved?


Sample Times…Again?

• Every SysGen signal must be sampled; that is, transitions occur at equidistant discrete points in time called sample times– Set explicitly

• Gateway in• Blocks w/o inputs (note: constants are idiosyncratic)

– Derived from input sample times• Inherited using Simulink idiom (mask sample time = -1)

– System sample period controlled by System Generator token– What if the sample rate needs to be changed?


Outline


– Solvers


Sample RateChanging Blocks

• Up sample can either replicate the same number M-1 times or insert M-1 zeros to achieve the higher sampling rate

• Down sample “throws away” M-1 samples to achieve lower sampling rate

Up Sample by 3 0 0

Down Sample by 3 0 0


Sample RateChanging Blocks

• Parallel to Serial: Output rate will be M times faster, where M is the width of the input parallel data

• Serial to Parallel: Output rate will be M times slower, where M is the width of the output parallel data

• FIR: Can be used as a polyphase interpolation or decimation FIR


Too Many Rates!

• As designs grow, there are tools available to track and manage all the different sampling rates– Use Sample Time block from Xilinx BlocksetIndex or Tools libraries– Use the sample time colors (Format Sample Time Colors)– Use Simulink display block to view the output of the sample block


Sample Period (GCD)

SamplePeriod

Gateway InBlock Output Down Sample Up Sample Up Sample1

0.1 1.3 0.26 0.13

10/100 130/100 26/100 13/100

Simulink System Period: 1/100

Who Runs the Show?

• The System Generator token still controls simulations. The “Simulink System Period” must be set correctly for simulation to work. The System Period is the global sample period that all other sample periods can be derived from. Therefore, every sample period in a design must be a multiple of the System period


Who Runs the Show?

“Simulink System Period” MUST be set correctly for simulation to work

• If incorrect, the tools will calculate the value for you and update the value


44.1 kHz 48 kHz441 kHz

CDformat

DATformat

7056 kHz

SamplePeriod (GCD)

SamplePeriod

Gateway InBlock antiAliasFIR antiAliasFIR1 Gateway Out

Simulink System Sample Period:

Exercise: Audio Application

• Analyze the following sampling rate change system that is commonly found in audio broadcasting studios. Determine the Simulink System Sample period:


Outline


– Solvers


Simulink Propagation Rules

• Simulink’s data type and sample time inheritance rules make it possible to tailor design without having to update every block

• Simulink resolves all data types and sample times during initialization by propagating known values– As mentioned, all blocks inherit their input sample rate– Feedback loops cause problems for Simulink’s propagation algorithms– Must set at least one explicit sample time in every feedback loop– SysGen idiom: “explicit inherited” sample period tells Simulink to inherit first

encountered sample time


Propagation in Loops

Note: The addsub block sets an explicit sample period to inherit the input sample period coming from the constant multiplier. This placatesSimulink for both the simple feedback loop in this subsystem, and also the longer feedback loop that goes through this subsystem from its parent


Propagation in Loops

Q. What would happen if a full precision adder is used in this example?


Outline


– Solvers


What About the Hardware?

• System Generator implements multi-rate systems using a synchronous clock enable scheme

• Every block gets the same system clock signal, the fastest clock, but is enabled at its relative sample rate defined in Simulink



• How this works: – In hardware, think of the sample period as the “number clock pulses

between block execution” • E.g., a sample period of 1 means that particular block will be executed on every

clk cycle. Hence, the system clock is assumed to have a sample period of “1.” A sample period of 5 means that particular block will be executed on every fifth clock cycle

– SysGen examines every sample time in the entire system, and computes their greatest common divisor (GCD). The system clock corresponds to the GCD (sample period of ‘1’), and each sample period is then normalized to a multiple of this value

– SysGen generates circuitry (xlclockdriver.vhd) that periodically asserts a CE (for a single clock cycle) for every required multiple. The main circuitry in the xlclockdriver.vhd is a counter and some comparator logic


0101=5

System Clock

Block2 CE2

Block1 CE1

Block1 DOUT

Block3 CE6

Block2 DOUT

Block3 DOUT 0101 = +5 1011 = -5 0000 = 0

0110=6 1111 =-10111=7 0111=7 0000=0 0001=10111=7 1110=-2 0111=7


• This concept is illustrated below in a timing diagram. These Clock enable pulses are referred to as the “Normalized Sample Times”


0101=5

System Clock

Block2 CE2

Block1 CE1

Block1 DOUT

Block3 CE6

Block2 DOUT

Block3 DOUT 0101 = +5 1011 = -5 0000 = 0

0110=6 1111 =-10111=7 0111=7 0000=0 0001=10111=7 1110=-2 0111=7


• This clocking scheme means the implementation tools need to be informed how fast each flip-flop really has to be clocked (i.e., multi-cycle path constraints are a must). Fortunately, in SysGen, the code generator does this (see XCF file)


Some Hardware Specifics

• To continue with our theme of ‘looking under the hood’ it is important to examine the hardware implementation and potential traps associated with using multi-rate systems

• We will examine the:– Up Sampler– Down Sampler


L[ ]x n

Up Sampler

• Up sampler becomes a “short” (a wire) if samples are copied. There is no cost in hardware, simply a simulation construct

• Otherwise, a MUX switches between 0 and the data input


Up Sampler

L[ ]x n

System Clock

SRC CE3

DEST CE

DIN

OUTPUT

5 7 24 11 6

7 0 0 4 0 0 0 0 0 0 0 011 6 20


• Latency > 0 has two options– Sample Last Value of Frame is most efficient (a delay)

– Sample First Value (costs one additional register)

Down Sampler


• Latency > 0 has two options– Sample Last Value of Frame is most efficient (a delay)

– Sample First Value (costs one additional register)

M[ ]x n [ ] [ ],y n x nM n Z

System Clock

DEST CE

DIN

DOUT 5 0 11 8 0

7 2 1 4 7 8 3 0 3 111 6 20

System Clock

DEST CE

DIN

DOUT 5 2 27 3 1

7 2 1 4 7 8 3 0 1 311 6 20

Down Sampler


Down Sampler

• Latency zero has a shutter, but has a registered enable• Careful of the combinatorial feedthrough path on the data line through

the output MUX. This is a problem with zero-latency down samplers


Useful Blocks

• Use the CLK probe and the CE Probe from the Xilinx Blockset to view their respective signals

• CE Probe produces Boolean output that can be used for control logic


Hint: Refer to the up/down sampler slides to help determine their respective sample times

Block Output SampleFrequency

NormalizedSample Time

InReg

Up Sampler

AntiAliasFIR

Down Sampler

OutReg

Exercise: Audio Application

• Analyze the following sampling rate change system that is commonly found in audio broadcasting studios. Fill in the sampling rates in the table below:

DATformat

DABformat

32 kHz96 kHz

48 kHz


Outline


– Solvers


Typical SysGen settings

Solvers

• Simulink works by establishing a dialog between the system (the block diagram) and the solver (i.e., simulator)

• The solver computes block outputs, then:– Updates discrete states (exact)– Decides on the next time step

• Simulink carries necessary information:– From system to solver: parameters, equations– From solver to system: computed states, inputs,

time• Auto fixed step size determines the required

step rate from the sample periods of your model

Documents

© 2003 Xilinx, Inc. All Rights Reserved Multi-rate Systems