2013/3/4

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TEG1.11.2TEGTEG1.31.41.5

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1.1SPICE3BSIMBinningBSIM3v3BSIM4RFRC

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1.2TEGTEG1.2.1DC TEG1.2.2DC TEG1.2.3TEG1.2.4TEG

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1.2.1DC TEG1: 4: DUTDUTLRDB ONOFFLRDB

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1.2.2DC TEGAND33VDFVDSVDLVGFVGSVGLVSFVSSVBFVBSUNIT_CELL

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1.2.3TEGJames C. Chen, Bruce W. McGaughy, Dennis Sylvester, and Chenming HuAn On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) TechniqueIEDM 1996 OpenShortPch TrNch Tr0.01fF10aF

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1.2.3TEG1 CIEF CBCMMOSFET VCCPADGND Yao-Wen Chang, Hsing-Wen Chang, Tao-Cheng Lu, Ya-Chin King, Wenchi Ting, Yen-Hui Joseph Ku, and Chih-Yuan LuCharge-Based Capacitance Measurement for Bias-Dependent Capacitance IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 5, MAY 2006

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1.2.3TEG4 //MOSFET

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1.2.4TEG CBCM

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1.31.3.1 TEG1.3.2 1.3.3 RDRS RD+RS1.3.4 WDLD1.3.5 VTO1.3.6 UO1.3.7 THETA1.3.8 VMAX

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1.3.1 TEG

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1.3.2

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1.3.3 RoutVDS

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1.3.3 I-VVIR-VRI-VR-VVIRVIR

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RD+RSInfluence of RDS in VTHWith series resistanceIntrinsic device

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1.3.4 IDSW

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1.3.5 VTO

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1.3.6 UO

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1.3.7 THETAVGS1VGSVBS=0VVDS=0.05V,0.1V2VGS1VGS2

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1.3.8 VMAX

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1.4 1.4.1 1.4.2 LDD LEVEL3 LDD1.4.3 1mRout1.4.4 Cgb-Vgb Cgb-Vgb

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1.4.1

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1.4.2 LDDIds-VgsIds-Vds

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LEVEL3LDD

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1.4.3

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1mRoutRout1m

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1.4.4 Cgb-Vgb

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Cgb-VgbRegion AB:gate oxide capacitance +parallel-plate overlap component +the fringing components Region CD:parallel-plate overlap component +the fringing componentsRegion DE:inversion capacitace +the fringing componentsA Simple Model for the Overlap Capacitance of a VLSI MOS Device

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1.5DC TEGTEGDC TEGTEG

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