--HDL

()Verilog HDL, VerilogVerilogVerilog testbenchtaskfunction(primitive)Verilog

()Cadence Verilog, (source libraries)Verilog-XLNC Verilog Tcl(GUI)(annotation)NC VerilogNC Verilog(cycle)

() (STA) design analyzer HDLVerilog HDLVerilog HDL Designware (1)

() Constraint FSM (2)

()(Silicon Ensemble)

54 (18)27Verilog (5) Synthesis (3)Place &Route (1)24Verilog (5)Synthesis (2)Place &Route (1)3

Cadence Verilog Language and SimulationVerilog-XL Simulation with SynthesisEnvisia Ambit SynthesisVerilog Thomas &Moorby2001.8

Verilog HDLVerilogVerilog(levels of abstraction)Verilog

(terms and definitions)HDLHDLASIC(Application Specific Integrated Circuit)ASIC Vender RTL(Register Transfer Level)TclTool command Language,

HDLHDLVerilogVHDLVerilogCCVHDLADAVHDLIEEE 1706-1985

HDLHDLHDLHDL

VerilogVerilog HDL1983GDA(GateWay Design Automation)Phil MoorbyPhi MoorbyVerilog-XLCadence

1984~1985MoorbyVerilog-XL

1986MoorbyXL

1990CadenceGDA

1991CadenceVerilogOVI(Open Verilog International)Verilog HDL

1995Verilog HDLIEEEIEEE1364

VerilogVerilogASICFPGARTLASICFPGA

(Levels of Abstraction)VerilogVerilog-/

RTL/-Verilog

/-Verilog

/-

(Levels of Abstraction)-/

RTL/-Verilog

/-Verilog

/-

/

(Levels of Abstraction)Verilog

RTL/

/(primitive)(component)RTL

(Levels of Abstraction)RTL()

Verilog

RTLMUXabselsel0abmodule muxtwo (out, a, b, sel); input a, b, sel; output out; reg out;always @( sel or a or b) if (! sel) out = a; else out = b;endmoduleRTLXZ@, while,wait,if, caseTestbench(test fixture)testbenchRTLRTLVerilog

VerilogASICFPGAVerilog(primitive)andUDP(User Defined Privitives)(glue)MUXVerilog()module twomux (out, a, b, sl); input a, b, sl; output out; not u1 (nsl, sl ); and #1 u2 (sela, a, nsl); and #1 u3 (selb, b, sl); or #2 u4 (out, sela, selb);endmodule!

VerilogRTLtestfixture

Verilog ?Verilog?Verilog RTL?Verilog?VerilogVerilog OVIIEEE1394RTLVerilog

CadenceVerilog-XLNC Verilog

(SPICE)(Verilog-XLNC Verilog)(cycle)

2~10%evaluate when necessary() (1, 0)

(time wheel)00timeslice

Cadence VerilogVerilog-XLNC VerilogVerilog HDL

Verilog-XLNC VerilogIEEE 1364 Verilog

Verilog(compiler directive)compilationelaborationNetZX0initialalways0

Versus Verilog-XLVerilog(compiler directive)() () Verilog-XLVerilog-XLVerilog HDL

Versus Verilog-XLVerilog HDLVerilog HDL

Verilog-XLTurboXLSwitch-XL

NC Verilog-NC VerilogVerilogncvlogVerilog(compile directive)ncelab(element)ncsim()TclNC VerilogTcl

NC VerilogNC VerilogVerilog-XLNC Verilog(kernel)NC VerilogTclNC Verilog

VerilogVerilog-XLNC VerilogVerilogIEEE1364-1995 VerilogOVI 2.0 VerilogAttributes: Verilogoutputinout(argument)OVI2.0outputinout

Verilog-XLVerilog-XL: verilog [verilog-xl_options] design_filesoption verilog mux.v test.v c verilog c mux.v test.v-f verilog f run.f run.f

Verilog-XLverilog.logmux.vtest.v-c

NC VerilogNC Verilog(ncvlog, ncelab, ncsim)ncverilogNC Verilog: ncverilog [ncverilog_options] verilog-xl_argumentsExamples:ncverilog mux.v test.vncverilog c mux.v test.vncverilog f run.f run.f

NC Verilogncverilog.logmux.vtest.v-c

NC Verilog+gui-q-selaborateSDFelaborateNC VerilogSDFncverilog +access + argument ncverilog f run.f + access+RWC+linedebug ncverilog -f run.f +linedebug+noupdate

NC Verilog +access+access++access-argsRWC+linedebugRWC

+noupdate

+gui-q-s0

SignalScan> signalscan & signalscan &

SignalScanTitle BarSignalScanSignalScanMenu BarTool Barcopy, cut, paste, undo, delete, zoom, create marker, expand buses, launch the Design BrowersignalscanSignalScanDesign BrowerGroups PaneWaveforms RegionNames PanepanemarkerTime-Display Region

SHMSHMSHMinitialbegin $shm_open(lab.shm); $shm_probe();end

$shm_open(waves.shm);$shm_probe();$shm_close;$shm_save;

SHM (Simulation History ManagerSHM)(probe) $shm_SHM$shm_probe$shm_probe (0)

$shm_probe $shm_probescope/node $shm_probe( ); (scope) $shm_probe(A); $shm_probe(alu, adder); aluadder $shm_probe(S, top.alu, AC); (1): (2)top.alu

$shm_probe $shm_probe $shm_probe(scope0, node0, scope1, node1, ...); nodescope(

scope(scope)node

nodeASCASAC((port))(),(),

Affirma NC VHDLEnvisia AmbitVerilog-XL, SignalScan-TXAffirma equivalence checkerRTLAffirma model checkerVerilogVHDLAffirma model packagerVerilog, VHDLCAffirma Advanced Analysis Environment includes CoverScan, a code profiler, and HAL, a lint checkerCadence Verilog

Verilog-XLNC Verilog

ttNC VerilogIEEE 1364 Verilog LRMNC VerilogIEEE 1364 LRM(array of instances)

VerilogVerilog

moduleICASICCPUALUmoduleSN74LS74DFFALUendmodulemodule()modulemodule

(module ports)DFFinput, outputinout(pin)

(module instances)module DFF (d, clk, clr, q, qb); ....endmodule

module REG4( d, clk, clr, q, qb); output [3: 0] q, qb; input [3: 0] d; input clk, clr; DFF d0 (d[ 0], clk, clr, q[ 0], qb[ 0]); DFF d1 (d[ 1], clk, clr, q[ 1], qb[ 1]); DFF d2 (d[ 2], clk, clr, q[ 2], qb[ 2]); DFF d3 (d[ 3], clk, clr, q[ 3], qb[ 3]);endmodule

REG4DFF(d0, d1, d2, d3)(module instances)

test fixtureDUT(test fixture)Test fixtureDUTTest fixtureDUT

DUT (device under test) a, b, selout/module MUX2_1 (out, a, b, sel); // Port declarations output out; input a, b, sel; wire out, a, b, sel; wire sel_, a1, b1; // The netlist not (sel_, sel); and (a1, a, sel_); and (b1, b, sel); or (out, a1, b1);endmodule Verilogmoduleendmodule

Test Fixture templatemodule testfixture; // Data type declaration

// Instantiate modules

// Apply stimulus

// Display results

endmoduletestfixture

Test Fixture module testfixture; // Data type declaration

// Instantiate modules MUX2_1 mux (out, a, b, sel); // Apply stimulus

// Display results

endmodule

MUX

Test Fixture (procedural block)0 initial always

Test Fixture (procedural block)test fixture0

Test fixture a, b, selregreg#5 5$finishmodule testfixture; // Data type declaration reg a, b, sel; wire out; // MUX instance MUX2_1 mux (out, a, b, sel); // Apply stimulus initial begin a = 0; b = 1; sel = 0; #5 b = 0; #5 b = 1; sel = 1; #5 a = 1; #5 $finish; end // Display resultsendmoduleTime Values a b sel0 0 1 05 0 0 010 0 1 115 1 1 1

Test Fixture $time $monitor $monitor ([format_specifiers,] ); $monitor($time, o, in1, in2); $monitor($time, , out, , a, , b, , sel); $monitor($time, %b %h %d %o, sig1, sig2, sig3, sig4);Verilog

Test Fixture $time64$monitor $time$monitor

Test Fixturemodule testfixture; // Data type declaration reg a, b, sel; wire out; // MUX instance MUX2_1 mux (out, a, b, sel); // Apply stimulus initial begin a = 0; b = 1; sel = 0; #5 b = 0; #5 b = 1; sel = 1; #5 a = 1; #5 $finish; end// Display results initial $monitor($time,," out=%b a=%b b=%b sel=%b", out, a, b, sel);endmodule0 out= 0 a= 0 b= 1 sel= 05 out= 0 a= 0 b= 0 sel= 010 out= 1 a= 0 b= 1 sel= 115 out= 1 a= 1 b= 1 sel= 1

`timescale 1ns/1ns module testfixture; // Data type declaration reg a, b, sel; wire out; // MUX instance MUX2_1 mux (out, a, b, sel); // Apply stimulus initial begin a = 0; b = 1; sel = 0; #5.7 b = 0; #5 b = 1; sel = 1; #5 a = 1; #5 $finish; end// Display results initial $monitor($time,," out=%b a=%b b=%b sel=%b", out, a, b, sel);endmodule0 out= 0 a= 0 b= 1 sel= 06 out= 0 a= 0 b= 0 sel= 011 out= 1 a= 0 b= 1 sel= 116 out= 1 a= 1 b= 1 sel= 1

VCDVerilogVCD(Value Change Dump)VCD

$dumpfile("file. dump"); $dumpvars(); $dumpflush;$dumpoff; $dumpon; $dumplimit(); $dumpall; VCDVCDVCD(

VCD$dump*$dumpvars $dumpvars$dumpfileVCD(0)VCD$dumpallVCD

$dumpvars$dumpvars[(< levels>, *)];

scope$dumpvars$dumpvars initial begin $dumpfile (verilog. dump); $dumpvars (0, testfixture.a); #1 $dumpvars (0, testfixture.b); end$dumpvars

$dumpvars$dumpvars; // Dump$dumpvars (1, top); // Dump top$dumpvars (2, top. u1); // Dumptop. u1$dumpvars (0, top. u2, top. u1. u13. q); // Dump top.u2top. u1. u13. q$dumpvars (3, top. u2, top. u1); // Dump top. u1top. u2

test fixture$monitor: initial begin $dumpfile (verilog. dump); $dumpvars (0, testfixture); end$dumpvars(levels)(scope)

Verilogmoduletest fixturemodulemodulemodulemoduleDUTtestbenchtest fixturetestbenchinitialalwaysinitialalways$monitor

Verilog(Lexical convention)Verilog(tokens)timescale

tabsIdentifier: Verilog()Lexical: grammar)(syntax)LSB(Lease significant bit)MSB(Most significant bit)

module MUX2_1 (out, a, b, sel); // Port declarations output out; input sel, // control input b, /* data inputs */ a;/* The netlist logic selects input a when sel = 0 and it selects b when sel = 1.*/ not (sel_, sel); and (a1, a, sel_), (b1, b, sel); // What does this line do? or (out, a1, b1);endmoduleVerilog/* */

size (bit)32 base2(b)8(o)10(d)16(h)10 valueXZ Verilog(literals)

12 unsized decimal (zero-extended to 32 bits)'H83a unsized hexadecimal (zero- extended to 32 bits)8'b1100_ 0001 8-bit binary64'hff01 64-bit hexadecimal (zero- extended to 64 bits)9'O17 9-bit octal32'bz01x Z-extended to 32 bits3b1010_ 1101 3-bit number, truncated to 3b1016.3 decimal notation32e- 4 scientific notation for 0.00324.1E3 scientific notation for 4100

_(size)32(base)(16)value 2b11012b01 10

string)C(escape)\t \nC(%b) This is a normal string This string has a \t tab and ends with a new line\n This string formats a value: val = %bVerilogVerilog

string) %0d0

%h%o%d%b%c%s%v%m%thexoctdecbinACSIIstringstrengthmoduletime

\t\n\\\\tabASCII representation of above

(identifiers)Verilog(a-z, A-Z)( _ )( $ )( _ )1023selSEL

module MUX2_1 (out, a, b, sel);output out;input a, b, sel; not not1 (sel_, sel); and and1 (a1, a, sel_); and and2 (b1, b, sel); or or1 (out, a1, b1);endmodule

Verilog

(identifiers) shift_reg_a busa_index _bus3 34net // _ a*b_net // $ _ n@238 // $ _VerilogVerilog

( Escaped identifiers)module \2:1MUX (out, a, b, sel);output out;input a, b, sel; not not1(\~sel ,sel); and and1( a1, a, \~sel ); and and2( b1, b, sel); or or1( out, a1, b1);endmoduleVerilog\Escaped Identifiers

( Escaped identifiers) \~#@sel \busa+ index \{A,B} top.\ 3inst .net1 //

( tokens) $$$time/($display, $monitor)$stop$finish $monitor($time, a = %b, b = %h, a, b);

ab$monitora(), b16

( tokens)#(procedural)module MUX2_ 1 (out, a, b, sel) ;output out ;input a, b, sel ;not #1 not1( sel_, sel);and #2 and1( a1, a, sel_);and #2 and2( b1, b, sel);or #1 or1( out, a1, b1);endmodule(gate delay)(propagation delay)(intrinsic delay)(intra-object delay)

(Compiler Directives)( `)`resetall

(substitution) - `define`define not_delay #1`define and_delay #2`define or_delay #1module MUX2_1 (out, a, b, sel);output out;input a, b, sel;not `not_delay not1( sel_, sel);and `and_delay and1( a1, a, sel_);and `and_delay and2( b1, b, sel);or `or_delay or1( out, a1, b1);endmodule`define `define not_delaynot_delay

(substitution) `undef macro_name`defineVerilog `define vectors_ file "/usr1/chrisz/library/vectors" `define results_ file "/ usr1/chrisz/library/results"`define

(inclusion) - `include`include `include `include "global.v"`include "parts/count. v"`include "../../library/mux. v`includeincludeincludetasks)

Timescale`timescale `timescale / `timescale 1 ns / 100 ps time_unit: time_precision: `timescale

`timescale 1 ns / 10 ps// All time units are in multiples of 1 nanosecondmodule MUX2_1 (out, a, b, sel);output out;input a, b, sel;not #1 not1( sel_, sel);and #2 and1( a1, a, sel_);and #2 and2( b1, b, sel);or #1 or1( out, a1, b1);endmodule

Timescaletime_precisiontime_unittime_precisiontime_unitinteger unit_stringinteger : 1 10 100unit_string: s(second), ms(millisecond), us(microsecond), ns(nanosecond), ps(picosecond), fs(femtosecond)integerunit_stringprecisionprecisiontime_unitprecision_unit`timescale 1s / 1ps11012`timescale 1s/1ms103timescalens

Timescaletimescale STU100fs`timescale 1ns/ 10psmodule1 (. . .);not #1.23 (. . .) // 1.23ns or 12300 STUs. . .endmodule`timescale 100ns/ 1nsmodule2 (. . .);not #1.23 (. . .) // 123ns or 1230000 STUs. . .endmodule`timescale 1ps/ 100fsmodule3 (. . .);not #1.23 (. . .) // 1.23ps or 12 STUs (rounded off). . .endmodule

Verilogtimescale///* */1032`resetall