Seattle Pacific University EE 1210 - Logic System DesignSOP-POS-1 The Connection: Truth Tables to Functions abcF00000011010101111000101111011110abcF00000011010101111000101111011110

Seattle Pacific University EE 1210 - Logic System Design SOP-POS-1

The Connection: Truth Tables to Functions

a b c F

0 0 0 00 0 1 10 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

a b c a b c a b c

a b c a b c

Function F is true if any ofthese and-terms are true!

Condition that a is 0, b is 0, c is 1.

OR

Sum-of-Products form

F a b c a b c a b c a b c a b c ( ) ( ) ( ) ( ) ( )


Minterm Shorthand

F a b c a b c a b c a b c a b cF

( ) ( ) ( ) ( ) ( )

( , , , , ) m + m + m + m + m

F = 1 2 3 5 6

m 1 2 3 5 6

a b c a b c a b c

a b c a b c

a b c

a b c a b c

= m0

= m1

= m2

= m3

= m4

= m5

= m6

= m7

Note: Binary ordering

A minterm has one literal for each input variable, either in its normal or complemented form.

A canonical sum-of-products form of an expression consists only of minterms OR’d together

a b c F

0 0 0 00 0 1 10 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0


Minterms of Different Sizes

Two variables:

a b minterm0 0 a’b’ = m0

0 1 a’b = m1

1 0 a b’ = m2

1 1 a b = m3

Three variables:a b c minterm0 0 0 a’b’c’ = m0

0 0 1 a’b’c = m1

0 1 0 a’b c’ = m2

0 1 1 a’b c = m3

1 0 0 a b’c’ = m4

1 0 1 a b’c = m5

1 1 0 a b c’ = m6

1 1 1 a b c = m7

Four variables:

a b c d minterm0 0 0 0 a’b’c’d’ = m0

0 0 0 1 a’b’c’d = m1

0 0 1 0 a’b’c d’ = m2

0 0 1 1 a’b’c d = m3

0 1 0 0 a’b c’d’ = m4

0 1 0 1 a’b c’d = m5

0 1 1 0 a’b c d’ = m6

0 1 1 1 a’b c d = m7

1 0 0 0 a b’c’d’ = m8

1 0 0 1 a b’c’d = m9

1 0 1 0 a b’c d’ = m10

1 0 1 1 a b’c d = m11

1 1 0 0 a b c’d’ = m12

1 1 0 1 a b c’d = m13

1 1 1 0 a b c d’ = m14

1 1 1 1 a b c d = m15


Sum-of-Products Minimization

F a b c a b c a b c a b c a b c ( ) ( ) ( ) ( ) ( )

F in canonical sum-of-products form (minterm form):

Use algebraic manipulation to make a simpler sum-of-products form

)()()()()()( cbacbacbacbacbacbaF

Use commutativity to reorder to group similar terms

))(())(())(( cbaabacccbaaF Use distributivity to factor out common terms)()()( cbbacbF

Use x’+x = 1 identity

Duplicate term - OK

We will find a better method (K-maps) later…


Product-of-Sums from a Truth Table

A

0 0 0 0 1 1 1 1

B

0 0 1 1 0 0 1 1

C

0 1 0 1 0 1 0 1

F

0 0 0 1 1 1 1 1

F

1 1 1 0 0 0 0 0

CBACBACBAF

Use DeMorgan’s Law to re-express as product-of sums

Find an expressionfor F’ (the complement)

Complement both sides…

)()()( CBACBACBAF

CBACBACBAF

CBACBACBAF


Maxterms

A

0 0 0 0 1 1 1 1

B

0 0 1 1 0 0 1 1

C

0 1 0 1 0 1 0 1

F

0 0 0 1 1 1 1 1

F

1 1 1 0 0 0 0 0

F A B C A B C A B C ( ) ( ) ( )

• To find a Product-of-Sums form for a truth table

• Make one maxterm for each row in which the function is zero

• For each maxterm, each variable appears once• In its complemented form if it is one in the row• In its regular form if it is zero in the row

Maxterms


Maxterm Shorthand

Product of Sums

F in canonical maxterm form:

A B C Maxterms

A + B + C = M7

A + B + C = M6

A + B + C = M5

A + B + C = M4

A + B + C = M3

A + B + C = M2

A + B + C = M1

A + B + C = M00 0 00 0 10 1 0

0 1 11 0 01 0 11 1 01 1 1

F A B C A B C A B CF M M MF

( ) ( ) ( )

0 1 2

M(0, 1, 2)


Boolean operations and gates

• Theorem: Any operation than can be represented by a truth table can be represented in Boolean algebra

• All truth tables can be made out of only and, or, and not functions


NAND/NOR expressionsAny expression can be made of and ANDs, ORs and NOTs

Thus, we can make any expression out of NANDs, NORs, and NOTs

So, we can make any expression out of just NANDs and NORs

X X

note: NANDs and NORs are easy to build with switches

We can make ANDs and ORs from NANDs and NORs and NOTs

We can make NOTs out of a single NAND gate


NAND-only circuits

Using DeMorgan’s Law

NORs can be made with NANDs!

We can make any Boolean expression out of only NAND Gates

NANDs can be made out of NORs!

We can make any Boolean expression out of only NOR Gates


Sum-of-Products Circuits with NANDs

Introduce Double Inverters

Sum-of-Productsworks well with NANDs

DeMorgan’sLaw


Product-of-Sums Circuits with NORs

Introduce Double Inverters

Product-of-Sumsworks well with NORs

DeMorgan’sLaw


Converting General Circuits to NANDs

AB

D

CB

ACD

BD

Introduce Double Inverters to make NANDs:

Add inverters as needed to maintain correct polarity

Represent inverters with NANDs


Seven-Segment Example

A seven-segment display is used to display numbers

a

b

c

d

e

f g

a b c d e f

b c

a b d e g

a b c d g

b c f g

a c d f g

a c d e f g

a b c

a b c d e f g

a b c d f g


Seven Segment Truth TableInputs: Four binary inputs, interpreted as a four-bit binary numberOutputs: Seven outputs, for each of the seven segments

number A B C D a b c d e f g0 0 0 0 0 1 1 1 1 1 1 01 0 0 0 1 0 1 1 0 0 0 02 0 0 1 0 1 1 0 1 1 0 13 0 0 1 1 1 1 1 1 0 0 14 0 1 0 0 0 1 1 0 0 1 15 0 1 0 1 1 0 1 1 0 1 16 0 1 1 0 1 0 1 1 1 1 17 0 1 1 1 1 1 1 0 0 0 08 1 0 0 0 1 1 1 1 1 1 19 1 0 0 1 1 1 1 1 0 1 110 1 0 1 0 x x x x x x x11 1 0 1 1 x x x x x x x12 1 1 0 0 x x x x x x x13 1 1 0 1 x x x x x x x14 1 1 1 0 x x x x x x x15 1 1 1 1 x x x x x x x

Invalid inputs, assume zero

segment a = A’B’C’D’ + A’B’CD’ + A’B’CD + A’BC’D + A’BCD’ + A’BCD + AB’C’D’ + AB’C’D (canonical SOP)

segment a = A’C + A’BD + AB’C’ + B’C’D’ (minimal SOP)

segment a = (A+B+C+D’) (A+B’+C+D) (canonical and minimal POS)


Circuits for Segment a

segment a = A’C + A’BD + AB’C’ + B’C’D’ (minimal SOP)

segment a = (A+B+C+D’) (A+B’+C+D) (canonical and minimal POS)

A B C D

a

ABCD

AB

CD

a

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Seattle Pacific University EE 1210 - Logic System DesignSOP-POS-1 The Connection: Truth Tables to Functions abcF00000011010101111000101111011110abcF00000011010101111000101111011110