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Xilinx XC9500 CPLDs
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High performance— tPD = 5ns, fSYS = 178MHz
36 to 288 macrocell densities
Lowest price, best value CPLD
Highest programming reliability
Most complete IEEE 1149.1 JTAG
Space-efficient packaging, including chip scale pkg
XC9500
125MHz
XC9500XL
200MHz
XC9500XL Key Features
LowestPrice PerMacrocell
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XC9500XL/XV Architecture Embraces In-System Changes
Advanced, 2nd Generation Pin-Locking— Superior routability with
speed
Maximum Flexibility— 54-input function block
fan-in— 90 p-terms per output— 3 global, locally invertible
clocks— Global set/reset pin— P-term OE per macrocell— Clock enable
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XC9500XL/XV System Features
I/O Flexibility— XL:5v tolerant; direct interface to 3.3v & 2.5v— XV:5v tolerant; direct interface to 3.3v, 2.5v & 1.8V
Input hysteresis on all pins
User programmable grounds
Bus hold circuitry for simple bus interface
Easy ATE integration for ISP & JTAG— Fast, concurrent programming times
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XC9500XL/XV Family3.3v ISP XC9536XL XC9572XL XC95144XL XC95288XL2.5v ISP XC9536XV XC9572XV XC95144XV XC95288XV
Macrocells 36 72 144 288Usable Gates 800 1600 3200 6400tpd (ns) XC9500XL 5 5 5 7.5tpd (ns) XC9500XV 4 5 5 6Registers 36 72 144 288fSYSTEM XC9500XL XC9500XV
178200
178178
178178
125151
Packages PC44 PC44
CS48 CS48
VQ44* VQ44*
VQ64 VQ64
TQ100 TQ100
TQ144 TQ144
CS144 PQ208
BG256
FG256*
CS280*
* available in 2Q00
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XC9500 5V Family
XC9536
Macrocells
UsableGates
tPD (ns)
Registers
Max. UserI/Os
36 72 108 144 216
800 1600 2400 3200 4800
5 7.5 7.5 7.5 10
36 72 108 144216
34 72 108 133166
Packages 44VQ44PC
48CSP
44PC84PC100TQ100PQ
84PC100TQ100PQ160PQ
100TQ100PQ160PQ
288
6400
15
288
192
208HQ352BG
160PQ208HQ352BG
XC9572 XC95108 XC95144 XC95216 XC95288
3/97
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Most Complete JTAG Testability
IEEE Std 1149.1 boundary-scan — Testability & advanced system debug/diagnosis— 8 instructions supported (incl. CLAMP)
Full support on all family members
Industry-standard ISP interface
Complete 3rd party support
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FLASH Technology EnablesRapid Die Size Reduction
1.0x
0.3x
0.2x
0.5x
0.6u/2LM 0.5u/3LM 0.35u/4LM 0.25u/4LM
1996
1998
1999
• 0.5 µ = 0.5µ transistor with 0.35µ interconnect
5V
5V
3.3V
0.12x
0.18u/5LM
2001 1.8V
0.3x2.5V
2.5V
DELIVERED
On schedule
On schedule
DELIVERED
DELIVERED
DELIVERED
2000
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Xilinx CPLD Process Leadership
Non-VolatileTechnology Memories
Year used inSPLD/CPLD
SPLD/CPLDPioneer
Year used in
Bipolar Fuse 1973 1978 MMI (AMD)
EPROM 1979 1984
5V EEPROM 1986 1991
5V FLASH 1990 1995
3.3V FLASH 1993 1998
Altera EP-series
Lattice ispLSI
Xilinx XC9500
Xilinx XC9500XL
2.5V FLASH 1996 2000 Xilinx XC9500XV
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Web-Powered CPLD Software
Integrated CPLD Design Environment— FREE, downloadable solution— VHDL, Verilog & ABEL synthesis— Modular, efficient CPLD design
On-line CPLD Design Analysis— Accepts any input— Complete XC9500 Series evaluation— On-line pricing, saves money
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Xilinx CPLDsPerformance ISP
Price• Lowest, best value
Ultra Low Power• CoolRunner
Reliability• 10,000 program/erase cycles• 20 year data retention
Technology• True, 0.35u Flash
Pin-Locking• Industry’s Best
Density• 12% More M/Cs• 22V10s to 960 M/Cs
JTAG• 1149.1 Family Support
Packaging• TQ/PQ & 0.8mm CSP
Silicon Xpresso• WebFITTER• WebPACK
Speed• Fast tPD, fSYS
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Appendix Slides to Follow
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Xilinx Programmable Logic Solutions
SystemGates
XC9500 CPLDs- XC9500XL (3.3v)- XC9500 (5v)- XC9500XV (2.5v)
Key Features- 36 to 288 macrocells- High performance- Low cost- In-system programmable- Chip scale packages
Spartan FPGAs- SpartanXL (3.3v)- Spartan (5v)
Key Features- Low cost ASIC replacement- 5K to 40K system gates- High performance- SelectRAM memory- Chip Scale packages
Feat
ures
5K1K 40K
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Supports high-growth market segments: Communications, Computers, Consumer
New 48-pin CSP:1/3 size of the VQ44
Uses standard IR techniques for mounting to PC board
Chip Scale Packaging Leadership
