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IEEE RANSACTIONS ON COMPUTER-AIDED DESIGN, VOL. CAD5 NO 3, JU LY
1986 379
Automated Synthesis of Data Paths in igital Systems
CHIAJENG TSENG, MEMBER IEEE AND DANIEL P. SIEWIOREK, FELLOW,
IEEE
Absct-Thi paper preen a unifying proedure, alled Facet,
for he auomaed ynhei of daa pah a he regierranfer level.
The proedure minimize he numer of orage elemen daa oper
aor and ineronneion uni. deign generaor named Emerald
aed on Faet, wa developed and implemened o failiae exenive
experimen wih he mehodology. The inpu o he deign generaor
i a ehavioral deripion whih i viewed a a ode equene. Emerald
provide mehanim for ineraively manipulaing he ode e
quene. Dieren form of he ode equene are mapped ino daa
pah of dieren o and peed. Daa pah for he ehavioral de
ripion of he M2910 he M2901 and he IBM Syem/370 were
produed and analyed Deign for he M2910 and he M2901 are
ompared wih ommerial deign. Overall he oal numer of gae
required for Emerald's deign i aou 15 peren more han he om
merial deign The deign pae panned y he ehavioral pei
aion of he M2901 i exenively explored
1. NTRODUCTON
THE research presented in this paper is a portion ofthe
CaegieMellon University Design Automation
(CMUDA) system [8] Using the ISPS description [5] asinput the
CMUDA system proceeds through global op-timization, design style
selection datamemory alloca-tion, physical module binding control
allocation, chippartitioning and mask generation phases This paper
de-scribes the result of some research in the datamemoryallocation
phase
The data paths of a digital system generally containthree types
of primitive elements: storage elements, data
operators, and interconnection units Given a
behavioraldescription the problem of datamemory allocation includes
ve subproblems They are the specication of dataow and control ow
the allocation of storage elementsthe allocation of data operators,
the allocation of inter-connection units , and the exploration of
the design space
Prior research in datamemory allocation is outlined inSection II
The ISPS description species the data owand control ow. The input
to the datamemory allocatoris an intermediate form, named the Value
Trace (VT) [ 13] 20] of the ISPS description Facet views the VT as
a codesequence Section III contains a code sequence which is
used as a running xample to illustrate the synthesis pro-cedure
Given a list of operation sequences (in somesense, this means the
performance is specied) the prob
Manuscrpt receved July 8 984 This work was done a the
CaegeMellon Uniersty Ptsburgh PA and was suppoed by he Naonal
Scence Foundaon under Grant ECS8207709
CJ. seng s wh A&T Bell Laboraores Murray Hill 07974D P
Siewore s wh he Depamen of Electrcal and Computer En
gneerng and the Deparment o Compuer Scence Caege Mellon
Un-versty, Pttsburgh PA 1523
IEEE Log umber 8608705.
lem of design improvement is conceed with the min-imization of
the number of storage elements data opera
tors, and interconnection units acet transforms thesethree
minimization problems into the cliquepartitioningproblem The notion
of cliquepartitioning is introducedin Section IV . Sections VVII
describe the formulationsand present algorithms for generating
solutions for eachof these three problems Sections VIII and IX
discuss theimplementation of an automated data path
synthesizerbased on the algorithms Evaluation of designs is
discussed in Section X and the evaluation criteria are use
tocompare automatically synthesized designs to commercialdesigns in
Section XI. Section XII contains conclusionsand suggestions for
future work Finally, details of the
cliquepartitioning algorithms are included in the Appendix
II ELATED ORK
Over the last two decades, signicant eort has beendevoted to the
development of methodologies for the syn-thesis of data paths in
digital systems This section con-tains a selective survey of the
related research which canbe found in the literature.
The EXPL system [4] uses a behavioral description asthe design
specication and a module set for implemen-tation of the design The
behavior is described in ISPwhich is a high level hardware
description language Themodule set used is the Digital Equipment
CorporationPDP 6 Register Transfer Modules (RTM) The behav-ioral
description of the system to be designed is compiledinto an inteal
representation (a graph model) . Based onthe graph model, a number
of serialtoparallel and paralleltoserial transformations are
developed for exploringthe design space. Heuristic techniques are
used to limitthe search process. Examples (an RTM multiplier and
acontroller for a conveyorbin system) are given to illustrate the
design procedure Applying these transformations to the initial
designs of these examples improve-ments up to a factor of two in
cost and speed are observed
Rege 17] addresses the problem of designing a smallset of high
level (higher than the register transfer leveland lower than the
computer leel) Data modules (D-modules) useful for constructing
digital systems He divides the design activity into a number of
welldenedsubactivities The activities are dened by means of
threespaces: the specication space, the solution space, andthe
space of primitive components He rst proposes abasic model for the
specication space Then he developsa set of design and analysis
techniques to survey the space
02780070/86/07000379$01 00 1986 IEEE
