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268 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 2, MAY 2009

A Manufacturing Cost Model for 3-D MonolithicMemory Integrated Circuits

Andrew J. Walker, Member, IEEE

Abstract—Imminent lateral scaling issues with NAND Flash areforcing manufacturers to consider 3-D process integration to keepsingle chip memory capacities rising while keeping costs down. Inthis way, several layers of memory cells are stacked on top of a sil-icon substrate using a single series of process steps with no mate-rial bonding used. This paper presents a general and practical costmodel showing the advantages of 3-D process integration togetherwith the main parameters determining the total cost. This modelsuggests that a mini revolution will soon be upon us consisting ofmultiprogrammable stacked nonvolatile memory cells in a mono-lithic chip.

Index Terms—3-D, memory, nonvolatile (NV), yield.

I. INTRODUCTION

T HREE-DIMENSIONAL (3-D) stacking of circuits [1] isbeing promoted as a way to increase CMOS performance,

reduce form factor, combine different materials and functionsall at reasonable cost and usually in this descending order ofimportance. While this may be true for fast CMOS circuits,the most important consideration for NAND Flash is cost. Upuntil now, the way to increase capacity in a single package hasbeen to stack several NAND chips where each chip consists ofa single physical layer of Flash cells built into a silicon wafersubstrate. Successful scaling of lateral dimensions has allowedthe capacity per NAND chip to double almost every year withthe minimum feature size being the real half pitch in the tech-nology.

NAND Flash scaling problems have been reported recentlywith monolithic 3-D process integration being proposed as asolution [2] to continue the decreasing cost per bit with in-creasing single chip capacities. To avoid confusion with other3-D stacking approaches, the NAND Flash monolithic approachconsists of stacking several layers of memory cells on top of asilicon substrate using a single series of process steps with nomaterial bonding required.

The cost analysis of such a monolithic 3-D approach is not in-tuitively obvious except for the simple-minded observation that,for a certain memory capacity, cost is being added in the processto decrease the die size and so increase the number of die perwafer. In this way, monolithic 3-D integration can be seen in his-torical perspective where traditionally the way to decrease costper bit or transistor has been to laterally shrink and add processcomplexity to solve the resultant process and device problems

Manuscript received July 09, 2008; revised November 26, 2008. Current ver-sion published May 06, 2009.

The author is with the Schiltron Corporation, Mountain View, CA 94040 USA(e-mail: [email protected]).

Digital Object Identifier 10.1109/TSM.2009.2017643

[3]. Up until now, lateral scaling has been very successful inthe quest for decreasing cost per bit or transistor. Impendingphysical limits to lateral scaling change the economics and re-sult in monolithic 3-D integration becoming the least expensivepath to decreasing bit and transistor costs. The added processcomplexity associated with 3-D replaces that arising from lat-eral scaling. The importance is to know the cost leverage.

Given the high probability that such monolithic 3-D integra-tion will serve the NAND Flash market [4] it is the intention ofthis paper to put the cost analysis on a firm footing.

This paper is organized as follows: Section II deals with yielddue to monolithic 3-D stacking; Section III presents a discus-sion on the process cost increase and die cost reduction fromincreased die per wafer; examples in the use of the cost modelare given in Section IV; Section V contains a discussion of thefindings and Section VI concludes the paper.

II. YIELD

The effect on defect-limited-yield of adding process com-plexity is a well-trodden path in silicon manufacturing. For ourdiscussion here, Sredni’s general mathematical description willform the basis for the analysis [5] with the same variable changeas used by Rung [6]. Thus we have:

(1)

where is the defect-limited-yield, is the defect density,is the effective critical area in which the defects define the

yield, and is a parameter. With this equation choice for Y,we do not limit ourselves to one particular non-composite yieldmodel since, as noted by both Sredni and Rung, this equationcovers most well-known models: for , we have the Seeds-Price expression [7], [8]; for , Dingwall’s expression [9];for , a close approximation to Murphy’s expression[10]; and for , the Poisson expression. This generalequation for yield will help to show that the conclusions of thecost model are independent of any particular yield model.

In a high density 2-D Flash memory, can be reasonablyassociated with the memory array area since this is the regionof the chip using the most aggressive design rules and so mostprone to spot defects. When we consider a 3-D Flash chip con-sisting of layers of devices, we can write the total yield ofsuch a 3-D approach as

(2)

0894-6507/$25.00 © 2009 IEEE

WALKER: MANUFACTURING COST MODEL FOR 3-D MONOLITHIC MEMORY INTEGRATED CIRCUITS 269

Fig. 1. Ratio of 3-D yield to 2-D yield for different defect densities. The 2-D case has a fixed critical effective area at 2 cm which is then divided up into the 3-Ddevice layers. The yield parameter � is fixed at 1. Note the strong effect of defect densities on 3-D yield.

where all the symbols have the same meanings as above but foreach physical memory layer.

A practical simplification of (2) can be made with the rea-sonable assumptions that each memory layer in the 3-D stackadds spot defects at the same rate as any other layer and thatthese defects tend to affect the memory layer they are on andnot those layers above and below them. The first assumption canbe defended by the identical physical nature of each memorylayer and its associated processing steps. A slight adjustmentwould be necessary perhaps if the first memory layer is in thesilicon bulk versus those monolithic memory approaches whereall layers are built above the silicon bulk [11] since the pro-cessing steps would be slightly different between the first layerand all the rest. The second assumption is reasonable when theindividual memory layers are isolated from each other using adielectric that is thicker than the minimum feature size in eachmemory layer (see for instance Jung). It is then envisaged thatspot defects are far likelier to cause problems in the layer theyare on than interfere with other layers.

With these assumptions, (2) becomes:

(3)

with the symbols having their definitions above.It is instructive to compare the 3-D and 2-D yields for memory

chips that have the same total number of cells. Fig. 1 shows theratio of 3-D to 2-D yields as a function of the number of devicelayers stacked in the 3-D case with defect density as a parameter.This example used a fixed effective critical area of 2 cm (equiv-alent to 32 Gbit using 50 nm minimum feature size and 2 bits percell). The key is that this total effective area is distributed over

device layers in the 3-D case. Therefore, the in (3) is the2-D area divided by . Fig. 1 shows that monolithic 3-D in-

tegration has very little impact on yield compared to 2-D whenthe defect densities per device layer are on the order of thosealready obtainable in advanced processes [12]. A further resultfrom this yield analysis is shown in Fig. 2. Here, the ratio of 3-Dto 2-D yields is shown as a function of increasing values of theparameter with defect density as a parameter. Again, the ratioof the yields is almost independent of the yield model chosenwhen the defect densities per device layer are on the order ofthose already obtainable in advanced processes. These are ex-tremely important results for 3-D memory integration and willbe used later in the full cost model comparison with 2-D.

III. PROCESS AND DIE COST

When device layers are stacked in 3-D, the total process be-comes more complex and expensive. We can calculate the wafercost of adding device layers with the following:

(4)

(5)

where and are the process costs of the wafer for 2-Dand 3-D respectively; is the base wafer cost with all the sup-port circuitry but without memory cells (assumed to be verysimilar in both the 2-D and 3-D approaches); is thecost of a critical mask photolithography step and its associatedprocess steps in 2-D but then replicated in 3-D; is the rate ofincrease in wafer cost between process generations [13] to ac-count for the possibility that the 3-D approach can use older gen-erations of technology (values between 1.5 and 2 were used byNakatsuka, but for NAND Flash may actually be increasingdue to the use of double patterning technology and any migra-tion to more advanced wavelength lithography); is the numberof technology generations between the 2-D and 3-D approaches


Fig. 2. The ratio of 3-D to 2-D yields as a function of � in the yield (3) with defect density as a parameter. � has been fixed at 5 and the effective critical areaat 2 cm .

(0 if using the same node, 1 if 2-D is at 32 nm and 3-D uses42 nm); and and are the total number ofcritical masking steps needed in 2-D and 3-D respectively.

The total number of dice per wafer in both 2-D and 3-D canbe approximated by

(6)

where is the wafer diameter and is die area. The latter inthe 3-D case can be expressed as

(7)

where is the total number of cells in the chip; is thenumber of device layers; is the area of a single memorycell on each layer; is the array efficiency of the chip with asingle layer of cells defined as the memory array area “as seenfrom above” divided by the total chip area and in %; MLC is avariable for multilevel cell (1 for single bit per cell; 2 for 2 bitsper cell and so on).

It will be apparent that die size cannot continue shrinkingwith added 3-D device layers since the CMOS driving circuitryremains in the substrate. Indeed, the minimum die size alongwith the number of added device layers needed to reach it canbe calculated. Imagine that all memory cells in a 2-D versionof a chip could be elevated above the substrate in 3-D fashion.Then the minimum die size is given as the area originally takenup by this peripheral substrate circuitry. This area is given as:

(8)

where all symbols have been defined before. Now, setting (7)equal to (8) and solving for , we reach the following equation

for the number of 3-D device layers above the substrate neededto achieve the minimum die size:

(9)

with all symbols defined before. It should be clear that the min-imum die size given by (8) is not achievable if the first layer ofmemory cells is placed in the substrate as is the case in the Jungreference. In this case, (7) would have to be recast as follows:

(10)

which shows (8) as an asymptotic limit at large . This ofcourse would be at the expense of increased wafer cost givenin (5). The general point is that it is always better to elevate allmemory cells above the wafer substrate and keep the latter forcontrol circuitry to be able to minimize the die size at minimumadded process cost. We shall make this comparison more con-crete below.

It is perhaps better in the interests of clarity to reformulate (7),(8) and (10) in terms of the original 2-D die size. The results are:

(11)

when no memory cells are placed in the silicon substrate andwith a minimum at:

(12)


Fig. 3. Ratio of 3-D to 2-D die size as a function of the number of 3-D device layers for the cases where all memory cells are above the substrate and where thefirst layer of memory cells are in the substrate.

The equivalent of (11) when the first layer of memory cells isplaced in the substrate is:

(13)

which clearly has no minimum but asymptotically approaches(12) with increasing 3-D device layers as has been stated above.Fig. 3 shows the ratio of 3-D to 2-D die sizes as a function ofthe number of device layers stacked in 3-D for the two caseswhere the first layer of memory cells is either above the substrateor in the substrate. Clearly, putting all memory cells above thesubstrate allows us to reach the minimum die size at lower addedprocess complexity.

We shall now revisit the yield equations given by (2) and(3) with the realization that there is indeed a minimum die sizeachievable with 3-D memory stacking. The key here is that thenumber of 3-D dice per wafer has a maximum since has aminimum. However, the yield in a memory is defined by the ef-fective critical area, , which is approximated by the memoryarray area. In 3-D for a fixed capacity memory, per layercontinues to shrink as increases even beyond the minimumdie size. Therefore, for a fixed capacity single chip memoryfrom a purely yield perspective, it pays to continue adding 3-Dmemory layers. The cost of this will be taken up by the processcomplexity and resultant wafer cost as given by (5).

IV. COST EXAMPLES

The general equation for the comparison of cost between the3-D and 2-D approaches to achieve a memory of fixed capacitycan be given as

(14)

where and are the good die costs for 3-D and 2-Drespectively and where all other parameters have been definedabove.

In the first example, we shall look at the case of a 64 GbitFlash memory using a minimum feature size of 32 nm in both2-D and 3-D. The defect density (per layer in the 3-D case) isset at 0.1/cm . Other relevant parameters are: cell size in bothcases given as where is the minimum feature size; inyield model is 1; 300 mm wafer diameter; MLC is 2 for both2-D and 3-D; in 2-D is 75%; 2-D uses 4 critical lithographymasks while 3-D uses 4 per device layer added; is $2800 and

is $200, similar to standard foundry numbers. Fig. 4shows the cost comparison for this case.

The second example uses the inputs as in the first examplebut changes the 3-D MLC to 1 which would model the initialinability to do MLC in 3-D. Fig. 4 again captures this result.

The third example uses the approach where the 3-D versionof the chip would use older technology. In this case, a 64 GbitFlash memory is made in 2-D using the inputs as in the firstexample. The 3-D version uses 42-nm technology at about onegeneration behind 32 nm. The is set at 2. Fig. 4 shows the costcomparison.

The fourth example is the same as the third except for a defectdensity of 0.02 cm for the 42 nm technology versus 0.1/cmfor the 32-nm technology reflecting a more mature technologynode.

The fifth example is the same as the fourth except that the 3-Dversion has MLC set at 1. Fig. 4 shows the result.

As NAND Flash manufacturers pursue lateral scaling, every-thing is being done to avoid a transition to the more expen-sive Extreme Ultra Violet (EUV) lithography. The measuresbeing taken include double patterning technology and immer-sion 193-nm lithography. Nevertheless, if the NAND cells canindeed be laterally scaled, a transition point will be reached. Thecost model can take this into account through increasing asused and defined in (5). Fig. 5 shows the example of the costadvantage of 3-D stacking the older more mature (by that time)technology at 32 nm versus the 2-D approach using 25 nm that


Fig. 4. Ratio of 3-D to 2-D die costs as a function of the number of 3-D device layers added for a fixed capacity memory (64 Gbit in this case) for various scenarios.The 2-D AE0 was set at 75%. Example 1: 32 nm for both; � � �� cm ; � � �; �� for both; 2-D uses four critical masks; 3-D uses four critical masksper device layer added; � � ��;� � ��. Example 2: as example 1, but with �� for 3-D. Example 3: as example 1, but 3-D uses 42 nmwith � � �. Example 4: as example 3, but with � � �� cm for 3-D. Example 5 as example 4, but with �� for 3-D.

Fig. 5. Ratio of 3-D to 2-D die costs as a function of the number of 3-D device layers added for a fixed capacity memory (64 Gbit in this case) with � as aparameter. 2-D uses advanced 25-nm half-pitch while 3-D uses more mature 32-nm half-pitch. � � �� cm , �� and �� . The same basewafer and adder costs were used as in Fig. 4.

would perhaps use EUV. For this example, a 64 Gbit was usedwith all other parameters as given in the first example above.Here we can see the increasing advantage of using 3-D even onolder technologies as the cost of the more advanced 2-D tech-nology increases.

If we can use an older more mature technology in 3-D whilethe 2-D approach is at the most advanced node, we may expectthat defect densities on the more mature technology would be

lower. This also has an impact on the relative costs as can beseen in Fig. 6 where the 2-D approach is at a minimum halfpitch of 25 nm and 3-D is at 32 nm. The has been fixed at 3.The defect density for 2-D has been set at 0.1/cm while the 3-Ddefect densities vary to show the effect. All other parameters areas in the first example above.

The ability to use older more mature technologies to competeon cost allows us to take advantage of their lower defect densi-


Fig. 6. Ratio of 3-D to 2-D die costs as a function of the number of 3-D device layers added for a fixed capacity memory (64 Gbit in this case) with the 3-D �

as a parameter. 2-D uses advanced 25-nm half-pitch while 3-D uses more mature 32-nm half-pitch. 2-D � � �� cm , �� , �� and � is fixedat 3. The same base wafer and adder costs were used as in Fig. 4.

Fig. 7. Ratio of 3-D to 2-D die costs as a function of the number of 3-D device layers added for a fixed capacity memory (64 Gbit in this case) with the 3-Dtechnology half-pitch as a parameter indicating the use of older more mature technologies for 3-D. The 2-D � � �� cm while all 3-D � � �� cm toreflect their process maturity. � is fixed at 3 to reflect the much more expensive 2-D node. MLC is 2 for all except the one case shown. �� . The samebase wafer and adder costs were used as in Fig. 4.

ties. Fig. 7 shows the cost advantages of this strategy. In thesecases, the 2-D approach is at a minimum half pitch of 25 nmand 3-D is fabricated at various older nodes. The defect den-sity for 2-D is set at 0.1/cm while the 3-D defect density isfixed at 0.01/cm to reflect the maturity of the older technolo-gies. Fig. 7 shows the advantages of such an approach. Also in-cluded is the case where the 32 nm 3-D approach uses a singlelevel cell to show that even this can be cheaperthan the advanced node with MLC at 2 if the defect conditionsare right.

The final example considers the case when 2-D lateral scalinghas reached its limit for NAND Flash. To provide solid-stateproducts with ever-increasing memory capacities to compete in

the computer hard drive market, several possibilities are thenopen to us: first, several 2-D dice stacked in a single package;second, several 3-D dice stacked in a single package; third, onemonolithic 3-D die in a package. In this example, the followingassumptions have been made: 32 nm is the final lateral min-imum half-pitch, F; a single cell area is given as ; 64 Gbitis the final single 2-D die capacity; 2-D and 3-D approachesconsist of 2 bits per cell; 2-D array efficiency is 75%; 3-D hasno memory cells in the substrate; each new 3-D device layeradds four critical lithography steps; the base wafer cost withoutcritical memory layers in 2-D and 3-D is $2800; each new crit-ical lithography step and its associated process steps costs $200;the 3-D die size reaches a minimum after four device layers


Fig. 8. Ratio of 3-D cost to 2-D cost to achieve given capacity as a function of the capacity with defect density as a parameter. 32 nm half-pitch is assumed to bethe last laterally scaled node. 64 Gbit is then the final 2-D single chip. 3-D approaches consist of: either building single die with four device layers all above thesubstrate and then chip-stacking these to achieve the capacity; or stacking device layers (above the substrate) monolithically on a single substrate to achieve thecapacity. �� ,�� , 3-D device layer consists of 4 critical lithography steps. The same base wafer and adder costs were used as in Fig. 4.

have been added (therefore, the effective critical area in (3) isfixed and does not shrink with increasing monolithic capacitieswhereas keeps on rising).

Fig. 8 shows the ratio of 3-D capacity cost to 2-D capacitycost as a function of the single package memory capacity (nocosts have been added to the multichip cost originating fromthe actual physical stacking and bonding). The two 3-D ap-proaches are: first, make single chip 64 Gbit using four devicelayers reaching the minimum die size and physically stack thesein a package similar to the 2-D multichip stacking; second, add3-D device layers monolithically until the required capacity isreached with the minimum die size having been reached afterfour device layers. The variable parameter in Fig. 8 is the de-fect density per device layer (being equal to the defect densityin 2-D). Clearly, 3-D in whatever form provides a less expen-sive option to 2-D die stacking. Also, the defect density per de-vice layer is the key to achieving low cost. The values for thisparameter are within the reach of existing memory productionfacilities.

V. DISCUSSION

Monolithic 3-D integration has been touted since the early1980’s as the solution to impending CMOS lateral scaling limits[14]. CMOS has however been successfully scaled since then.The problems are now more severe in NAND Flash scalingleading to new calls for monolithic 3-D integration specificallyfor high density Flash. The resulting increase in process com-plexity and wafer cost can be seen in historical perspective asbeing part of the same trend as coming from lateral scaling. Nowhowever, 3-D monolithic integration is gaining in impetus dueto the impending lateral scaling limits specific to NAND Flash.

Figs. 1 and 2 show monolithic 3-D die yield can be compet-itive provided defect densities are kept on their current trendsfor 2-D. Fig. 4 shows that various degrees of freedom are madeavailable through 3-D integration to achieve low cost solutions.Apart from the use of the most advanced tooling, older de-preciated fabrication facilities could also be used to achievelower cost than 2-D approaches. This provides possibilities foruseful “fab filling” to manufacturers with spare capacity andolder tooling and could extend the life of such facilities. Fig. 4also shows the appearance of an optimum number of 3-D devicelayers the position of which depends on the compactness of thesubstrate control circuitry.

The possibility of using older more mature technologies toserve the high density Flash market is apparent from Figs. 5–7where fabrication facility depreciation and lower defect densi-ties could even allow single level cell in 3-D to be cheaper thanmulti-level cells in 2-D at the advanced node.

An interesting example of the possibilities of 3-D monolithicintegration is that of the cost of increasing capacity solutionsspecifically to be able to provide solid-state computer drivesat reasonable cost compared to magnetic hard drives. Fig. 8showed the 3-D cost advantages over stacked 2-D dice. At thetime of writing, solid-state Flash-based drives are gaining afoothold in the computer hard drive market but at significantcost disadvantage. To be able to take sizable market share, theFlash-based solution needs to drop in price. Clearly, severallower cost scenarios become possible provided defect densitiesare kept in control.

VI. CONCLUSION

The advent of lateral scaling limitations combined withthe ever-increasing market demand for high density NAND


Flash have given added impetus to monolithic 3-D integration.This paper has presented a simple and practical cost model toshow the advantages of such an approach. Several degrees offreedom are possible in achieving lower cost high density Flashmemory than the 2-D approach allows. The main points are thefollowing.

• 3-D monolithic stacking can achieve lower cost at both thesame technology node as and at older nodes than 2-D.

• The optimum approach is to place all memory cells abovethe substrate.

• There is then a minimum in die size at a given number ofadded device layers.

• Monolithic stacking is the best path to lower bit cost as weapproach the limits to 2-D scaling.

We are not far from the situation where high density non-volatile memory products consist of single chips each with fouror more active device layers in a monolithic stack. As in allsuch mini revolutions in silicon technology, the cost drives thechange.

REFERENCES

[1] , C. S. Tan, R. J. Gutmann, and L. R. Reif, Eds., Wafer Level 3-D ICsProcess Technology. New York: Springer, 2008.

[2] S. M. Jung, J. Jang, W. Cho, H. Cho, J. Jeong, Y. Chang, J. Kim, Y.Rah, Y. Son, J. Park, M. Song, K. Kim, J. Lim, and K. Kim, “Threedimensionally stacked NAND flash memory technology using stackingsingle crystal Si layers on ILD and TANOS structure for beyond 30 nmnode,” in Tech. Dig. Int. Electron Devices Meeting, 2006, pp. 1–4.

[3] W. Maly, “Cost of silicon viewed from VLSI design perspective,” inTech. Dig. 31st Conf. Design Automation, Jun. 1994, pp. 135–142.

[4] K. Prall, “Scaling non-volatile memory below 30 nm,” in Tech. Dig.Non-Volatile Semiconductor Memory Workshop, 2007, pp. 5–10.

[5] J. Sredni, “Use of power transformations to model the yield of IC’s asa function of active circuit area,” in Tech. Dig. Int. Electron DevicesMeeting, Dec. 1975, pp. 123–125.

[6] R. Rung, “Determining IC layout rules for cost minimization,” J. Solid-State Circuits, vol. 16, no. 1, pp. 35–43, Feb. 1981.

[7] J. E. Price, “A new look at yield of integrated circuits,” Proc. IEEE,vol. 58, no. 12, pp. 1290–1291, Aug. 1970.

[8] R. B. Seeds, “Yield and cost analysis of bipolar LSI,” in Tech. Dig. Int.Electron Devices Meeting, Oct. 1967, paper 1.1.

[9] A. G. F. Dingwall, “High-Yield-Processed bipolar LSI arrays,” in Tech.Dig. Int. Electron Devices Meeting, Oct. 1968, paper 14.6.

[10] B. T. Murphy, “Cost-Size optima of monolithic integrated cicruits,”Proc. IEEE, vol. 52, no. 12, pp. 1537–1545, Dec. 1964.

[11] M. Johnson, “512-Mb PROM with a three-dimensional array of diode/antifuse memory cells,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp.1920–1928, Nov. 2003.

[12] R. C. Leachman, Competitive Semiconductor Manufacturing: FinalReport From Benchmarking Eight-Inch, Sub-350 nm Wafer Fabrica-tion Lines Univ. California, Berkeley, 2002.

[13] H. Nakatsuka, “Derivation and implication of a novel DRAM bit costmodel,” IEEE Trans. Semicond. Manuf., vol. 15, no. 2, pp. 279–284,May 2002.

[14] C. Petti, S. B. Herner, and A. J. Walker, Monolithic 3D Integrated Cir-cuits. New York: Springer, 2008.

Andrew J. Walker (M’90) was born in Sialkot,Pakistan, in December 1962. He received the B.Sc.(Hons) degree in physics from Dundee University,Scotland, in 1985 and the Ph.D. degree from theTechnical University of Eindhoven, The Nether-lands, in 1994.

He was with Philips Research Laboratory, Eind-hoven from 1985 to 1994 where he worked onMOS transistor and nonvolatile memory physicsand technology. Between 1994 and 1998, he workedprimarily on ESD at Cypress Semiconductor, San

Jose, CA. After a one year stint at Artisan Components, Sunnyvale, CA, andfour years at Matrix Semiconductor, Santa Clara, CA, he became an ESDconsultant. He founded Schiltron Corporation to investigate new monolithic3-D Flash technologies.

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