04a Xilinx Design Flow

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2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only

Xilinx Design FlowFPGA Design Flow Workshop


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Xilinx Design Flow 3 - 2 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only

Objectives

After completing this module, you will be able to: List the steps of the Xilinx design process

Implement an FPGA design by using default software options


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Outline

Oeriew

!"#

"ummary


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$ranslate

%ap

Place & 'oute

Xilinx Design Flow

Plan & (udget )D* '$*

"imulation

"ynthesi+e

to create netlist

Functional

"imulation

reate

(it File

Attain $iming

losure

$iming

"imulation

!mplement

reate ode-

"chematic


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Xilinx Design Flow 3 - 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only

Design !ntry

Plan and budget

Two designentry methods! "#L or schematic$ Architecture %i&ard' ()*+ Generator, system' and -tate(A# are a.ailable

to assist in design entry

%hiche.er method you use' you will need a tool to generate an +#IF or /G(netlist to bring into the Xilinx implementation tools

$ Popular synthesis tools! -ynplify' Precision' FPGA (ompiler II' and X-T

-imulate the design to ensure that it wor0s as expected1

Plan & (udget reate ode-"chematic )D* '$*"imulation

"ynthesi+e

to create netlist

Functional

"imulation. . .


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Xilinx #m$lementation

)nce you generate a netlist'

you can implement the design

There are se.eral outputs of

implementation$ *eports

$ Timing simulation netlists

$ Floorplan files

$ FPGA +ditor files$ and more1

Translate

2ap

Place 3 *oute

!mplement

% % %

%%%


7/25Xilinx Design Flow 3 - & 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only

'(at is #m$lementation)

2ore than 4ust 5Place 3 *oute6

Implementation includes many phases$ $ranslate:2erge multiple design files into a single netlist

$ %ap:Group logical symbols from the netlist 7gates8 into physical

components 7slices and I)9s8

$ Place & 'oute:Place components onto the chip' connect them' and

extract timing data into reports

+ach phase generates files that allow you to use other Xilinx tools

$ Floorplanner' FPGA +ditor' XPower


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+iming ,losure

The Timing (losure Flow is a recommended method for helping designsmeet their timing ob4ecti.es

#etails on each part of the flow are discussed in this course and in theDesigning for Performancecourse


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Download

)nce a design is implemented' you must create a file that the FPGA

can understand$ This file is called a bitstream! a 9IT file 7:bit extension8

The 9IT file can be downloaded directly to the FPGA' or it can be

con.erted into a P*)2 file' which stores the programming information


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Outline

Oeriew

!"#

"ummary


11/25Xilinx Design Flow 3 - .. 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only

'(at is #0!)

Graphical interface to

design entry and

implementation tools$ Access to synthesis

and schematic tools Including thirdparty

synthesis tools

$ Implement your design

with a simple doubleclic0

Finetune witheasytoaccess

software options


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'ebU$date

Automatically chec0s for -er.ice Pac0s on the web

Alerts you when an update is a.ailable

-upports P( platform only



,reating a 1roject

-elect File/ew

Pro4ect

/ew Pro4ect %i&ard

guides you through

the process$ Pro4ect name

and location

$ Target de.ice

$

-oftware flow$ (reate or add

source files



,reating and Adding

0ource Files To include an existing source file'

doubleclic0 Add #/isting "ource

To create a new source file'

doubleclic0 reate 0ew "ource

and choose the type of file$ "#L file

$ IP

$ -chematic

$

-tate diagram$ Testbench

$ (onstraints file


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#m$lementing a Design

To implement a design!$ In the -ources in Pro4ect window'

select the tople.el source file "#L' schematic' or +#IF'

depending on your design flow$ In the Processes for -ource window'

doubleclic0 Implement #esign


16/25Xilinx Design Flow 3 - ." 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only

#m$lementation 0tatus

I-+ will run all of the necessary stepsto implement the design

$ -ynthesi&e "#L code$ Translate

$ 2ap$ Place 3 *oute

Progress and status are indicated by icons$ Green chec0 mar0 7 8 indicates that the

process was completed successfully

$ ;ellow exclamation point 7 18 indicateswarnings

$ ;ellow


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0imulating a Design

To simulate a design!$ In the -ources in Pro4ect window'

select a testbench file

$ In the Processes for -ource window'

expand 2odel-im -imulator$ #oubleclic0 -imulate

9eha.ioral 2odel or

-imulate PostPlace 3 *oute

2odel

(an also simulate after Translateor after 2ap


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Xilinx Design Flow 3 - .* 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only

0ub-1rocesses

+ach process can be expanded to .iew

subtools and subprocesses$ Translate

Floorplan

Assign Pac0age Pins$ 2ap

Analy&e timing

$ Place 3 *oute Analy&e timing

Floorplan

FPGA +ditor

Analy&e power

(reate simulation model


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ierarc(ical 0imulation

etlists (reate separate simulation netlists and -#F files for each le.el of design

hierarchy$ -implifies timing .erification

$ Allows you to reuse testbenches from beha.ioral simulation

"ierarchy must be maintained during synthesis

=se the >++P?"I+*A*("; attribute in =(F file

For more information' see Answer @BCDE


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Xilinx Design Flow 3 - 2/ 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only

1rogram t(e F1A

There are two ways to

program an FPGA$ Through a P*)2 de.ice

;ou will need to generate

a file that the P*)2programmer will

understand

$ #irectly from the computer =se the i2PA(T

configuration tool


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5eview 6uestions

%hat are the phases of the Xilinx design flow

%hat are the components of implementation' and what happens

at each step

%hat are two methods used to program an FPGA


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Answers

%hat are the phases of the Xilinx design flow$ Planning and budgeting' create code or schematic' *TL simulation' synthesi&e'

functional simulation' implement' timing closure' timing simulation' 9IT file

creation

%hat are the components of implementation' and what happensat each step

$ Translate! merges multiple design files into one netlist

$ 2ap! groups logical symbols into physical components

$ Place 3 *oute! places components onto the chip and connects them together

%hat are two methods used to program an FPGA$ P*)2

$ Xilinx i2PA(T configuration tool


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0ummary

Implementation means more than place 3 route

Xilinx pro.ides a simple 5pushbutton6 tool to help you through the Xilinx

design process


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'(ere ,an # 7earn 8ore)

(omplete design flow tutorials$ http!support:xilinx:com#ocumentationTutorials

)n the phases of implementation$ http!support:xilinx:com-oftware 2anuals#e.elopment -ystem

*eference Guide

)n hierarchical simulation netlists$ http!support:xilinx:com Answer @BCDE

(onfiguration Problem -ol.er

$ http!support:xilinx:comProblem -ol.ers(onfiguration Problem-ol.er

Documents

04a Xilinx Design Flow