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08.601 Microcontroller Based System Design

Introduction:

First commercial processor on chip, the microprocessor is Intels 4-bit 4004 released in

1971.

By-product of microprocessor development is microcontroller

First microcontroller is 8748 by Intel (not familiar) released in 1976, but the powerful

one is 8051 released in 1981.

Variety of applications for microcontroller and such products became more intelligent

and programmable

Some examples are:

1. TV, CD players, Remote controllers, Camera, Cellular phones, etc.

2. Computers, Fax machines, Photo copiers, Printers, Security systems, etc.

3. Instrumentation, Engine control, Automobiles, etc.

Microprocessor versus Microcontroller Both are stem from same idea, made from same people and sold to same type of system

designers and programmers, but have many differences.

1. Microprocessor

General purpose digital computer Central Processing Unit (CPU)

Processor on a Chip

Not a complete digital computer

General Block diagram of microprocessor:

To make a complete microcomputer, memories like ROM and RAM, memory

decoders, oscillator, IO devices, serial and parallel ports, etc. are required.

A very large system can be configured around CPU as the application demands,

since the flexibility of microprocessors they are referred as General Purpose

Processor.

Department of ECE, VKCET Page 1

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Block diagram of a system designed using microprocessor:

2. Microcontroller

True computer on a chip, also referred as System on a Chip

Uses all features of microprocessor with peripherals like RAM, ROM, Ports, clock

circuit, etc.

General block diagram of microcontroller:

Similar to microprocessor, microcontroller is also general purpose device, but not

very flexible as microprocessor.

Block diagram of system using microcontroller:


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Microcontroller itself is a system

An eg.

Comparison between Z80 microprocessor and 8051 microcontroller:

Features 8085 8051

Pins 40 40

Address lines 16 16

Data lines 8 8

Interrupt lines 6 2

IO lines 0 32

8-bit registers 20 34

16-bit registers 4 2

Stack size 64kB 128B

Internal ROM 0 4kBInternal RAM 0 128B

External

Memory

64kB 128kB

Flags 6 4

Timer 0 2

Parallel ports 0 4

Serial ports 0 1

The main disadvantage of microcontrollers is less number of instruction sets, but

can be overcome by writing programs by high level programming languages.


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Types of microcontrollers:

1. 4-bit microcontrollers

Typically used for home appliances and toys


Simple applications to high speed machine control

Different families for each type


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More computational and complex control applications

4. 32-bit microcontrollers Applications like Robots, high intelligent instruments, avionics, image

processing, etc.

Some features of Intels 80960 microcontrollers are:

5. Embedded Processors

Microcontrollers are inadequate for complicated tasks, can be overcome by

embedded processors

RISC and CISC processors

High end processors

Integrating more functions into the chip, Instruction Set Architecture (ISA) model

Some processors:

1. Intels X86 processors

2. Macintosh Power PC 604,603, 620 etc.


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Criteria for choosing microcontroller:

1. Speed; highest speed

2. Packaging; DIP or QFP etc.

3. Power consumption; for battery powered products

4. On chip ROM and RAM size

5. Number of IO pins and timer on the chip

6. Easiness to upgrade to higher performance or lower-power consumption

7. Cost/unit

8. Availability of development tools like assembler, compiler, debugger,

emulator, etc.

9. Availability of microcontroller

Some companies which producing 8051 family microcontroller:

1. Intel (www.intel.com/design/mcs51)

2. Atmel (www.atmel.com)3. Philips/Signetics (www.semiconductors.philips.com)

4. Dallas Semi/Maxim (www. Maxim-ic.com)

Overview of 8051 Family Microcontrollers

On-board features:

128 bytes of RAM

4k bytes of ROM

Two 16-bit timers

Four 8-bit IO ports

One serial port Six interrupt sources

Many versions for 8051, with different speed and amount of on-chip ROM

Core 8051 in Intels MCS-51

Other members of 8051 families are:

8031, 8052 and 8032

The difference between these microcontrollers are:


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Other versions based on ROM types are:

Intels 8751 has 4kB on-chip UV-EPROM; require more time to program

Atmels AT89C51 has on-chip flash ROM; faster than UV type

Dallas DS89C4x0 has on-chip NV-RAM; much faster

Architecture of 8051 Microcontroller


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The on-chip features of MCS-51 core architecture are:

8-bit CPU with registers Acc. (A) and B

16-bit program counter (PC) and data pointer (DPTR)

8-bit program status word (PSW)

8-bit stack pointer (SP)

ROM/EPROM/UV-ROM/Flash/NV-RAM of 4k byte

RAM of 128 byte

Four register banks, each containing eight registers

16 byte bit-addressable registers

80 byte general purpose data memory (Scratch pad)

32 IO lines arranged as four 8-bit ports P0-P3

Two 16-bit timers/counters T0 and T1

Full duplex serial data transmitter/receiver SBUF

Control registers TCON,TMOD, SCON, PCON, IP and IE Two external and five internal interrupt sources

8051 pin out details:

Functions of pins:

1. Port 0 pins P0.0 to P0.7:


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Dual purpose pins

One function is general purpose IO port

Other function is lower byte of external memory address bus is multiplexed with

data bus (AD0 to AD7) and can be de-multiplexed by ALE signal

Open drain ports


Dedicated IO port

. 3. Port 2 pins P2.0 to P2.7:

Dual purpose pins


Other function is higher byte external memory address bus (A8 to A15)


Dual purpose pins


Alternate functions are:

RxD Receive data for serial port

TxD Transmit data from serial port

- External interrupt 0

- External interrupt 1

T0 Timer/counter 0 external input

T1 Timer/counter 1 external input

- External data memory write strobe - External data memory read strobe

5.

Program Store Enable

Dedicated control signal

To enable external program memory, usually connected to Output Enable (OE)

pin of external EPROM

During fetch state this signal becomes low and the binary opcodes (programs) are

read from external EPROM

During the execution of a program from internal ROM, this pins remains high

6.

ALE is used to de-multiplex address and data bus of port 0 during external

memory operation. The ALE signal pulses 1/6th of on-chip oscillator frequency


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and can be used general purpose clock for the rest of the system, but an exception

is, one ALE pulse will miss during execution of external memory access

instruction

The same pin can be used for programming input pulse for internal EPROM

7.

External Access

If high (+5V) 8051/8052 executes program from internal ROM from 0 to 4k/8k

byte of memory

If low (0V) microcontroller executes program from external memory only and

pulses low accordingly

For 8031/8032 this pin must be tied low

The pin is also served as programming voltage (Vpp) for internal EPROM

For flash Vpp is +12V

For EPROM Vpp is +21V

8. RST

Master reset

When this pin is high for 2 machine cycles, 8051 internal registers are loaded with

appropriate values for an orderly system start-up

Some register values are:

PC = 0000H

SP = 07H

DPTR = 0000H

A = 00H

B = 00H

PSW = 00H

P0 = FFH

P1 = FFH

P2 = FFH

P3 = FFH


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Two type of circuits can be used for reset:

1. Power-on-reset circuit

2. Power-on-reset with de-bounce

9. XTAL1 and XTAL2

On-chip oscillator inputs

Typically connected to driven by a crystal (stable, but costly) or ceramic

resonators (poor stability, but economic).


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Typical circuit:

Where C1 and C2 are stabilizing capacitors and C1 = C2 = 30pF 10pF for crystals or

40pF 10pF for ceramic resonators

External clock driving also possible and circuit diagram is shown below:

The pulse train produced internally by the oscillator circuit is:

State is the basic time period for microcontroller for discrete operations like

fetching, decoding, executing, etc. One state form two pulse periods.

To complete most operations, microcontroller require at least six states and is

referred as one machine cycle

ALE signal is also shown above

Typical frequency range 0 to 24MHz

Practical frequency range is 1MHz to 24MHz; since some internal registers are

dynamic and causes data loses at low frequencies

8051 Memory organization


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Internally two memories; 128 byte RAM as data memory and 4k byte

ROM as program/code memory

Internal RAM

128 byte internal RAM is organized as three groups:

1. A total of 32 bytes of working registers from address 00H to 1FH

and are set aside for four register banks and the stack

2. A total of 16 bytes bit-addressable locations from address 20H to

2FH and the address range of bit area are 00H to 7FH

3. A total of 80 bytes general purpose area from 30H to 7FH can be

used for read/write operation and is also referred as scratch pad.

One bank can be used at a time and can be switched between each using

PSW

Bank 0 is default register bank and default stack memory starts from

Bank 1

Internal ROM


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8051 has on-chip 4k byte ROM to hold program (code) and is organized

with address 0000H to 0FFFH

PC of 8051 hold 16 bit data, then the addressing capacity is 64k byte. So if

the address is more than 4k byte, microcontroller access external code

memory by enabling

8051 Registers

The 8051 registers are classified into general purpose and special function

registers (SFRs)

32 general purpose registers (working registers)

32 byte registers (00H to 1FH) arranged as 4 banks of internal RAM.

Other locations can be used as direct address registers (20H to 7FH)

Special Function Registers (SFR)

Three categories: a) For data manipulation b) Memory pointer c) Control

registers


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List of all SFRs are:

The functions and RAM address of SFRs are:

Accumulator (A) register hold one operand as well as result during

mathematical operations in CPU and also used to transfer data between

8051 and external memory. It is 8-bit bit-addressable register

B register is used to hold one operand and result during multiplication and

division operation


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Along with working registers these registers are used for data

manipulation.

8051 IO ports

24 IO lines grouped into four 8-bit ports

Each port has D-type output latch and the SFR for each port is made up of

these latches

Each port has separate buffers and can be used to read the status of port

The voltage and power requirements for the port lines are:

The port pin circuits are:

Port 0.X pins-


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Port 1.X pins-

Port 2.X pins-

Port 3.X pins-


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Port 0:

Dual function: IO lines and bidirectional data bus and lower order address bus for

external memory

To use as input line, a 1 must write to corresponding port 0 latch to turn off two

output transistors, which provide high impedance state to pin

To use as output line, a 0 logic will appear due to the on state of lower

transistor. But for logic 1 external pull-up resistor is required

Control logic turn on/off output transistors according to external memory access

Port 1:

Dedicated IO lines with internal FET pull up , hence faster than port 0 pins

Input and output operations are similar to port 0

Port 2:

Dual function: IO lines and higher order address bus for external memory

For input operation no need to write 1 to latch Output operation is similar to other ports

Have internal FET pull up

Port 3:

Dual function: IO lines and other functions are:

IO operation is similar to port 2


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External Memory connection with 8051:

Data memory and code memory can improved up to 64k bytes, since PC and

DPTR are 16 bit

External memory connection with 8051/8031 is:

Timing diagram:


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Possible to connect 64k byte ROM and 64k byte RAM

ROM is enabled by PSEN signal and RAM is accessed by RD and WR signal

The multiplexed address and data bus in port 0 is de-multiplexed by latch using

ALE signal

EA pin should be low for 8031/8051 for external memory access

In 8051, if PC content is more than 4k byte PSEN signal becomes low and

microcontroller access external memory automatically even if EA pin is high.

Addressing modes in 8051:

The way in which the operands are specified in instructions

Five types:

1. Immediate addressing mode

2. Register addressing mode

3. Direct addressing mode

4. Register Indirect addressing mode5. Indexing addressing mode

Examples. ADD A,#06H

MOV R0,#FFH

Examples: ADD A,R0

MOV A,R7


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Examples: ADD A,30H

MOV 00,07

Examples: MOV A,@R1

ADD A,@R0

INC @R1

MOVX A,@DPTR

Example: MOVC A,@A+DPTR


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Instruction Sets:

Around 40 instructions and its variants

Alphabetical List of Instructions

1. ACALL - Absolute Call

2. ADD, ADDC - Add Accumulator (With Carry)3. AJMP - Absolute Jump4. ANL - Bitwise AND5. CJNE - Compare and Jump if Not Equal6. CLR- Clear Register7. CPL - Complement Register8. DA - Decimal Adjust9. DEC - Decrement Register10. DIV - Divide Accumulator by B11. DJNZ - Decrement Register and Jump if Not Zero12. INC - Increment Register

13. JB - Jump if Bit Set14. JBC - Jump if Bit Set and Clear Bit15. JC - Jump if Carry Set16. JMP - Jump to Address17. JNB - Jump if Bit Not Set18. JNC - Jump if Carry Not Set19. JNZ - Jump if Accumulator Not Zero20. JZ - Jump if Accumulator Zero21. LCALL - Long Call22. LJMP - Long Jump23. MOV - Move Memory

24. MOVC - Move Code Memory25. MOVX - Move Extended Memory26. MUL - Multiply Accumulator by B27. NOP - No Operation28. ORL - Bitwise OR29. POP - Pop Value From Stack30. PUSH - Push Value Onto Stack31. RET - Return From Subroutine32. RETI - Return From Interrupt33. RL - Rotate Accumulator Left34. RLC - Rotate Accumulator Left Through Carry

35. RR- Rotate Accumulator Right36. RRC - Rotate Accumulator Right Through Carry37. SETB - Set Bit38. SJMP - Short Jump39. SUBB - Subtract From Accumulator With Borrow40. SWAP - Swap Accumulator Nibbles41. XCH - Exchange Bytes

http://www.win.tue.nl/~aeb/comp/8051/set8051.html#51acallhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51addhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51ajmphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51anlhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51cjnehttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51clrhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51cplhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51dahttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51dechttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51divhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51djnzhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51inchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jbhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jbchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jmphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jnbhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jnchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jnzhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jzhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51lcallhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51ljmphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51movhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51movchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51movxhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51mulhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51nophttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51orlhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51pophttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51pushhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rethttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51retihttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rlhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rlchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rrhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rrchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51setbhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51sjmphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51subbhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51swaphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51xchhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51acallhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51addhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51ajmphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51anlhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51cjnehttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51clrhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51cplhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51dahttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51dechttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51divhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51djnzhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51inchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jbhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jbchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jmphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jnbhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jnchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jnzhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51jzhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51lcallhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51ljmphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51movhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51movchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51movxhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51mulhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51nophttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51orlhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51pophttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51pushhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rethttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51retihttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rlhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rlchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rrhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51rrchttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51setbhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51sjmphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51subbhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51swaphttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51xch

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42. XCHD - Exchange Digits43. XRL - Bitwise Exclusive OR

Different types:

1. Arithmetic instructions2. Logical instructions

3. Data transfer instructions

4. Bit oriented instructions

5. Program branching instructions

Arithmetic instructions:

1. ADD A, source

A = A + source, source may be immediate, direct, register or register

indirect address operand. CY, OV and AC flags affect.

Examples: ADD A,#90H

ADD A,R7

ADD A,37H

ADD A,@R1

2. ADDC A, source

A = A + CY + source, similar to ADD instruction, but carry flag status

will added to the result. CY, OV and AC flags affect.

3. DA A

Decimal adjust for addition, it adjust A content to BCD after ADD or

ADDC operation. Only CY flag affect.Example: ADD A,R0

DA A

4. SUBB A, source

A = A CY source, source may be immediate, direct, register or register

indirect address operand. CY, OV and AC flags affect.

Examples: SUBB A,#90H

http://www.win.tue.nl/~aeb/comp/8051/set8051.html#51xchdhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51xrlhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51xchdhttp://www.win.tue.nl/~aeb/comp/8051/set8051.html#51xrl

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SUBB A,R7

SUBB A,37H

SUBB A,@R1

5. MUL AB

Byte x byte multiplication, perform A x B and place 16-bit result to B and

A register (Lower byte to A and upper byte to B). OV flag affect.

6. DIV AB

Byte over byte division, perform A (numerator) by B (denominator) and

place the results to A and B (Quotient to A and reminder to B). OV flag affect.

7. INC destination

Destination = destination + 1

Destination may be A, direct address, any register or indirect register

address.

Examples: INC AINC @R0

INC 80H

INC DPTR

8. DEC destination

Destination = destination 1

Addressing is similar to INC

Logical instructions:

1. ANL destination, source

destination = destination AND source, source may be immediate, direct,

register or register indirect address operand and destination may be A or directExamples: ANL A,#90H

ANL A,R7

ANL A,37H

ANL A,@R1

2. ORL A, source

A = A OR source, source is similar to ANL

3. XRL A, source

A = A XOR source, source is similar to ANL


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4. CPL A

A = NOT A

5. CLR A

A= 0

6. RL A

Rotate A content to left, MSB becomes LSB

7. RLC A

Rotate A content to left through CY, CY becomes LSB and MSB becomes

CY

8. RR A

Rotate A content to right, LSB becomes MSB

9. RRC A

Rotate A content to right through CY, LSB becomes CY and CY becomes

MSB10. SWAP A

Swaps nibbles within A

Data transfer instructions:

1. MOV destination, source

Destination = source

Destination may be A, B, DPTR, any register, direct address of internal

RAM or indirect register address. Source may be A, B, any register, direct address,

immediate data or indirect register address (if destination is not indirect address)

Examples: MOV A,#40H

MOV R3,#90MOV R0,@R1

MOV 30H,B

MOV R0,3F

2. MOVX destination, source


Destination may be A or indirect external data memory or in DPTR or any

register. Source may A or indirect external data memory address in DPTR or any register

Examples: MOVX @DPTR, A

MOVX A,@DPTR

MOVX @R0,A

MOVX A,@R1

3. MOVC destination, source


Destination is A and source indexed address of code memory generated by

A + DPTR or A+PC


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Examples: MOVC A,@A+DPTR

MOVC A,@A+PC

4. PUSH direct

Move the content in direct internal RAM address to stack, where address

defined in SP

Example: PUSH E0H

5. POP direct

Move the content from stack to direct internal RAM address, where

address defined in SP

Example: POP E0H

6. XCH A, source

Exchange A with source. Source may be any register, direct address or

indirect address

Examples: XCH A,R0XCH A,80H

XCH A,@R0

7. XCHD A, source

Exchange lower nibble of A with indirect address RAM content

Example: XCHD A,@R0

Bit oriented instructions:

1. CLR C

Clears the carry flag

2. CLR bit

Clears the direct bitExamples: CLR ACC.0

CLR EA

CLR 00

3. SETB C

Sets the carry flag

4. SETB bit

Sets the direct bit

Examples: SETB ACC.0

SETB EA

SETB 00

5. CPL C

Complements the carry flag

6. CPL bit

Complements the direct bit


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Examples: CPL ACC.0

CPL EA

CPL 00

7. ANL C, bit

AND direct bit to the carry flag

Examples: ANL C,PSW.0

ANL C,01

8. ANL C,/bit

AND complements of direct bit to the carry flag

Examples: ANL C,/PSW.0

ANL C,/01

9. ORL C,bit

OR direct bit to the carry flag

Examples: ORL C,ACC.010.ORL C,/bit

OR complements of direct bit to the carry flag

Example: ORL C,/00

11. MOV C,bit

Moves the direct bit to the carry flag

Example: MOV C,00

12. MOV bit,C

Moves the carry flag to the direct bit

Example: MOV 02,C

Program branching instructions:Different types:

Branching instructions replace the content of the PC with a new program address

causes program execution from a new location.

The difference of the new address from the current address in PC is called rangeand there tree types of ranges for branching instructions:

1. Relative range: +127 to -128 bytes from the instruction following

the branch instruction

2. Short Absolute range: Same of 2k byte from the instruction

following the branch instruction


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Long absolute range

Acquire more bytes of code than other types; from 0000H to FFFFH and is its

advantage

The disadvantage is the program must be re-assembled every time and the

branching instructions are re-locatable

Jump instructions:

1. Conditional jump instructions

a) Bit jump instructions

b) Byte jump instructions

2. Unconditional jump instructions

Conditional jump instructions:

a) Bit jumps

Operates according to the status of the CY flag in PSW or any bit-addressable location

Instructions:

Where radd is relative address and is generated by:

radd = target address current address, if target address is more than

current address, radd is positive ranges from 01H to 7FH . If target is less than current

address, radd is negative ranges from 80H to FFH and is in 2s complement from


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Call and subroutine instructions:

Subroutine is the program that may used several times in the execution of a large

program

It can be written into body of main program everywhere it is needed

Instructions:

Interrupt and returns:

Interrupt causes a hardware generated call

Interrupt subroutine addresses are:

Instruction to return from interrupt call:

Assembly language programming:

Programming by mnemonics: codes and abbreviations easily to remember.

Eg: ADD , MOV, JMP etc..

Assembler translates assembly language to opcode (machine code or operation code)

Eg: ADD A, R0 has opcode 28 Assembly languages are low level languages deals with structure of CPU; knowledge of

internal architecture is must

C, C++, BASIC etc are high level language; no need to have the knowledge of internal

structure of CPU

Compiler translates high level language to opcodes

Structure of 8051 ASSEMBLY LANGUAGE


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Series of lines

Consists mnemonics (instructions) followed by one or two operands

Have directives (pseudo instructions) to give the directions to assembler

Eg: ORG 100H - To direct assembler to the starting address of program

memory

END To direct assembler to the end of program

EQU To define a constant

eg: N EQU F0H

.

MOV R0,#N ; R0 F0H

DB To define data byte in ROM

eg: ORG 0100H

Data1: DB 01 ;Decimal

Data2: DB 01011111B ;BinaryData2: DB F0H ;Hexa decimal

Data4: DB VKCET ;ASCII

Has four fields:

Eg: MAIN: MOV DPTR,#4500H ;Point external memory

Steps to create program

Where,

.asm is source file

.lst is list file


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.obj object file

.abs absolute object file

.hex hex file (for 8051 Intel hex file format)

Q: Write an ALP to generate a square wave of 1 kHz at P0.0 if P0.1 is at logical high and change

the duty cycle of the signal to 75% if P0.1 is low? Assume that the crystal frequency is 12MHz.

Circuit diagram:

XTAL218

XTAL119

ALE30

EA31

PSEN29

RST9

P0.0/AD039

P0.1/AD138

P0.2/AD237

P0.3/AD336

P0.4/AD435

P0.5/AD5 34

P0.6/AD633

P0.7/AD732

P2.7/A1528

P2.0/A821

P2.1/A922

P2.2/A1023

P2.3/A1124

P2.4/A1225

P2.5/A1326

P2.6/A1427

P1.01

P1.12

P1.23

P1.34

P1.45

P1.56

P1.67

P1.78

P3.0/RXD10

P3.1/TXD11

P3.2/INT012

P3.3/INT113

P3.4/T014

P3.7/RD17

P3.6/WR16

P3.5/T115

U1

80C51

X1CRYSTAL

C1

33nF

C2

33nF

C310uF

Vcc

R18.2k

RESET

Output

R210k

Vcc

R310k

INPUT


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Flowchart:

Assembly language program:

To wait during execution either software delay or hardware delay is required. Hardware

delay is provided by timer/counter module. At this level software delay can be used and design

for standard delay may be 100us, 1ms, 1s etc In the given program all delay are multiples of

250us, so a 250us delay is suitable.

Consider a subroutine:

delay_us: MOV R0,#N ;1 MC (machine cycle) execution time

loop: DJNZ R0,loop ;2 MC x N execution time

RET ;2 MC execution time

For the above instructions total time for execution is Texecution = 3MC +(2N)MC

If clock frequency is 12MHz, one clock period is T = 1/12M sec and 1MC = 12T = 1us

Then Texecution = (3 + 2N)us.

If Texecution = 250us, N = 123.5

To get accurate output N value should be an integer, the add a NOP instruction to the

code;


Start

Clear pin P0.0

Set P0.1 as input pin

Read P0.1

If P0.1 = 1?No

Yes

Set P0.0 as 1

Wait 0.5ms

Clear P0.0

Wait 0.5ms

Set P0.0 as 1

Wait 0.75ms

Clear P0.0

Wait 0.25ms

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New code:

delay_us: MOV R0,#N ;1 MC (machine cycle)

loop: DJNZ R0,loop ;2 MC x N

NOP ;1 MC

RET ;2 MC

Then Texecution = (4 + 2N)us.

For Texecution = 250us, N= 123 = 7BH

Calling this routine causes a software delay; killing the time:

Final program:

ORG 0

MAIN: CLR P0.0

SETB P0.1REPEAT: MOV C,P0.1

JNC SEVENTYFIVE

SETB P0.0

LCALL delay_us

LCALL delay_us

CLR P0.0

LCALL delay_us

LCALL delay_us

SJMP REPEAT

SEVENTYFIVE: SETB P0.0LCALL delay_us

LCALL delay_us

LCALL delay_us

CLR P0.0

LCALL delay_us

SJMP REPEAT

delay_us: MOV R0,#7BH ; Count value for 250us

loop: DJNZ R0,loop

NOP

RET

END


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Introduction to C programming in 8051:

Assembly language programming is tedious and time consuming, but the hex file

produced has less size

C programming is less time consuming and easier to write, but the hex file produced is

larger than that of using assembly language

Some advantages of C programming in 8051 are:

1) Easier to modify and update

2) Availability of codes for function libraries

3) Code is portable to other microcontrollers with little or no modification

Some data types for C programming used for 8051 are:

1) Unsigned character (unsigned char)

2) Signed character (signed char or char)

3) Unsigned integer (unsigned int)

4) Signed integer (signed int or int)5) SFR (sfr)

6) Single bit (sbit)

7) Bit (bit)

C program for the previous example:

#include //Header file for generic 8051 registers

void us_delay(void); //Subroutine for 250us delay

sbit out = P0^0; //Output variable assigned on pin P0.0

sbit in = P0^1; //Input variable assigned on pin P0.1

void main() //Main program

{

out = 0; //Clear output

in = 1; //Set PP0.1 as input

while(1) //Infinite loop

{

CY = in; //Read input

if(CY == 1)

{

out = 1;us_delay(); //250us delay

us_delay();

out = 0;

us_delay();

us_delay();

}


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else

{

out = 1;

us_delay();

us_delay();

us_delay();

out = 0;

us_delay();

}

}

}

void us_delay(void)

{int i;

for(i=0;i

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Idle/Sleep mode:

Core CPU is put to sleep while all on-chip peripherals remains active and continue to

function

Oscillator continue to provide clock to peripherals, but no clock to CPU

All the contents of the registers and on-chip RAM remain unchanged

Terminated either by any enabled interrupt or hardware reset

When idle is terminated by a hardware reset, the device normally resumes program

execution, from where it left off, up to two machine cycles before the internal reset

algorithm takes control. On-chip hardware inhibits access to internal RAM in this event,

but access to the port pins is not inhibited. To eliminate the possibility of an unexpected

write to a port pin when Idle is terminated by reset, the instruction following the one that

invokes Idle should not be one that writes to a port pin or to external memory.

Power down mode:

On-chip oscillator is stopped and cuts off frequency to CPU and all peripherals Reduce the power consumption to absolute minimum

The on-chip RAM and SFR contents are saved and unchanged


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Watch dog timer

A watchdog timer is a piece of hardware that can be used to automatically detect software

anomalies and reset the processor if any occur

Generally speaking, a watchdog timer is based on a counter that counts down from some

initial value to zero.

The embedded software selects the counter's initial value and periodically restarts it. If

the counter ever reaches zero before the software restarts it, the software is presumed to

be malfunctioning and the processor's reset signal is asserted. The processor (and the

software it's running) will be restarted as if a human operator had cycled the power.

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08.601 MBSD Module 1