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4
Inverter Timing Diagram
Figure 3--2 Inverter operation with a pulse input.
Figure 3--6 The inverter complements an input variable.
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AND Gate Truth Table
Figure 3--14 Boolean expressions for AND gates with two, three, and four inputs.
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AND Gate Timing Diagram
Figure 3--10 Example of pulsed AND gate operation with a timing diagram showing input and output relationships.
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Figure 3--15 An AND gate performing an enable/inhibit function for a frequency counter.
AND Gate Application Example
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OR Gate Truth Table
Figure 3--23 Boolean expressions for OR gates with two, three, and four inputs.
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OR Gate Timing Diagram
Figure 3--19 Example of pulsed OR gate operation with a timing diagram showing input and output time relationships.
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OR Gate Application Example
Figure 3--24 A simplified intrusion detection system using an OR gate.
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Fixed-Function Logic : IC Gates
• CMOS (Complementary Metal-Oxide Semiconductor)
• TTL (Transistor-Transistor Logic)
• CMOS – lower power dissipation
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Figure 3--49 Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin numbers and basic dimensions.
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Figure 3--51 Logic symbols for hex inverter (04 suffix) and quad 2-input NAND (00 suffix). The symbol applies to the same device in any CMOS or TTL series.
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Performance Characteristics and Parameters
• Propagation delay Time
• DC Supply Voltage (VCC)
• Power Dissipation
• Input and Output Logic Levels
• Speed-Power product
• Fan-Out and Loading
42Figure 3--53 The LS TTL NAND gate output fans out to a maximum of 20 LS TTL gate inputs.
Higher fan-out = gate can be connected to more gate inputs.
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Programmable Logic• Programmable Arrays
Figure 3--65 An example of a basic programmable OR array.