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Hardware/Software Co-Hardware/Software Co-Design Final ProjectDesign Final Project

Emulation on Distributed Emulation on Distributed SimulationSimulation

Co-Verification SystemCo-Verification System

陳少傑 教授陳少傑 教授R91921081 R91921081 黃鼎鈞黃鼎鈞R91943004 R91943004 尤建智尤建智R91921089 R91921089 林語亭林語亭

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AgendaAgenda

1. Introduction of verification 1. Introduction of verification 2. Simulation / Emulation 2. Simulation / Emulation 3. Principle of co-verification3. Principle of co-verification 4. System Architecture4. System Architecture 5. Experiment Result 5. Experiment Result 6. Conclusion6. Conclusion 7. Reference7. Reference

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Introduction of Introduction of verificationverification

Check if a design correctly Check if a design correctly implements specified behavior implements specified behavior (usually done before manufacture)(usually done before manufacture)

ClassesClasses Logic design verificationLogic design verification simulationsimulation emulationemulation formal verificationformal verification Physical design verificationPhysical design verification

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Challenge in SOC EraChallenge in SOC Era

The complexity and gate count sky-rocket The complexity and gate count sky-rocket base on Moore Lawbase on Moore Law

The chip includes multi-modules( IP ), and The chip includes multi-modules( IP ), and mixed signal blocksmixed signal blocks

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Design and Verification Design and Verification ProcessProcess

Design: writing design specification and start

design cycle

Implement: Implement and refine

the design through all phases

Verify:Verify the

Correctness ofdesign

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The Verification The Verification BottleneckBottleneck

Verification problem grows even faster due to the combination of increased gate count and increased vector count

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Approaches to Design Approaches to Design VerificationVerification

Software Simulation─ traditional software-based simulation

Hardware Accelerated Simulation─ use special purpose hardware to

accelerate simulation of circuit

Emulation─ Emulation actual circuit behavior

Rapid Prototyping─ Create a prototype of actual hardware

Formal Verification─ formal method

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Simulation / Emulation Simulation / Emulation VerificationVerification

Software Simulation:Software Simulation: With very high With very high flexibility high extension and more flexibility high extension and more cheaper than emulationcheaper than emulation

----Verilog, VHDL, C/C++, mixed ----Verilog, VHDL, C/C++, mixed languagelanguage

Hardware Emulation:Hardware Emulation: With very With very high speed for processing timehigh speed for processing time

-----PFGA, special hardware-----PFGA, special hardware

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Industrial Verification Industrial Verification IssuesIssues

Intel: Processor project verification:“Billions of generated vectors”“Our VHDL regression tests take 27 days to run. ”

Sun: Sparc project verification:Test suite ~1500 tests > 1 billion random simulation cycles“A server ranch ~1200 SPARC CPUs”

Bull: Simulation including PwrPC 604“Our simulations run at between 1-20 CPS.”“We need 100-1000 cps.”

Cyrix : An x86 related project“We need 50x Chronologic performance today.”“170 CPUs running simulations continuously”

Kodak: “hundreds of 3-4 hour RTL functional simulations”Xerox: “Simulation runtime occupies ~3 weeks of a design cycle”Ross: 125 Million Vector Regression tests

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Software Verification Software Verification MechanismMechanism

Design Under Test

Test Patterns

Simulation EngineMonitor or Rule Check

Library

Specific outputs

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System/Abstract level System/Abstract level simulationsimulation

Easily debug and diagnosis Easily debug and diagnosis Reduce simulation timeReduce simulation time 1. Saving data structure transfer time1. Saving data structure transfer time 2. Native code predominance2. Native code predominance Much more memory function Much more memory function

HDL HDL HDL

HDL C/C++Simulation

Engine

Perl

HDL

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Emulation SystemEmulation System Advantages:

+ easiest to implement (involves little change to the simulation environment)+ 10X to 100X faster than traditional simulation

Disadvantages:--All module must be synthesized --Difficult to handle verification scripts or mathematical formulas--Can’t probe any signal --Can’t probe any signal we want (only on we want (only on input/output)input/output)

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SW/HW Co-VerificationSW/HW Co-Verification

Dedicatedhardware

Softwaresimulator

Synthesizable DUT and transactor

High-level protocol for Communication via network or system bus

DUTTest Bench

Design

transactor

Transaction-level HDL or C/C++ test bench

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Principle of co-Principle of co-verificationverification

How to design an hardware / How to design an hardware / software co-verification system ?software co-verification system ?

----The key issue is ----The key issue is

PARTITIONPARTITION

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Partition constraint on Partition constraint on hardware parthardware part

Maximum gate-count of FPGA or emulatorMaximum gate-count of FPGA or emulator Maximum number of input and output Maximum number of input and output

portsports Maximum number of registers in FPGA or Maximum number of registers in FPGA or

emulatoremulator Gate-count balance among emulatorsGate-count balance among emulators Delay for critical path in emulatorDelay for critical path in emulator Monitored signal is suitable in hardwareMonitored signal is suitable in hardware

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Partition constraint on Partition constraint on software partsoftware part

Communication overhead among Communication overhead among simulators and emulators simulators and emulators

Monitored signal is suitable in hardwareMonitored signal is suitable in hardware Tight clock policy or loose clock policy Tight clock policy or loose clock policy

(multi-clock system)(multi-clock system)

ALL of these are test patterns ALL of these are test patterns related factorsrelated factors

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Partition process flowPartition process flow--Dynamic process--Dynamic process

HDL file

Test Patterns

Partition Engine

Hardware constraintSoftware constraint

Emulator

Simulator

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Incentives of the ProjectIncentives of the Project

Provide earlier verification in IC Provide earlier verification in IC design processdesign process

Co-verification among different level Co-verification among different level descriptiondescription PhysicalPhysical Register Transfer Level Register Transfer Level BehaviorBehavior

Accelerates verificationAccelerates verification

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Our GoalOur Goal

VerilogVHDL

C PartitionManual/Automatic

Simulate 1

Simulate 2

Emulate 1

Emulate 2

Co-verification

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System Architecture (I)System Architecture (I)

Distributed SimulationDistributed Simulation

Master

Child I Child III

Child II

TCP/IP port communication

TCP/IP port

TCP/IP port

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Features of the Features of the SimulatorSimulator

A master process A master process must be setup to manipulate must be setup to manipulate

communicationcommunication Several child processesSeveral child processes

Each corresponds to one partEach corresponds to one part CommunicationCommunication

TCP/IP portsTCP/IP ports

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Potential Difficulties (I)Potential Difficulties (I)

Distributed SimulationDistributed Simulation SynchronizationSynchronization

Different simulating speeds among partsDifferent simulating speeds among parts The faster have to waitThe faster have to wait

Data communicationData communication Communication overheadCommunication overhead

PartitionPartition Clocks are the bottleneckClocks are the bottleneck

Duplicate global clocks within each parts Duplicate global clocks within each parts speedup simulationspeedup simulation

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System Architecture (II)System Architecture (II)

EmulationEmulation

MasterSimulation

Child ISimulation

Child IIISimulation

Child II

TCP/IP port

TCP/IP port

TCP/IP port

FPGAEmulation

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Features of the EmulatorFeatures of the Emulator

Must be child processesMust be child processes Each corresponds to one part Each corresponds to one part

synthesized as EDIFsynthesized as EDIF Under the control of a Under the control of a

corresponding child simulationcorresponding child simulation CommunicationCommunication

Through IDE to its corresponding Through IDE to its corresponding simulation processsimulation process

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Potential Difficulties (II)Potential Difficulties (II)

EmulationEmulation SynchronizationSynchronization

Among FPGA’s and SimulatorAmong FPGA’s and Simulator Clock Signals must be handled by SimulatorClock Signals must be handled by Simulator

Among different FPGA’sAmong different FPGA’s Simulator synchronize the verification Simulator synchronize the verification

progressionprogression

Data communicationData communication Must be manipulated by the simulatorMust be manipulated by the simulator

Multiple clocksMultiple clocks Handled by SimulatorHandled by Simulator

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Potential Difficulties (III)Potential Difficulties (III)

Design PartitionDesign Partition Manual / AutomaticManual / Automatic

Emulation parts must be synthesizableEmulation parts must be synthesizable Hardware constrains Hardware constrains

Communication overheadCommunication overhead Among different emulation partsAmong different emulation parts Among different simulation partsAmong different simulation parts

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System LimitationSystem Limitation

EmulationEmulation Clocks are handled by Simulator, Clocks are handled by Simulator,

emulation can progress one clock cycle emulation can progress one clock cycle at each call.at each call.

FPGAs works interruptedly instead at FPGAs works interruptedly instead at their full speeds.their full speeds.

Partition among emulation parts may Partition among emulation parts may dominate communication overhead.dominate communication overhead.

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Experiment ResultsExperiment Results

RTL module : Jazz2020 (DSP core)RTL module : Jazz2020 (DSP core) Gate Count : 0.5M (estimated)Gate Count : 0.5M (estimated) Number of test patterns : 374 (with Number of test patterns : 374 (with

verification function)verification function) Purely software simulation : 183 secPurely software simulation : 183 sec Co-simulation (with Xilinx Vertex 400E) Co-simulation (with Xilinx Vertex 400E)

: 94 sec: 94 sec Speed up : 2x (almost) Speed up : 2x (almost) Not fast as we Not fast as we

expectexpect

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Future workFuture work

We will separate RTL code into We will separate RTL code into nonsynthesizable part and synthesizable nonsynthesizable part and synthesizable partpart

Nonsynthesizable Part : Convert to C Nonsynthesizable Part : Convert to C code (compiled code type) run under code (compiled code type) run under embedded CPU on FPGA chipembedded CPU on FPGA chip

Synthesizable Part : put into FPGA blockSynthesizable Part : put into FPGA block GoalGoal : : All process will be done only All process will be done only

on one FPGA chipon one FPGA chip

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Future WorkFuture Work

OriginalRTL code

C Code

non-synthesizable

RTL Gate Level

code

Embedded CPU compiler

FPGA synthesizer

Embedded CPU

Embedded CPU

Compiledcode

netlist

FPGA Block

FPGA main board

PartitionEngine

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ConclusionConclusion

Simulation is and will be the most Simulation is and will be the most popular verification method.popular verification method.

Emulation will standout as an Emulation will standout as an accelerator under heavy simulation accelerator under heavy simulation load.load.