1 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication P. Zeitzoff Contributors: J. Hutchby, P. Fang, G. Bourianoff, J. Chung, Y. Hokari, J

1 PIDS

7/1/01 18 July 2001 Work In Progress – Not for Publication

P. Zeitzoff

Contributors: J. Hutchby, P. Fang, G. Bourianoff, J. Chung, Y. Hokari, J. Bruines, S. C. Sun, H. Bennett, T. Dellin, D. G. Kang, K. Shibahara, M. Yoshimi

International Technology Working Group MeetingSan Francisco, CA

7/16-7/18/01

PIDS Presentation at Open Meeting

2 PIDS


Outline

• Definition of PIDS• Logic: high performance • Logic: low power• Difficult challenges• Emerging research devices• Summary

– Reliability, Memory, and Mixed Signal here only: time constraints

3 PIDS


PIDS Definition & Scope• PIDS = Process Integration, Devices, and Structures• Deals with

– Full process flows and process integration – Design and optimization of active and passive devices for electrical

performance– Reliability– Physical and electrical design rules

• Interacts with all TWG’s, especially:– FEP– Interconnect– Design– Litho

• Main subsections: logic and memory, mixed signal, reliability, and emerging research devices (new in 2000)

4 PIDS


High Performance Logic (MPU type)• High performance logic driven by requirement of

17% annual improvement in transistor performance– Historic trend– Metric: = CgateVdd/Id

– A spreadsheet used, including analytic, empirical, simplified models

– Compared to ’99 ITRS: scaling redone to extend viability of gate oxide, polysilicon electrode, etc. until ’07

– High k and/or non-classical CMOS needed by 2007• To control short channel effects, reduce leakage, improve Ion

5 PIDS


High Performance Logic Table

•High k not required until ’07

•Vdd & Tox scaling relatively slowly

•Ioff scaling up rapidly

Gate Dielectric Equivalent Oxide Thickness (EOT)

nm 1.4 1.4 1.2 1.0 0.9 0.9 0.8 0.6 0.5 0.4

Revision Date: 7/09/01Calendar Year 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016Technology Node 130nm 90nm 65nm 45nm 32nm 22nmMPU Gate Length nm 65 53 45 37 32 30 25 18 13 9

Near Term Long Term

Relative Gate Dielectric Constant with respect to Oxide

1.0 1.0 1.0 1.1 1.1 1.1 2.0 2.7 3.2 4.0

Id-NMOS (@Vdd) uA/um 926 959 967 954 924 960 1091 1250 1492 1507

Required "Technology Improvement" (SOI/Low-Temp/High-mobility)

0% 0% 0% 0% 0% 0% 10% 30% 70% 100%

Sub-Threshold I-off (@25C)

uA/um 0.01 0.03 0.07 0.1 0.3 0.7 1 3 7 10

Vdd V 1.2 1.2 1.1 1.0 0.9 0.9 0.8 0.6 0.5 0.4

6 PIDS


High Performance Logic Table (con’t.)Calendar Year 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016Technology Node 130nm 90nm 65nm 45nm 32nm 22nmMPU Gate Length nm 65 53 45 37 32 30 25 18 13 9

Id-NMOS (@Vdd) uA/um 926 959 967 954 924 960 1091 1250 1492 1507

Required "Technology Improvement" (SOI/Low-Temp/High-mobility)

0% 0% 0% 0% 0% 0% 10% 30% 70% 100%

Intrinsic Frequency (1/Tau)

GHz 613 746 865 1005 1159 1261 1510 2577 4335 6440

Relative Device Performance

1.0 1.2 1.4 1.6 1.9 2.1 2.5 4.2 7.1 10.5

•1/ improving 17%/year•Id increasing slowly

•Needed to keep 1/ decreasing•Device improvements (high mobility layers, non-classical dual gate CMOS) needed at 2007

7 PIDS


Low Power Logic• Driven by requirement for reduced static and dynamic

power dissipationreduced leakage• Analysis is similar to high performance

– Same transistor performance metric: = CgateVdd/Id

– Same spreadsheet used, including analytical, empirical models

• Two different versions of low power– Low operating power (LOP): for notebook computers, mobile

computingperformance and low power: Ioff=Ig=100 pA/µm– Low standby power (LSTP): for cellular ‘phones super low

power: Ioff=Ig=1 pA/µm

8 PIDS


Low Power Gate Leakage Requirements

0 1 2 3

Gat

e le

akag

e (A

/cm

2)

Physically effective oxide thickness (nm)

1E-10

1E-8

1E-6

1E-4

1E-2

1E 0

Pr2O3

La2O3

SiO2

Al2O3

Al2O3

ZrO2

Ta2O5

HfO2

@Vg=1V

Limit in LOP/ASIC

Limit in MPU

Limit in LSTP/ASIC

1E 2 SiON

TiO2

N/O

VLSI ‘01

VLSI ‘01

9 PIDS


Low Power [L(O)P] Requirements Table

•High k required in 2004 for L(O)P & L(ST)P•Vdd scaling largely stops due to noise margin non-scalability•There is a “wall” after 2007 due to high field effectsinability to keep Vdd high

–Performance improvement: 11%/year ‘til 2007, flat thereafter

Calendar Year 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016Technology Node nm 130 90 65 45 32 22MPU Gate Length nm 65 53 45 37 32 30 25 18 13 9ASIC/LP Gate Length nm 90 80 65 53 45 37 32 30 25 18ASIC/L(O)P EOT nm 2.0 1.8 1.6 1.4 1.2 1.1 1.0 0.8 0.7 0.6MPU Vdd V 1.2 1.2 1.1 1.0 0.9 0.9 0.8 0.6 0.5 0.4ASIC/LP Vdd V 1.2 1.2 1.1 1.1 1.1 1.0 1.0 1.0 0.9 0.9ASIC/L(O)P Max. Ig@25℃ pA/um 100 100 100 100 100 100 100 100 100 100

ASIC/L(O)P Id-NMOS uA/um 550 572 529 562 575 518 604 664 597 616

ASIC/L(O)P Relative DevicePerformance 1.00 1.09 1.21 1.39 1.54 1.66 1.82 1.75 1.64 1.77

10 PIDS


Difficult Challenges (Short Term)Difficult Challenges >= 65nm /

Through 2007Summary of Issues

1. Meeting MOSFET performance and power dissipation requirements for high performance applications.

-Extending life of oxy-nitride/nitride films.-Dynamic power dissipation is increasing rapidly, especially with less aggressive Vdd scaling in the 2001 ITRS.-Leakage and static power dissipation are also increasing rapidly.

2. Implementation into manufacturing of non-classical MOSFET devices.

-Needed to scale device transconductance, control short-channel effects and off-state leakage by 2007.-Timely development, process integration, and qualification.

3. Meeting MOSFET performance and leakage requirements for low power applications.

Early availability of manufacturing-worthy high k gate dielectrics is necessary to meet stringent gate leakage and performace requirements.

4. Ensuring reliability of new materials and structures in a timely manner.

-Accelerated reliability ensurance of high k material for gate stack is needed for early insertion into manufacturing.-Ensuring reliability of new, non-classical MOSFET device structures.

-Ensuring reliabillity for increasing Vdd/Tox with very thin oxy-nitrides-Difficulty of screening with high leakage.

5. Constructing high density nonvolatile, DRAM, and SRAM memories for scaled technologies

-DRAM: Storage capacitor dielectric scaling-SRAMs: lithography and etch issues, as well as process integration-NVM: Scaling of tunneling and inter-poly dielectric.

6. High performance mixed signal solutions for scaled technologies.

-Passive element scaling.-Isolation-Effectiveness of scaled high-performance transistors for RF applications.

11 PIDS


Difficult Challenges (Short Term)

• Meeting MOSFET performance and power dissipation requirements for high performance applications.

• Implementation into manufacturing of non-classical MOSFET devices.

• Meeting MOSFET performance and leakage requirements for low power applications: high k in 2004.

• Ensuring reliability of new materials and structures in a timely manner.

• Constructing high density nonvolatile, DRAM, and SRAM memories for scaled technologies.

• High performance mixed signal solutions for scaled technologies.

12 PIDS


Difficult Challenges (Long Term)

Difficult Challenges < 65nm / Beyond 2007

Summary of Issues

7. Fundamental improvements in MOSFET device effective transconductance needed to maintain device performance scaling trend.

With sharp reductions in Vdd and 17% annual increase in circuit clock speed, basic MOSFET device performance will be inadequate to meet circuit speed requirements.

8. Dealing with statistical process variations and atomic-level fluctuations.

Projected 15% gate length dimensional will have increasing impact on device characteristics.Device resistance/capacitance elements increasingly sensitive to

9. New circuit and device design solutions for achieve dynamic and static low-power requirements.

Constant-leakage device design will not scale beyond 2007 due to power-supply/signal-margin non-scalability.

10. New interconnect schemes-Eventually, copper/low k performances will be inadequate.-Solutions (optical, microwave/RF, etc,) are currently unproven.

11. Implementation of novel, non-CMOS devices and architectures, including interconnect and memory.

Will drive major changes in process, materials, physics, design, etc.Novel devices may coexist with CMOS: integration of the two.

13 PIDS


Difficult Challenges (Long Term)

• Fundamental improvements in MOSFET device effective transconductance needed to maintain device performance scaling trend.

• Dealing with statistical process variations and atomic-level fluctuations.

• New circuit and device design solutions for achieve dynamic and static low-power requirements.

• New interconnect schemes (optical, RF, …).• Implementation of novel, non-CMOS devices and

architectures, including interconnect and memory.

14 PIDS


Emerging Research Devices• Devices beyond classical, bulk CMOS

– Required to meet chip power dissipation and performance requirements for later technology generations

• Presumably, at 2007 (65nm) and beyond• Includes a range of new devices and architectures

– Non-classical CMOS (strained Si MOS, DG-SOI, etc.) – Advanced structures (SET’s, etc.) – New information processing architectures (molecular memory, cellular neural networks,

etc)

– PIDS logic and memory subsection highlights need for innovative devices

– Emerging Research Devices subsection expands on these devices and architectures

• Added to PIDS chapter in 2000, expanded in 2001

15 PIDS


Summary• Logic: Analytical, empirical models used in spreadsheet– High performance: driven by 17%/year performance improvement

• High k, non-classical CMOS needed by 2007– Low power driven by power and leakage requirements

• High k needed in 2004; this drives introduction of high k to product

• Difficult challenges include implementation of high k by 2004 for low power, and in the long-term, dealing with statistical variation and atomic-level fluctuations

• Emerging research devices range from non-classical CMOS in 2007 to advanced, non-CMOS solutions at the end of Roadmap

• Memory, mixed signal, reliability only touched on due to time limitation– Key reliability issue: development and implementation time re: new materials and

structures– Key memory issue: dielectric equivalent thickness, materials– Key mixed signal issue: electrical isolation

Documents

1 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication P. Zeitzoff Contributors: J. Hutchby, P. Fang, G. Bourianoff, J. Chung, Y. Hokari, J