ITRS workshop on Emerging Spin and Carbon Based

Emerging Logic Devices

George Bourianoff, IntelJim Hutchby, SRC

Barcelo Renacimiento HotelConference Room D2

Sept 17, 2010 (8:00 – 18:30)Seville, Spain

Outline

• ERD charter

• Background

• Meeting Objectives

• Next steps, timeline

• Agenda

Work in Progress --- Not for Publication3 ERD WG 7/11/2010 San Francisco, CA. FxF Meeting

Charter of ERD ChapterOn behalf of the 2011 ITRS, develop an Emerging

Research Devices chapter to -- Critically assess new approaches to Information

Processing technology beyond ultimate CMOS Identify most promising approach(es) to Information

Processing technology to be implemented by 2024

To offer substantive guidance to – Global research community Relevant government agencies Technology managers Suppliers

Work in Progress --- Not for Publication4 ERD WG 7/11/2010 San Francisco, CA. FxF Meeting

Scope of ERD Chapter

Integrated emerging research memory, logic and new architecture technologies enabled by supporting -- Materials and process technologies Modeling and simulation Metrologies

Selection of specific technical approaches shall be Guided by fundamental requirements Bounded by ERD’s topic selection criteria

Work in Progress --- Not for Publication5 ERD WG 7/11/2010 San Francisco, CA. FxF Meeting

Scope of ERD Chapter Criteria for Including Technology Entries

Devices and Architectures – Published by 2 or more groups in archival literature and peer

reviewed conferences, or Published extensively by 1 group in archival literature and peer

reviewed conferences Technology Entry (by itself or integrated with CMOS) must

address a major electronics market. Materials and Fabrication Technologies – Materials and processes that address the specific material needs

defined by emerging research device technology entries Supporting disciplines – specify for crosscut TWGs

Metrologies Modeling & simulation

Work in Progress --- Not for Publication6 ERD WG 7/11/2010 San Francisco, CA. FxF Meeting

Emerging Research Devices Working Group Meeting Objectives

Review ERD/ERM 2010 Workshops (cont’d) Logic Devices

Summary of VLSI Tech Workshop on III-V MOSFETs Assessment of III-V compound & Ge MOSFET technology Carbon-based nanoelectronic devices Spin Transfer Torque logic devices Review plans for ERD Device workshop in Seville, Spain on Sept. 17

Emerging Research Architectures (Logic device benchmarking) Current status Plans for 2010 – 2011

Summary of potential changes in 2011 ERD Chapter Summary of potential changes in 2011 ERM Chapter

Background

• ITRS rewritten on a 2 year cycle– Information gathering workshops and chapter

writing done on alternate years– 2010 is devoted to workshops– Previous Emerging Logic Workshop was held

in Tsukuba, Japan 2008 focusing on spin and graphene devices

• This workshop will review significant accomplishments in those areas in the intervening 2 years

Meeting objectives

• Review significant new research initiatives in spin based logic

• Review significant research programs and accomplishments in graphene based logic

• Hold brief business meeting– Discuss 2011 ERD Logic Table structure and

en tries– Discuss potential writing assignments

Work in Progress --- Not for Publication9 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting

Morning AGENDAProgress, status and research needs for spin based

logic elements – Sept, 17, 2010

8:00 Welcome and Introductions G. Bourianoff

8:15 Overview of DARPA Spin Logic Program D. Shenoy

8:50 Nano-magnetic Logic S. Hu

9:25 All Spin Logic B. Bhin-Aein

10:00 Break

10:15 Magnetic FPGA Spin in Logic T. Hanyu

10:50 "TIMARIS" Linear dynamic deposition technology W. Maass

for production of spintronic devices

11:25 Wrap-up and Discussion G. Bourianoff

12:00 Lunch

Work in Progress --- Not for Publication10 ERD/ERM WG 4/6-7/2010 Barza, ITALY Workshop & FxF Meeting

Afternoon AGENDAProgress, status and research needs for graphene

based logic elements – Sept. 17, 201013:15 Graphene Logic Devices P. Kim

13:50 Analog & RF Graphene – based FETs C.Y. Sung

14:20 GRAND Perspectives on Graphene Electronics H. Kurz

15:00 Break

15:15 Gate induced Bandgap for Graphene Devices T. Tsukagoshi

15:50 Graphene Research at CEA S. Roche

16:25 Wrap-up and Discussion J. Hutchby

17:00 Break

17:30 ITRS Business Meeting J. Hutchby

18:30 Adjourn

Business meeting

Emerging Research Logic Device business meeting

• Review table structure and make recommendations– 2009 had 3 tables plus transition table– Table 1 MOSFETS: Extending the channel to the End

of the Roadmap– Table 2 Charge based Beyond CMOS: Non-

Conventional FETs and other Charge-based information carrier devices

– Table 3 Alternative Information Processing Devices

• Review table entries and make recommendations

13 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009

New Logic Technology Tables

Table 1 – MOSFETsExtending the Channel

of MOSFETs to theEnd of the roadmap _____________

CNT FETsGraphene nanoribbons

III-V Channel MOSFETsGe Channel MOSFETs

Nanowire FETsNon conventional geometry devices

Table 2- UnconventionalFETS, Charge-based

Extended CMOS Devices

_______________

Tunnel FET I-MOS

Spin FET SET

NEMS switchNegative Cg MOSFET

Table 3 - Non-FET, Non Charge-based ‘Beyond

CMOS’ devices

_______________

Collective Magnetic DevicesMoving domain wall devices

Atomic SwitchMolecular Switch

Pseudo-spintronic DevicesNanomagnetic (M:QCA)

2009 Logic Transition tableTechnology Status Reason Comment

RTD out No viable logic functionality

Has been tracked for multiple revisions

Bi-layer tunneling devices

In Significant theoretical work in NRI

Band to band tunneling devices

In

NEMS In

RSFQ Possible future device

Spin FET [K]Spin MOSFET

bCell Size 100 nm

(spatial pitch) [B]for spin MOSFET

[L]

~1mm (channel length)

2000 nm for Spin FET[M]Not known: ~1E10

channel length scalable down to

20nm [D]1.00E+10

for spin MOSFET [L]

Demonstrated 2.80E+08 ~1E10 2.50E+07 Unknown Not investigated ~2E9 1 /cm**2 W2

~10 THz or less

Identical to CMOSFET- with Ge,

SiGe [E],[F],[G]

for spin MOSFET [N]]

Si/Ge/InAs tunneling source:

not known 30GHz

1GHz/1THz/3THz [A]

for Spin FET[M]

~10GHz or lessIdentical to

CMOSFET- with Ge, SiGe [E],[F],[G]

for spin MOSFET [M]

Not known:

will depend on the source material used

not known

1E-17-1E-18 1×10–18 [O]Identical to

CMOSFET- with Ge, SiGe [E],[F],[G]

for spin MOSFET [M]] [>1.5×10–17 ] [U]

Si/Ge/InAs tunneling source: 8×10–17 [V]

90/90/3000E-18 [>1.3×10–14] [W]J/um at VDD=0.5V,

L=20nm [A]not known

Binary Throughput,

GBit/ns/cm 2 Projected 238 Not known not known Not known ~200 10 10

Demonstrated: 70 nm, 100nm [B,C]

100 nm

Table ERD7b Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based information carrier devices

Device FET [A] Negative Cg FETTunnel FET Spin Transistor

Typical example devices Si CMOSAll Si tunnel FET

Strained Ge or III-V Ferroelectric FET

[H], [I]

Projected 100 nm100 nm [same as

CMOS]40 nm [O]20 nm [A]

~200 nm [P,Q]

Single Electron Transistor

MEMSI-MOS

100 nm [X}

900 nm

Density

(device/cm 2 )

Projected 1.00E+101E10[same as

CMOS] [I]6.00E+10 1.00E+10

Demonstrated 590 nm Unknown

Switch Speed

Projected 12 THz Not known

Circuit Speed

Projected 61 GHz Not known

1 GHz [Y]

Demonstrated 1.5 THz N/A 2 THz [S] 0.18 GHz [Z]

Unknown Limited by the ferroelectric response time, depends on the

ferroelectric material

10 THz [R]

1 GHz

Demonstrated 5.6 GHz N/A Not investigated 1 MHz [T] .18 GHz

Unknown Limited by the ferroelectric response time, depends on the

2 GHz [O]

unknown5E -17 J [A1,A2]

Demonstrated 1.00E-16 N/A Not investigated

Switching Energy, J

Projected 3.00E-18 Not known

Table ERD7c Alternative Information Processing Devices

Collective spin devices Moving Domain wall Atomic switch Molecular Pseudospintronc Nano magnetic

State Variable SpinPolarization,

magnetizationmetal cations / atoms

Molecular configuration

Charge distribution symmetry in two

layers

Magneric polarization

patterns

Response Function Sinusoidal, various Non linear Non-linear Nonlinear, NDRGate controlled

NDRNon linear

Class—ExampleSpin Wave Mach

ZenderFerromagnetic wire

devicesProgramable logic

Combinatorial logic circuits

Bilayer Pseudospin Field Effent Transistor

MQCA majority gate

Architecture Morphic Morphic Morphic, cross bar Morphic Morphic Morphic

Application Signal ProcessingLow power,

reconfigurable logicNon volitale logic

Combinatorial logic circuits

General purpose logic

General purpose logic

CommentsLow resistance, low

powerExtremely low

powerLow power, high

densityStatus Demonstrated Simulated Demonstrated Simulated Simulated, theory Demonstrated

Material IssuesHigh propagation loss,

slow propagation velocity

High permeability material required

Low defect bilayer graphene, contacts

Work in Progress --- Not for Publication17 ERD WG 7/11/2010 San Francisco, CA. FxF Meeting

Issues and Decisions for 2011 Chapter - LogicLogic (Baltimore):

The following questions were addressed:1. Is the new organization (e.g. 3 subsections) an effective taxonomy of logic devices?

2. Are the technology entries the best candidates pursed by the research community?

3. Any technology entries in the logic chapter to move to the transition table? Potential candidates for 2011?

4. Right level of details? Mission accomplished concerning current status and critical paths?

Refer to Adrian Ionescu’s presentation for his thoughtful answers to these questions (attached to this file).

• In the Logic Transition Table, the IN/OUT entries for Ge FET, Spin MOSFET, Collective Spin Devices, Pseudomorphic, and Nanomagnetic Devices should be move into the Comment column to the right. Entries in the IN/OUT column might better be technical in nature. (being considered & discussed)

Work in Progress --- Not for Publication18 ERD WG 7/11/2010 San Francisco, CA. FxF Meeting

Issues and Decisions for 2011 Chapter - Logic• Areas for improvements (suggested by Adrian Ionescu):

– Introduction of energy efficiency criteria? Important (being considered/discussed)

– Role of other functionality than digital of beyond CMOS: image processing, analog, RF, etc. (being considered/discussed)

– Convergence of beyond CMOS and More than Moore technology entries? MEMS/NEMS already in (being considered/discussed)

– More interaction with emerging architectures needed. (Decided)• Transfer to PIDS in 2011

– Alternate channel materials , Ge and III-V Semiconductors (keep CNT and GNR FETs) (Decided)

– Unconventional FET s, Tri-Gate, FinFET, GAA FETs, etc. (Decided)Logic (Hsinchu):• Transfer to PIDS in 2011

– Alternate channel materials , Ge and III-V Semiconductors (keep CNT and GNR FETs) (Decided)

• Unconventional FET s, Tri-Gate, FinFET, GAA FETs, etc. (Decided)

19 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009

Resistive Memories

Memory Technology Entries

Nanothermal–Thermochemical FUSE/Anti-FUSE− Nanowire PCM Nanoionic Memory (Electrochemical)− Cation migration− Anion migration

Electronic Effects Memory− Charge trapping− Metal-Insulator Transition− FE barrier effects

Nanoelectromechanical Spin Transfer Torque MRAMMacromolecular (Polymer)Molecular Memory

FeFET Memory

Capacitive Memory

Work in Progress --- Not for Publication20 ERD WG 7/11/2010 San Francisco, CA. FxF Meeting

Issues and Decisions for 2011 Chapter - Memory

Memory (Baltimore):• In the Memory Section, we need to discuss fabrication

and issues related to the select device, either a diode or a transistor, for the storage elements in a cross-bar array.

• We will include emerging research solid state Storage Class Memory technologies, but not include SCM based on mechanical or magnetic disc storage. The driving issue is to minimize the cost per bit – this is very important.

Memory (Hsinchu): No decisions

Proposed changes to the ERD Memory section

To take out the “electronic effect memories” entry from the ERD memory table

The FTJ memory could be covered along with FeFET as a subcategory

Mott Memory could form a stand-alone entry if the ERD group decides, there is a sufficient critical mass of works

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