10-Bit, 210 MSPS ADC AD9410 - Analog Devices · 2019. 6. 5. · 10-Bit, 210 MSPS ADC AD9410 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable

10-Bit, 210 MSPS ADC

AD9410

Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2007 Analog Devices, Inc. All rights reserved.

FEATURES SNR = 54 dB with 99 MHz analog input 500 MHz analog bandwidth On-chip reference and track and hold 1.5 V p-p differential analog input range 5.0 V and 3.3 V supply operation 3.3 V CMOS/TTL outputs Power: 2.1 W typical at 210 MSPS Demultiplexed outputs each at 105 MSPS Output data format option Data sync input and data clock output provided Interleaved or parallel data output option

APPLICATIONS Communications and radars Local multipoint distribution services (LMDS) High-end imaging systems and projectors Cable reverse paths Point-to-point radio links

FUNCTIONAL BLOCK DIAGRAM

T/H

DS

CLK–

DSCLK+

DFS I/P

REFERENCE

DGNDAGND

DCO

10

DCO

AD9410

10

10ADC10-BITCORE

TIMING ANDSYNCHRONIZATION

PORTB

PORTA

REFIN REFOUT VD VDD VCC

ORA

DA9–DA0

ORB

DB9–DB0

AIN

AIN

0167

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Figure 1.

GENERAL DESCRIPTION The AD9410 is a 10-bit monolithic sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit and is optimized for high speed conversion and ease of use. The product operates at a 210 MSPS conversion rate, with outstanding dynamic performance over its full operating range.

The ADC requires a 5.0 V and 3.3 V power supply and up to a 210 MHz differential clock input for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL-/CMOS-compatible and separate output power supply pins also support interfacing with 3.3 V logic.

The clock input is differential and TTL-/CMOS-compatible. The 10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V) supplies. Two output buses support demultiplexed data up to 105 MSPS rates and binary or twos complement output coding format is available. A data sync function is provided for timing-dependent applications. An output clock simplifies interfacing to external logic. The output data bus timing is selectable for parallel or interleaved mode, allowing for flexibility in latching output data.

Fabricated on an advanced BiCMOS process, the AD9410 is available in an 80-lead thin quad flat package, exposed pad specified over the industrial temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS 1. High Resolution at High Speed—The architecture is spe-

cifically designed to support conversion up to 210 MSPS with outstanding dynamic performance.

2. Demultiplexed Output—Output data is decimated by two and provided on two data ports for ease of data transport.

3. Output Data Clock—The AD9410 provides an output data clock synchronous with the output data, simplifying the timing between data and other logic.

4. Data Synchronization—A DS input is provided to allow for synchronization of two or more AD9410s in a system, or to synchronize data to a specific output port in a single AD9410 system.

AD9410

Rev. A | Page 2 of 20

TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3

DC Specifications ......................................................................... 3 Switching Specifications .............................................................. 4 Digital Specifications ................................................................... 4 AC Specifications.......................................................................... 5

Absolute Maximum Ratings............................................................ 7 Explaination of Test Levels.......................................................... 7 ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions..............................8 Terminology .................................................................................... 10

Equivalent Circuits..................................................................... 12 Typical Performance Characteristics ........................................... 13 Theory of Operation ...................................................................... 16

Using the AD9410 ...................................................................... 16 Analog Input ............................................................................... 16 Digital Outputs ........................................................................... 16 Clock Outputs (DCO, DCO).................................................... 16 Voltage Reference ....................................................................... 17 Timing ......................................................................................... 17 Data Sync (DS) ........................................................................... 17

Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19

REVISION HISTORY 7/07—Rev. 0 to Rev. A Updated Format..................................................................Universal Deleted 80-Lead LQFP_EP ...............................................Universal Added 80-Lead TQFP_EP.................................................Universal Changes to Figure 1 and General Description ............................. 1 Changes to Table 2 and Table 3....................................................... 4 Changes to Figure 2.......................................................................... 6 Changes to Note 1............................................................................. 7 Changes to Figure 3 and Table 6..................................................... 8 Changes to Terminology Section.................................................. 10 Changes to Figure 6........................................................................ 12 Deleted Evaluation Board Section................................................ 14 Renamed Encode Input Section, Clock Input Section and Changes to Clock Input Section, Clock Outputs (DCO, DCO) Section, Figure 26, and Figure 27 ................................................. 16 Changes to Data Sync (DS) Section ............................................. 17 Changes to Figure 29...................................................................... 18 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19

10/00—Revision 0: Initial Version

AD9410


SPECIFICATIONS DC SPECIFICATIONS VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.

Table 1. Parameter Temp Test Level Min Typ Max Unit RESOLUTION 10 Bits DC ACCURACY

No Missing Codes Full IV Guaranteed Differential Nonlinearity 25°C I −1.0 ±0.5 +1.25 LSB Full VI −1.0 +1.5 LSB Integral Nonlinearity 25°C I −2.5 ±1.65 +2.5 LSB Full VI −3.0 +3.0 LSB Gain Error 25°C I −6.0 0 +6.0 % FS Gain Temperature Coefficient Full V 130 ppm/°C

ANALOG INPUT

Input Voltage Range (With Respect to AIN) Full V ±768 mV p-p

Common-Mode Voltage Full V 3.0 V Input Offset Voltage 25°C I −15 +3 +15 mV Full VI −20 +20 mV Reference Voltage Full VI 2.4 2.5 2.6 V Reference Temperature Coefficient Full V 50 ppm/°C Input Resistance Full VI 610 875 1250 Ω Input Capacitance 25°C V 3 pF Analog Bandwidth, Full Power 25°C V 500 MHz

POWER SUPPLY

Power Dissipation AC1 25°C V 2.1 W Power Dissipation DC2 Full VI 2.0 2.4 W

IVCC2 Full VI 128 145 mA IVD2 Full VI 401 480 mA

Power Supply Rejection Ratio, PSRR 25°C I −7.5 +0.5 +7.5 mV/V 1 Clock input = 210 MSPS, AIN = –0.5 dBFS, 10 MHz sine wave, IVDD = 31 mA typical at CLOAD = 5 pF. 2 Clock input = 210 MSPS, AIN = dc, outputs not switching.

AD9410


SWITCHING SPECIFICATIONS VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.

Table 2. Parameter Temp Test Level Min Typ Max Unit SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 210 MSPS Minimum Conversion Rate Full IV 100 MSPS Clock Pulse Width High, tEH 25°C IV 1.2 2.4 ns Clock Pulse Width Low, tEL 25°C IV 1.2 2.4 ns Aperture Delay, tA 25°C V 1.0 ns Aperture Uncertainty (Jitter) 25°C V 0.65 ps rms Output Valid Time, tV Full VI 3.0 ns Output Propagation Delay, tPD Full VI 7.4 ns Output Rise Time, tR 25°C V 1.8 ns Output Fall Time, tF 25°C V 1.4 ns CLKOUT Propagation Delay, tCPD1 Full VI 2.6 4.8 6.4 ns Data to DCO Skew, (tPD – tCPD) Full IV 0 1 2 ns

DS Setup Time, tSDS Full IV 0.5 ns DS Hold Time, tHDS Full IV 0 ns

Interleaved Mode (A, B Latency) Full VI A = 6, B = 6 Cycles Parallel Mode (A, B Latency) Full VI A = 7, B = 6 Cycles

1 CLOAD = 5 pF.

DIGITAL SPECIFICATIONS VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.

Table 3. Parameter Temp Test Level Min Typ Max Unit DIGITAL INPUTS

DFS, Input Logic 1 Voltage Full IV 4 V DFS, Input Logic 0 Voltage Full IV 1 V DFS, Input Logic 1 Current Full V 50 μA DFS, Input Logic 0 Current Full V 50 μA I/P Input Logic 1 Current1 Full V 400 μA I/P Input Logic 0 Current1 Full V 1 μA CLK+, CLK− Differential Input Voltage Full IV 0.4 V CLK+, CLK− Differential Input Resistance Full V 1.6 kΩ CLK+, CLK− Common-Mode Input Voltage2 Full V 1.5 V DS, DS Differential Input Voltage Full IV 0.4 V

DS, DS Common-Mode Input Voltage Full V 1.5 V

Digital Input Pin Capacitance 25°C V 3 pF

DIGITAL OUTPUTS

Logic 1 Voltage (VDD = 3.3 V) Full VI VDD – 0.05 V Logic 0 Voltage (VDD = 3.3 V) Full VI 0.05 V Output Coding Binary or Twos Complement

1 I/P pin Logic 1 = 5 V, Logic 0 = GND. It is recommended to use a series 2.5 kΩ (±10%) resistor to VDD when setting to Logic 1 to limit input current. 2 See Clock Input section.

AD9410


AC SPECIFICATIONS VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.

Table 4.

Parameter Temp Test Level Min Typ Max Unit DYNAMIC PERFORMANCE

Transient Response 25°C V 2 ns Overvoltage Recovery Time 25°C V 2 ns Signal-to-Noise Ratio, SNR (Without Harmonics)

fIN = 10.3 MHz 25°C I 52.5 55 dB fIN = 82 MHz 25°C I 52 54 dB fIN = 160 MHz 25°C V 53 dB

Signal-to-Noise Ratio, SINAD (With Harmonics) fIN = 10.3 MHz 25°C I 51 54 dB fIN = 82 MHz 25°C I 50 53 dB fIN = 160 MHz 25°C V 52 dB

Effective Number of Bits, ENOB fIN = 10.3 MHz 25°C I 8.3 8.8 Bits fIN = 82 MHz 25°C I 8.1 8.6 Bits fIN = 160 MHz 25°C V 8.4 Bits

Second Harmonic Distortion fIN = 10.3 MHz 25°C I −56 −65 dBc fIN = 82 MHz 25°C I −55 −63 dBc fIN = 160 MHz 25°C V −65 dBc

Third Harmonic Distortion fIN = 10.3 MHz 25°C I −58 −69 dBc fIN = 82 MHz 25°C I −57 −67 dBc fIN = 160 MHz 25°C V −62 dBc

Spurious-Free Dynamic Range, SFDR fIN = 10.3 MHz 25°C I 56 61 dBc fIN = 82 MHz 25°C I 54 60 dBc fIN = 160 MHz 25°C V 58 dBc

Two-Tone Intermod Distortion, IMD1 fIN1 = 80.3 MHz, fIN2 = 81.3 MHz 25°C V 58 dBFS

1 IN1, IN2 level = −7 dBFS.

AD9410


tEH tEL1/fS

tA

tSDS

tCPD

SAMPLE N–2

SAMPLE N–1 SAMPLE N

SAMPLE N+1 SAMPLE N+2

SAMPLE N+3SAMPLE N+4 SAMPLE N+5

SAMPLE N+6

tVtPD

tHDS

STATIC

STATIC

STATIC

STATIC

STATIC INVALIDINVALID INVALID

INVALID

INVALID

INVALID

INVALID

INVALID

INVALID

INVALID

INVALID

INVALID

INVALID

DATA N+1 DATA N+3

DATA N DATA N+2

DATA N+1

DATA N DATA N+2

INTERLEAVED DATA OUT

PARALLEL DATA OUT

AIN

CLK+

DS

PORT AD7 TO D0

PORT BD7 TO D0

DCO

PORT AD7 TO D0

PORT BD7 TO D0

CLK–

DS

DCO

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Figure 2. Timing Diagram

AD9410


ABSOLUTE MAXIMUM RATINGS

Table 5. Parameter Rating VD, VCC, VDD 6 V Analog Inputs 0 V to VCC + 0.5 V Digital Inputs 0 V to VDD + 0.5 V VREFIN 0 V to VD + 0.5 V Digital Output Current 20 mA Operating Temperature Range −55°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature1 150°C 1 Adequate dissipation of power from the AD9410 relies on all power and

ground pins of the device being soldered directly to a copper plane on a PCB. In addition, the thermally enhanced package of the AD9410BSVZ has an exposed paddle on the bottom that must be soldered to a large copper plane, which, for convenience, can be the ground plane. Sockets for package style of the AD9410 device are not recommended.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EXPLAINATION OF TEST LEVELS Test Level

I. 100% production tested.

II. 100% production tested at 25°C and sample tested at specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range.

ESD CAUTION

AD9410


PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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PIN 1IDENTIFIER

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

6162636465666768697071727374757677787980

AD9410TOP VIEW

80-LEAD THIN QUAD FLAT PACKAGE(Not to Scale)

AGNDAGND

VCCREFOUT

REFINDNCVCC

AGNDAGND

AIN

AGNDAGND

VCCVCC

AGNDAGNDCLK+

AGND

VDDDGNDDA4DA3DA2DA1DA0 (LSB)VDDDGNDDCODCODGNDVDDORBDB9 (MSB)DB8DB7DB6DB5VDD

I/P DFS

AG

ND

AG

ND

V D V D AG

ND

AG

ND

AG

ND

AG

ND

V D V D DG

ND

V DD

OR

AD

A9

(MSB

)D

A8

DA

7D

A6

DA

5

AG

ND DS

AG

ND V D V D

AG

ND

AG

ND

AG

ND

AG

ND V D V D

DG

ND

V DD

(LSB

) DB

0D

B1

DB

2D

B3

DB

4D

GN

D

AIN

CLK–

DS

DNC = DO NOT CONNECT. Figure 3. Pin Configuration

Table 6. Pin Function Descriptions Pin No. Mnemonic Function 1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24, 27, 28, 29, 30, 71, 72, 73, 74, 77, 78

AGND Analog Ground.

3, 7, 14, 15 VCC 5 V Supply. (Regulate to within ±5%.)

4 REFOUT Internal Reference Output.

5 REFIN Internal Reference Input.

6 DNC Do Not Connect. 10 AIN Analog Input—True.

11 AIN Analog Input—Complement.

18 CLK+ Clock Input—True.

19 CLK− Clock Input—Complement.

22 DS Data Sync (Input)—True. Tie low if not used.

23 DS Data Sync (Input)—Complement. Float and decouple with 0.1 μF capacitor if not used.

25, 26, 31, 32, 69, 70, 75, 76

VD 3.3 V Analog Supply. (Regulate to within ±5%.)

33, 40, 49, 52, 59, 68 DGND Digital Ground.

34, 41, 48, 53, 60, 67 VDD 3.3 V Digital Output Supply. (2.5 V to 3.6 V)

35 to 39 DB0 to DB4 Digital Data Output for Channel B. (LSB = DB0.)

42 to 46 DB5 to DB9 Digital Data Output for Channel B. (MSB = DB9.)

47 ORB Data Overrange for Channel B.

50 DCO Clock Output—Complement.

AD9410


Pin No. Mnemonic Function 51 DCO Clock Output—True.

54 to 58 DA0 to DA4 Digital Data Output for Channel A (LSB = DA0).

61 to 65 DA5 to DA9 Digital Data Output for Channel A (MSB = DA9).

66 ORA Data Overrange for Channel A.

79 DFS Data Format Select. High = twos complement, and low = binary.

80 I/P Interleaved or Parallel Output Mode. Low = parallel mode, and high = interleaved mode. If tying high, use a current limiting series resistor (2.5 kΩ) to the 5 V supply.

AD9410


TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay The delay between the 50% point of the rising edge of the clock command and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.

Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and taking the peak measurement again. The difference is then computed between both peak measurements.

Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step.

Effective Number of Bits (ENOB) ENOB is calculated from the measured SINAD based on the equation

02.6

log2076.1 ⎟⎟⎠

⎞⎜⎜⎝

⎛+−

=

AmplitudeInputAmplitudeScaleFull

dBSINAD

ENOB

MEASURED

Clock Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time the clock pulse should be left in low state. At a given clock rate, these specifications define an acceptable clock duty cycle.

Full-Scale Input Power Expressed in dBm. Computed using the equation

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

001.0

log102

INPUT

FULLSCALEFULLSCALE Z

VPOWER rms

Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.

Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.

Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least-square curve fit.

Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate The clock rate at which parametric testing is performed.

Output Propagation Delay The delay between a differential crossing of CLK+ and CLK− and the time when all output data bits are within valid logic levels.

Out-of-Range Recovery Time Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

Noise (For Any Range Within the ADC)

⎟⎠⎞

⎜⎝⎛ −××=

1010001.0|| dBFSdBmNOISE

SIGNALFSZV

where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SIGNAL is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise.

Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in power supply voltage.

AD9410


Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 0.5 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.

Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It may be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale).

Transient Response Time Transient response time is defined as the time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale.

Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc.

Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale).

Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc.

Table 7. Output Coding (VREF = 2.5 V) Step AIN − AIN Digital Outputs Offset Binary Digital Outputs Twos Complement ORA, ORB

>+0.768 11 1111 1111 01 1111 1111 1

1023 +0.768 11 1111 1111 01 1111 1111 0 · · · · · · · · · · 513 +0.0015 10 0000 0001 00 0000 0001 0 512 0.0 10 0000 0000 00 0000 0000 0 511 –0.0015 01 1111 1111 11 1111 1111 0 · · · · · · · · · · 0 –0.768 00 0000 0000 10 0000 0000 0 < –0.768 00 0000 0000 10 0000 0000 1

AD9410


EQUIVALENT CIRCUITS

1.5kΩ

2.25kΩ

1.5kΩ

2.25kΩ

VCC

AIN AIN

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Figure 4. Equivalent Analog Input Circuit

VREFIN

VCC

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Figure 5. Equivalent Reference Input Circuit

17kΩ17kΩ

8kΩ 8kΩ

CLK+

100Ω 100Ω

CLK–

450Ω 450Ω

VCC

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Figure 6. Equivalent Clock Input Circuit

VDD

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DIGITALOUTPUT

Figure 7. Equivalent Digital Output Circuit

VREFOUT

VCC

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8

Figure 8. Equivalent Reference Output Circuit

100kΩ

DFS

VCC

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Figure 9. Equivalent DFS Input Circuit

7.5kΩ

DS300Ω

17.5kΩ300Ω

DS

VCC

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Figure 10. Equivalent DS Input Circuit

7.5kΩ

I/P300Ω

17.5kΩ

VCC

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Figure 11. Equivalent I/P Input Circuit

AD9410


TYPICAL PERFORMANCE CHARACTERISTICS

FREQUENCY (MHz)

0

0

AM

PLIT

UD

E (d

B)

–20

–40

–60

–80

–100

–120105

ENCODE = 210MSPSAIN = 40MHz @ –0.5dBFSSNR = 54.5dBSINAD = 53.5dB

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Figure 12. Single Tone at 40 MHz; 210 MSPS

FREQUENCY (MHz)

0

0

AM

PLIT

UD

E (d

B)

–20

–40

–60

–80

–100

–120105

ENCODE = 210MSPSAIN = 100MHz @ –0.5dBFSSNR = 53.5dBSINAD = 52.5dB

0167

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3


FREQUENCY (MHz)

0

0

AM

PLIT

UD

E (d

B)

–20

–40

–60

–80

–100

–120105

ENCODE = 210MSPSAIN = 160MHz @ –0.5dBFSSNR = 53dBSINAD = 52dB

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4


51

SNR

/SIN

AD

(dB

)

50

49

48

47

46

45

53

55

SNR

SINAD

52

54

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AIN (MHz)0 50 100 150 200 250

Figure 15. SNR/SINAD vs. AIN; 210 MSPS

SAMPLE RATE (MSPS)

53.0

SNR

/SIN

AD

(dB

)

52.5

52.0

51.5

51.0

50.5

50.0

54.0

55.0

SNR

SINAD

53.5

54.5

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6

100 120 140 160 180 200 220 240

Figure 16. SNR/SINAD vs. Sample Rate; AIN = 70 MHz

PULSE WIDTH (ns)

40SN

R/S

INA

D (d

B)

35

30

55

60

50

45

SINAD

SNR

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0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Figure 17. SNR/SINAD vs. Clock Positive Pulse Width

(fS = 210 MSPS, AIN = 70 MHz)

AD9410


FREQUENCY (MHz)

0

0

AM

PLIT

UD

E (d

B)

–20

–40

–60

–80

–100

–120105

ENCODE = 210MSPSAIN1, AIN2 = –7dBFSSFDR = 62dBFS

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Figure 18. Two Tone Test AIN1 = 80.3 MHz, AIN2 = 81.3 MHz

54.5

SNR

/SIN

AD

(dB

)

54.0

53.5

53.0

52.5

52.0

51.5

55.0

55.5

SNR

SINAD

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TEMPERATURE (°C)–40 –20 0 20 40 60 80 100 120

Figure 19. SNR/SINAD vs. Temperature, 210 MSPS, AIN = 70 MHz

TEMPERATURE (°C)

70

SEC

ON

D A

ND

TH

IRD

HA

RM

ON

IC A

MPL

ITU

DE

(dB

)

68

66

64

62

60

58

72

74

H2

H3

–40 –20 0 20 40 60 80 100 120

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Figure 20. Second and Third Harmonics vs. Temperature; AIN = 70 MHz, 210 MSPS

ANALOG SUPPLY (V)

2.48

VREF

(V)

2.47

2.46

2.51

2.52

2.50

2.49

4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

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Figure 21. VREFOUT vs. Analog 5 V Supply

SAMPLE RATE (MSPS)

110

100

SUPP

LY C

UR

REN

T (m

A)

60

10

260

310

210

160

220

360

410

460

IAhi3

IAhi5

Ivdd

120 140 160 180 200

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Figure 22. Power Supply Currents vs. Sample Rate

LOAD CURRENT (mA)

2.35

0

VREF

(V)

2.30

2.251.5

2.40

2.5

2.45

2.50

2.55

0167

9-02

3

0.5 1.0 2.0

Figure 23. VREFOUT vs. ILOAD

AD9410


TEMPERATURE (°C)

VREF

(V)

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496806040200–20–40

0167

9-02

4

Figure 24. VREFOUT vs. Temperature

TIM

ING

SPE

CIF

ICA

TIO

NS

(ns)

5.1

4.9

4.7

4.5

4.3

4.1

3.9

TEMPERATURE (°C)806040200–20–40

0167

9-02

5

tPD

tV

tCPD

Figure 25. tPD, tV, tCPD vs. Temperature

AD9410


THEORY OF OPERATION The AD9410 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the flash 10-bit core. For ease of use, the part includes an on-board reference and input logic that accepts TTL, CMOS, or PECL levels.

USING THE AD9410 Clock Input

Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock combines with the desired signal at the ADC output. For that reason, considerable care has been taken in the design of the clock input of the AD9410, and the user is advised to give commensurate thought to the clock source. To limit SNR degradation to less than 1 dB, a clock source with less than 1.25 ps rms jitter is required for sampling at Nyquist (for example, the Valpey Fisher VF561). Note that required jitter accuracy is a function of input frequency and amplitude. Refer to the Analog Devices, Inc. AN-501 application note, Aperture Uncertainty and ADC System Performance, for more information.

The clock input is fully TTL/CMOS compatible. The clock input can be driven differentially or with a single-ended signal. Best performance is obtained when driving the clock differentially. Both clock inputs are self-biased to 1/3 × VCC by a high impedance resistor divider (see the Equivalent Circuits section). Single-ended clocking, which can be appropriate for lower frequency or nondemanding applications, is accomplished by driving the clock input directly and placing a 0.1 μF capacitor at CLOCK.

CLK+

CLK–

AD9410TTL/CMOSGATE

0.1µF

0167

9-02

6

Figure 26. Driving Single-Ended Clock Input at TTL/CMOS Levels

An example where the clock is obtained from a PECL driver is shown in Figure 27. Note that the PECL driver is ac-coupled to the clock inputs to minimize input current loading. The AD9410 can be dc-coupled to PECL logic levels, resulting in the clock input currents increasing to approximately 8 mA typical, which is due to the difference in dc bias between the clock inputs and a PECL driver (see the Equivalent Circuits section).

CLK+

CLK–

AD9410PECLGATE

0.1µF

0167

9-02

7

0.1µF

GND

510Ω 510Ω

Figure 27. Driving the Clock Inputs Differentially

ANALOG INPUT The analog input to the AD9410 is a differential buffer. For best dynamic performance, impedances at AIN and AIN should match. The analog input has been optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a single-ended signal. A wideband transformer, such as Mini-Circuits ADT1-1WT, can be used to provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to nominal 3 V (see the Equivalent Circuits section).

Special care was taken in the design of the Analog Input section of the AD9410 to prevent damage and corruption of data when the input is overdriven. The nominal input range is 1.5 V diff p-p.

The nominal differential input range is 768 mV p-p × 2.

2.616

INPU

T SP

AN

(V)

3.384

3.000

AIN

AIN

0167

9-02

8

Figure 28. Typical Analog Input Levels

DIGITAL OUTPUTS The digital outputs are TTL/CMOS compatible for lower power consumption. The outputs are biased from a separate supply (VDD), allowing easy interface to external logic. The outputs are CMOS devices that swing from ground to VDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (

AD9410


VOLTAGE REFERENCE A stable and accurate 2.5 V voltage reference is built into the AD9410 (VREFOUT). The input range can be adjusted by varying the reference voltage. No appreciable degradation in performance occurs when the reference is adjusted ±5%. The full-scale range of the ADC tracks reference voltage changes linearly within the ±5% tolerance.

TIMING The AD9410 provides latched data outputs, with six pipeline delays in interleaved mode (see Figure 2). In parallel mode, the Port A has one additional cycle of latency added on-chip to line up transitions at the data ports, resulting in a latency of seven cycles for the Port A. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9410; these transients can detract from the dynamic performance of the converter.

The minimum guaranteed conversion rate of the AD9410 is 100 MSPS. At internal clock rates below 100 MSPS, dynamic performance may degrade. Note that lower effective sampling rates can be obtained simply by sampling just one output port—decimating the output by two. Lower sampling frequencies can also be accommodated by restricting the duty cycle of the clock such that the clock high pulse width is a maximum of 5 ns.

DATA SYNC (DS) The data sync input, DS, can be used in applications requiring that a given sample appear at a specific output Port A or Port B. When DS is held high, the ADC data outputs and clock do not switch and are held static. Synchronization is accomplished by the assertion (falling edge) of DS, within the timing constraints tSDS and tHDS relative to an clock rising edge. (On initial synchronization, tHDS is not relevant.) If DS falls within the required setup time (tSDS) before a given clock rising edge N, the analog value at that point is digitized and available at Port B six cycles later (interleaved mode). The next sample, N+1, is sampled by the next rising clock edge and available at Port A six cycles after that clock edge (interleaved mode). In dual parallel mode, Port A has a seven cycle latency, and Port B has a six cycle latency, but data is available at the same time.

AD9410


DAOR

DA7DA8

DA5GND

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

GNDDA6

DA9

GND

3.3VAGND

3.3VA3.3VA

GND

3.3VA GND

GNDE14

5V

GND

E12

E16

5V

E10

GNDVDD

E11E7

DBOR

GND

DCOC

DCOT

GND

DB9

DB6

DB7

DA0

DA1

DA2

DA3

DA4

GND

VDD

DB8

VDD

VDD

GND

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

DGND

DCO

DCO

DGND

DGND

GND

GND

VDD

DB5

GNDGND DB0DB1

DB2

DB4GND

GND

4039383736353433323130292827262524232221

VDD

3.3VA

3.3VAGND

GND

3.3VA

GND

3.3VAGND

GND

J9X

J10X

AG

ND

DS

DS

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

DG

ND

DG

ND

GND

5V

GND

GND

ENCT

ENCC

GND

GND

GND

E3

E6

5V

GND

E1

1 T1

1:1

GND

J8

AIN

GND2

3

6

54

GND

GND

GND

GND

GND

5V

GND

AD9410U3

GND

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

C280.1 F

1

2

3

4 5

6

7

8NC

D

D

VBB

VCC

Q

Q

VEE

U1

5V

GND

GND

J1 5V

GND

GND

R15330Ω

GND

R11330Ω

ENCT

ENCC

GND

MC10EL16

GND GND

5V

P1

P5

P4

GND

VDD/3.3V

GND

GND

3.3VA

GND

5V

GND

VDAC

GND

EXT REF

GND

1

2

3

4

1

2

3

4

1

2

3

4

GND

5V 3.3VA VDD EXT REF VDAC

DG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

DFSI/P

AGND

AGND

DNC

AGND

AGND

AGND

AGND

AGND

AGND

CLK+

CLK–

AGND

DB3

C110µF

C210µF

C310µF

C510µF

C410µF

R850Ω R18

24kΩR924kΩ

R198.2kΩ

R148.2kΩ

C60.1µF

C400.1µF C7

0.1µF

C80.1µF

NOTE:R3, R6, R7, R24 OPTIONAL(CAN BE ZERO Ω )

C140.1µF

C110.1µF

C100.1µF

R6100Ω

R42.5kΩ

R7100Ω

R3100Ω

R24100Ω

C270.1µF

C260.1µF

EXTREF

C240.1µF

C250.1µF

C70.1µF

R2350Ω

R25X50Ω

C160.1µF

C150.1µF

R2650Ω

C190.1µF

C180.1µF

C220.1µF

C210.1µF

C120.1µF

0167

9-02

9

VCCREFOUTREFIN

VCC

R2750Ω

AIN

AIN

VCCVCC

V DV D V DV D DB

0

V DD

DB

1

DB

2

DB

3

DB

4VDD

DB6

VDD

DB5

DB7

DB8

DB9

ORB

VDD

DA1

VDD

DA0

DA2

DA3

DA4

DA

5

DA

6

DA

7

DA

8

DA

9

OR

A

V DDV D V DV DV D

Figure 29. PCB Schematic Example

AD9410


OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-026-AEC-HD 0915

06-A

0.750.600.45

1.20MAX

1.051.000.95

0.200.09

0.08 MAXCOPLANARITY

VIEW AROTATED 90° CCW

SEATINGPLANE

0° MIN

7°3.5°0°0.15

0.05VIEW A

PIN 1

TOP VIEW(PINS DOWN)

0.270.220.17

0.65 BSCLEAD PITCH

BOTTOM VIEW(PINS UP)

9.50 SQEXPOSEDPAD

2021 2140 40

41

61 61

60

41

60

80 80

1

20

1

16.2016.00 SQ15.80 14.20

14.00 SQ13.80

Figure 30. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-80-4) Dimensions shown in millimeters

ORDERING GUIDE Model Temperature Range Package Description Option AD9410BSVZ1 −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-4 1 Z = RoHS Compliant Part.

AD9410


NOTES

©2000–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01679-0-7/07(A)

FEATURESAPPLICATIONSFUNCTIONAL BLOCK DIAGRAMGENERAL DESCRIPTIONPRODUCT HIGHLIGHTSTABLE OF CONTENTSREVISION HISTORYSPECIFICATIONSDC SPECIFICATIONSSWITCHING SPECIFICATIONSDIGITAL SPECIFICATIONSAC SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGSEXPLAINATION OF TEST LEVELSTest Level

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONSTERMINOLOGY EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICSTHEORY OF OPERATIONUSING THE AD9410Clock Input

ANALOG INPUTDIGITAL OUTPUTSCLOCK OUTPUTS (DCO, )VOLTAGE REFERENCETIMINGDATA SYNC (DS)

OUTLINE DIMENSIONSORDERING GUIDE

Documents

10-Bit, 210 MSPS ADC AD9410 - Analog Devices · 2019. 6. 5. · 10-Bit, 210 MSPS ADC AD9410 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable