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A Memory Interleaving and Interlacing Architecture for Deblocking Filter in H.264/AVC

Yeong-Kang Lai, Member, IEEE, Lien-Fei Chen, Student Member, IEEE, and Wei-Che Chiou

IEEE Transactions on Consumer Electronics, Vol. 56, No. 4, November 2010

Reporter:Che-Ming Chang

Report Date:2011/05/20

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Outline

Introduction Algorithm Analysis of Data-Reuse for Deblocking Filter Architecture The Results Conclusion

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Introduction

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Fig. 1. Quality between non-filtered and filtered image

(a) Un-Filtered (b) Filtered

Algorithm

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Fig. 2. Flowchart for determining boundary strength

Algorithm

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Fig. 3. Principle of deblocking filter

Algorithm

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Fig. 4. Vertical and horizontal edges in one macroblock

Algorithm

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Fig.5. Edge filter flow chart.

Analysis of Data-Reuse for Deblocking Filter Ra is defined to evaluate the efficiency of the

external memory access for deblocking filter

Analysis of Data-Reuse for Deblocking Filter The memory bandwidth can be expressed as

The number of the memory reading from the external memory is 1536 (2×16×4×8+2×2×4×4×8) pixels within a MB without any data-reuse scheme.

The number of the external memory writing via the bus is 640 pixels for a MB (=16×24+2×16×8).

Each MB with 4:2:0 pictures only contains 384 (=16×16+2×8×8) unique pixels.

Ra = (1536+640)÷(2×384) = 2.83

Analysis of Data-Reuse for Deblocking Filter In this section, three data-reuse levels, Level A to

Level C, are defined to indicate the degree of the data-reuse.

Level A ： Data-Reuse Scheme for Both Vertical and Horizontal Edges

Level B ： Data-Reuse Scheme Not Only for Both Vertical and Horizontal Edges But Also for Adjacent MBs

Level C ： Data-Reuse Scheme among Adjacent MB Stripes

Analysis of Data-Reuse for Deblocking Filter Level A ： Data-Reuse Scheme for Both Vertical

and Horizontal Edges By using the on-chip buffer for local locality within

the MB, only 640/640 pixels within a MB need to be accessed from/to the external memory,respectively.

Ra = 640÷384 = 1.67

Analysis of Data-Reuse for Deblocking Filter Level B ： Data-Reuse Scheme Not Only for Both

Vertical and Horizontal Edges But Also for Adjacent MBs.

By utilizing the data-reuse of these four 4u4 blocks in the local locality, the number of the memory accesses from and to the bus can be reduced to 512 and 512,respectively.

Ra = 512÷384 = 1.33

Analysis of Data-Reuse for Deblocking Filter Level C ： Data-Reuse Scheme among Adjacent

MB Stripes In addition to the four right-side 4×4 blocks of

the left adjacent MB, the four bottom-side 4×4 blocks within the top adjacent MB can also be buffered to keep the data-reuse scheme not only for left adjacent MB but also for top adjacent MB.

Ra = 384÷384 = 1

Architecture

Memory Interleaving Organization Hybrid Schedule and Memory Configuration

Hybrid Schedule for 2-D Process Order Memory Interlacing Configuration

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Memory Interleaving Organization

Memory Interleaving Organization

Hybrid Schedule for 2-D Process Order

Memory Interlacing Configuration

The Results

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Conclusion

In this paper, a memory interleaving and interlacing architecture for deblocking filter in H.264/AVC is proposed.

The memory interleaving techniques to efficiently access data from the on-chip memory in both vertical and horizontal filter.