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General Description

The M AX1987/M AX1988 are dual-phase, Q uick-PWM ,step-down controllers for IM VP -IV C PU core supplies.

D ual-phase operation reduces input ripple current

requirements and output voltage ripple, while easing

component selection and layout difficulties. T he Q uick-

PWM control scheme provides instantaneous response to

fast load-current steps. The MAX1987/M AX1988 include

active voltage positioning with adjustable gain and offset,

reducing power dissipation and bulk output capacitance

requirements.

The M A X1987/M AX1988 are intended for two different

notebook C PU core app lications: stepping down the

battery directly or stepping down the 5V system supply

to create the core voltage. The single-stage conversion

method allows these devices to directly step down high-voltage batteries for the highest possible efficiency.

A lternatively, two-stage conversion (stepping down the

5V system supply instead of the battery) at higher

switching frequency provides the minimum possible

physical size.

The M A X1987/M A X1988 meet the IM VP -IV specifica-

tions and can directly interface with the C PU power-

good signals from the V C C P and VC C M C H rails within

the system. T he switching regulator features power-up

sequencing, automatically ramping up to the Intel-

specified boot voltage. T he M A X1987/M A X1988 also

feature independent four-level logic inputs for setting

the boot voltage (B0 to B2) and the suspend voltage

(S0 to S2).

The M A X1987/M A X1988 include output undervoltage

protection, thermal protection, and system power-O K

(SY SPO K ) input. When any of these protection features

detect a fault, the controller shuts down. Add itionally,

the M A X1987 includes overvoltage protection.

The M A X1987/M A X1988 are available in a low-profile

48-pin 7mm 7mm Thin Q FN package.

Applications

IM VP -IV Notebook C omputers

M ultiphase C PU C ore Supply

Voltage-Positioned Step-D own C onvertersServers/D esktop C omputers

Features

o Dual-Phase, Quick-PWM Controllerso 0.75% VOUT Accuracy Over Line, Load, and

Temperature

o Active Voltage Positioning with Adjustable Gainand Offset

o 6-Bit On-Board DAC (16mV Increments)

o 0.492V to 1.708V Output Adjust Range

o Selectable 200kHz/300kHz/550kHz SwitchingFrequency

o 2V to 28V Battery Input Voltage Range

o Adjustable Slew Rate Control

o Drives Large Synchronous Rectifier MOSFETs

o Output Overvoltage Protection (MAX1987 Only)

o Undervoltage and Thermal Fault Protection

o IMVP-IV Power Sequencing and Timing

o Selectable Boot and Suspend Voltages

o Low-Profile 7mm 7mm 48-Pin Thin QFNPackage

MAX1987/MAX1988

Dual-Phase, Quick -PWM Controllers for IM VP-IVCPU Core Pow er Supplies

________________________________________________________________Maxim Integrated Products 1

Ordering Information

19-2559; Rev 0; 7/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at1-888-629-4642, or visit Maxims website at www.maxim-ic.com.

Typical Operating Circuit appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX1987ETM -40C to + 100C 48 Thin Q FN 7mm 7mm

MAX1988ETM -40C to + 100C 48 Thin Q FN 7mm 7mm

VDD

DLM

LXM

BSTM

D1D2

D3

D5

D4

D0

DHMB0

B1

B2

S0

S1

S2

VCC

REF

ILIM

TON

TIME 1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

2928

27

26

25

CCI

FB

OAIN-

OAIN+

PSI

IMVPOK

SYSOK

NEG

POS

CCV

GND

CSN

CMN

CMP

SUS

V+

BSTS

LXS

DHS

PGND

DLS

CSP

7mm x 7mm THIN QFN

MAX1987

MAX1988

TOP VIEW

48

47

46

45

44

43

42

41

40

39

38

37

13

14

15

16

17

18

19

20

21

22

23

24

SHDN

CLKEN

DD0

DPSLP

Pin Configurat ion

Q uick-PW M is a tradem ark of M axim Integrated Products, Inc.

IM VP-IV is a tradem ark of Intel C orp.

CONFIDENTIAL INFORMATIONRESTRICTED TO INTEL IMVP LICENSEES

PRELIMINARY

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Dual-Phase, Quick -PWM Controllers for IMV P-IVCPU Core Pow er Supplies

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(C ircuit of Figure1, V+ = 15V, VC C = VD D = VSHDN = VTO N = VDPSLP = VPSI= VB1 = VOA I N- = 5V, VB2 = 2V, VFB = VC M P = VC M N =

VC SP = VC SN = VO A I N + = VNEG = VPO S = 1.26V, VD 4 = VD 3 = VD 2 = 1.0V, V SU S = VD 5 = VD 1 = VD 0 = VS0 = VS1 = VS2 =

VB0 = 0, TA = 0C to +85C, unless otherwise specified.)

Stresses beyond those listed under Absolute M axim um Ratings m ay cause p erm anent dam age to the d evice. These are stress ratings only, and functional

op eration of the device at these or any other cond itions beyond those ind icated in the operational sections of the specifications is not im plied . Exposure to

absolute m axim um rating conditions for extended period s m ay affect device reliability.

V+ to G ND ............................... ............................... -0.3V to +30V

VC C to G ND ............................. ............................... ..-0.3V to +6V

VDD to PG ND ........................... ............................... ..-0.3V to + 6V

PSI, SUS , IM VPOK , CLKEN, DPSLP,

SYSO K , D0D 5 to G ND ........................... .............-0.3V to + 6V

ILIM , FB , POS , NEG, C CV , CC I , REF, O A IN+ ,

O AI N- to G ND .......................... ...............-0.3V to (VC C + 0.3V)

CM P, C SP, C M N, CSN to G ND .. . .. . .. . . .. . . .. . .-0.3V to (VC C + 0.3V)

DDO, TO N, TIM E, B0, B1, B2,

S0, S1, S2 to G ND .............................. ....-0.3V to (VC C + 0.3V)

SHDNto G ND (N ote 1)........................... ................-0.3V to +18V

DLM , DLS to PG ND .... . . . .. . . . . . .. . . . . . . .. . . . . . .. . . . . .-0.3V to (V D D + 0.3V)

BST M , BSTS to G ND ............................... ...............-0.3V to + 36V

D HM to LXM .......................... .................-0.3V to (V BSTM + 0.3V)

LXM to BST M .............................. ..............................-6V to + 0.3V

D HS to LXS.......... .............................. ......-0.3V to (VBSTS + 0.3V)

LXS to BST S .......................... ............................... ....-6V to +0.3V

G ND to PG ND ............................ ...........................-0.3V to + 0.3V

REF Short-C ircuit D uration (TA = +70C ) ...................C ontinuous

C ontinuous Power Dissipation

48-P in Q FN ( derate 26.3mW/C above + 70C ) ...........2.105W

O perating Temperature R ange ..... ..... ..... ..... ..... ..-40C to +85C

Junction Temperature ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ....+ 150C

Storage Temperature R ange ..... ..... ..... ..... ..... ....-65C to + 150C

Lead Temperature (soldering, 10s) ..... ..... ..... ..... ..... ..... ...+ 300C

Note 1: SHDNmay be forced to 12V, for the purpose of debugging prototype boards using the no-fault test mode, which disables

fault protection and disables overlapping operation.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PWM CONTROLLER

Battery voltage, V+ 2 28Input-Voltage R ange

VC C , VDD 4.5 5.5V

D AC codes from1.276V to 1.708V

-0.75 + 0.75

D AC codes from

0.844V to 1.260V-1.25 + 1.25

D C O utput-Voltage Accuracy

(N ote 2)

V+ = 4.5V to 28V,

includes load

regulation error

D AC codes from

0.492V to 0.828V-3.00 + 3.00

%

Line Regulation Error VC C = 4.5V to 5.5V, V+ = 4.5V to 28V 5 mV

IFB FB -2 + 2Input Bias C urrent

IPOS, INEG PO S, N EG -0.2 + 0.2A

PO S, NEG C ommon-M ode Range DPSLP= G N D 0 2 V

PO S, NEG D ifferential Range VPO S - VNEG , DPSLP= G ND -200 + 200 mV

PO S, NEG O ffset G ain AO S

VFB/(VPO S - VNEG ) ,

(VPO S - VNEG ) = 100mV, DPSLP= G N D0.95 1.00 1.05 mV/mV

PO S, N EG Enable T ime tO S

M easured from the time DPSLPgoes low to

the time in which PO S, N EG affect a change

in the set point (VDAC )

0.1 s

640kH z nominal, R T I ME = 23.5k 580 640 700

320kH z nominal, R T I ME = 47k 295 320 345T IM E Frequency Accuracy f T I ME

64kHz nominal, R T I ME = 235k 58 64 70

kH z


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988


_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(C ircuit of Figure1, V+ = 15V, VC C = VD D = VSHDN

= VTO N = VDPSLP

= VPSI

= VB1 = VOA I N- = 5V, VB2 = 2V, VFB = VC M P = VC M N =VC SP = VC SN = VO A I N + = VNEG = VPO S = 1.26V, VD 4 = VD 3 = VD 2 = 1.0V, V SU S = VD 5 = VD 1 = VD 0 = VS0 = VS1 = VS2 =



T O N = RE F

(550kHz)155 180 205

TO N = open

(300kHz)320 355 390O n-T ime (Note 3) tO N

V+ = 12V,

VFB = VC C I = 1.2V

T O N = VC C

(200kHz)475 525 575

ns

TO N = REF (550kHz) 330 375M inimum O ff-T ime (Note 3) tO FF(M IN )

T O N = VC C or open (200kHz or 300kH z) 435 500ns

DDOD elay T ime tDDO

M easured from the time FB reaches the

voltage set by S0 to S2. C lock speed set by

R T I ME.

32 clks

SK IP Delay T ime tSKIP

M easured from the time whenDDO is

asserted to the time in which the controller

begins pulse-skipping operation

30 clks

BIAS AND REFERENCE

Q uiescent Supply C urrent (VC C ) IC CM easured at VC C , FB forced above the

regulation point1.70 2.70 mA

Q uiescent Supply C urrent (VDD ) IDDM easured at VDD , FB forced above the

regulation point< 1 5 A

Q uiescent Battery SupplyC urrent (V + )

IV+ M easured at V+ 25 50 A

Shutdown Supply Current (VC C ) M easured at VC C , SHDN= G ND 2 5 A

Shutdown Supply Current (VD D ) M easured at VDD , SHDN= G ND < 1 5 A

Shutdown Battery Supply

C urrent (V + )

M easured at V+ , SHDN= G N D ,

VC C = VD D = 0 or 5V< 1 5 A

Reference Voltage VREF VC C = 4.5V to 5.5V, IREF = 0 1.990 2.000 2.010 V

Reference Load R egulation VREF IR EF = -10A to + 100A -10 + 10 mV

FAULT PROTECTION

O utput O vervoltage P rotection

Threshold (M AX1987 O nly)VO VP M easured at FB 1.95 2.00 2.05 V

O utput O vervoltage Propagation

D elay (M AX1987 O nly) tO VP FB forced above 2.05V 10 s

O utput U ndervoltage Protection

ThresholdVUVLO

M easured at FB with respect to unloaded

output voltage67 70 73 %

O utput Undervoltage Propagation

DelaytUVP FB forced 2% below trip threshold 10 s


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4 _______________________________________________________________________________________



= VTO N = VDPSLP

= VPSI




Lower threshold

(undervoltage)-13 -10 -7

I M V P O K , CLKENThreshold

VSYSPOK = 5V;

measured at FB with

respect to unloaded

output voltageU pper threshold

(overvoltage)+ 7 + 10 + 13

%

CLKEND elay tCLKENFB in regulation, measured from the rising

edge of SYSP O K30 50 90 s

O utput Fault, IM VPO K , and

CLKENTransition Blanking TimetBLANK

M easured from the time when FB reaches

the voltage set by the DAC code, clock

speed set by R T I ME (N ote 4)

32 clks

IM VPO K Delay tI MV POKFB in regulation, measured from the falling

edge ofCLKEN3 5 7 ms

I M V P O K , CLKENO utput Low

VoltageISINK = 3mA 0.3 V

I M V P O K , CLKENLeakage

C urrentHigh state, IM VPO K , CLKENforced to 5.5V 1 A

VC C Undervoltage L ockout

Threshold

VUVLO

(V C C )

R ising edge, hysteresis = 90mV, PWM

disabled below this level4.0 4.2 4.4 V

T hermal Shutdown T hreshold TSHDN H ysteresis = 15C 160 C

CURRENT LIMIT AND BALANCE

C urrent-Limit Threshold Voltage(Positive, Default)

VL IM IT CM P - CM N, CSP - CSN; ILIM = VC C 27 30 33 mV

V ILIM = 1V 47 50 53C urrent-Limit Threshold Voltage

(Positive, Adjustable)VL IM IT

C M P - C M N ,

C SP - C SN V ILIM = 1.5V 72 75 78mV

C urrent-Limit Threshold Voltage

(Negative)

VL IM IT

(NEG)

CM P - CM N, CSP - CSN; ILIM = VC C ,

SUS = G ND, and DPSLP= PSI= VC C-30 -36 -42 mV


(Zero-C rossing)VZERO

CM P - CM N, CSP - CSN; SUS = VC C or

DPSLP= G N D orPSI= G N D1.5 mV

C M P , C MN , C S P,

C SN I nput Ranges0 2 V

C M P , C MN , C S P,

C SN Input C urrentVC SP = VC SN = 0 to 5V -2 + 2 A

ILIM Input C urrent I ILIM V ILIM = 0 to 5V 0.1 200 nA

C urrent-Limit D efault Switchover

ThresholdILIM 3

VC C -

1

VC C -

0.4V

C urrent-Balance O ffset VOS(IBAL)

(VC M P - VC M N ) - (VC SP - VC SN ) ;

IC C I = 0, -20mV < (V C M P - VC M N ) < +20mV,

0.5V < VC C I < 2.8V

-2.0 + 2.0 mV


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988


_______________________________________________________________________________________ 5



= VTO N = VDPSLP

= VPSI




C urrent-Balance

TransconductancegM( IBAL ) 400 S

GATE DRIVERS

DH_ Gate-Dri ver O n-Resistance RON (D H ) BST_ - LX_ forced to 5V 1.0 4.5

H igh state (pullup) 1.0 4.5DL_ G ate-Dri ver O n-Resistance RON (D L )

Low state (pulldown) 0.4 2.0

D H_ G ate-Driver Source/Sink

C urrentIDH

D H_ forced to 2.5V,

BS T_ - LX _ forced to 5V1.6 A

D L_ G a te-D river Sink C urrent IDL(SINK) D L_ forced to 5V 4 A

DL_ G ate-Driver Source Current IDL(SO URC E) D L_ forced to 2.5V 1.6 A

D L_ rising 35D ead T ime tDEAD

D H_ rising 26ns

VOLTAGE-POSITIONING AMPLIFIER

Input O ffset Voltage VO S -1.5 + 1.5 mV

Input Bias C urrent IBIAS O A IN + , O A IN - 0.1 200 nA

O p Amp D isable Threshold O A IN - 3VC C -

1

VC C -

0.4V

C ommon-M ode I nput-Voltage

RangeVC M G uaranteed by C M RR test 0 2.5 V

C ommon-M ode Rejection Ratio C M RR VOA I N+ = VOA I N- = 0 to 2.5V 70 100 dB

Power-Supply Rejection Ratio PSRR VC C = 4.5V to 5.5V 75 100 dB

Large-Signal Voltage G ain AO A R L = 1k to VC C /2 70 112 dB

VC C - VFBH 77 300

O utput-Voltage Swing(VOA I N+ - VOA I N-) 10mV,

R L = 1k to VC C /2VFBL 47 200

mV

Input C apacitance 11 pF

G ain-Bandwidth Product 3 M H z

Slew Rate 0.3 V/s

C apacitive Load Stability N o sustained oscillations 400 pF

LOGIC AND I/O

Logic-Input H igh Voltage VIH SUS, DPSLP, SHDN, SYSPO K 2.4 V

Logic-Input Low Voltage V IL SUS, DPSLP, SHDN, SYSPO K 0.8 V

Logic-Input C urrent SUS, DPSLP, SHDN, SYSPO K -1 + 1 A


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6 _______________________________________________________________________________________



= VTO N = VDPSLP

= VPSI




SHDNNo-Fault Threshold To enable no-fault mode 12 15 V

1V Logic-Input H igh Voltage D0D5, PSI 0.7 V

1V Logic-Input Low Voltage D0D5, PSI 0.3 V

DAC Input C urrent D0D5, PSI -1 + 1 A

Driver Di sable O utput High

VoltageDDO, IL OA D = 1mA 2.4 V

Driver D isable O utput Low

VoltageDDO, IL OA D = 1mA 0.3 V

H igh VC C - 0.4O pen 3.15 3.85

REF 1.65 2.35Four-Level Input Logic Levels

TO N, S0 to S2,

B0 to B2

Low 0.5

V

Four-Level Input C urrentTO N, S0 to S2, B0 to B2 forced to

G ND or VC C-4 + 4 A

ELECTRICAL CHARACTERISTICS(C ircuit of Figure 1, V+ = 15V, VC C = VDD = VSHDN = VTO N = VDPSLP= VPSI= VB1 = VOA I N- = 5V, VB2 = 2V, VFB = VC M P = VC M N =

VC SP = VC SN = VO A I N + = VNEG = VPO S = 1.26V, VD 4 = VD 3 = VD 2 = 1.0V, V SU S = VD 5 = VD 1 = VD 0 = VS0 = VS1 = VS2 =

VB0 = 0, TA = -40C to +100C, unless otherwise speci fied. ) ( N ote 5)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITSPWM CONTROLLER

Battery voltage, V+ 2 28Input-Voltage R ange

VC C , VDD 4.5 5.5V

DAC codes from

1.276V to 1.708V-1.00 + 1.00

DAC codes from

0.844V to 1.260V-1.50 + 1.50

D C O utput-Voltage Accuracy

(N ote 2)

V+ = 4.5V to 28V,

includes load

regulation error

DAC codes from

0.492V to 0.828V-3.5 + 3.5

%

PO S, NEG O ffset G ain AO FFVFB/(VPO S - VNEG ) ,

(VPO S - VNEG ) = 100mV, DPSLP= G N D0.95 1.05 mV/mV

640kH z nominal, R T I ME = 23.5k 580 700

320kH z nominal, R T I ME = 47k 295 345T IM E Frequency Accuracy f T I ME

64kHz nominal, R T I ME = 235k 58 70

kH z

TO N = REF (550kHz) 155 205

TO N = open (300kHz) 320 390O n-T ime (Note 3) tO NV+ = 12V,

VFB = VC C I = 1.2VT O N = VC C (200kHz) 475 575

ns


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988


_______________________________________________________________________________________ 7


(C ircuit of Figure 1, V+ = 15V, VC C = VDD = VSHDN

= VTO N = VDPSLP

= VPSI



PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

TO N = REF (550kHz) 375M inimum O ff-Time

(N ote 3)tOFF(MIN ) T O N = VC C or open

(200kHz or 300kHz)500

ns

BIAS AND REFERENCE

Q uiescent Supply Current (VC C ) IC CM easured at VC C , FB forced above the

regulation point3.00 mA

Q uiescent Supply Current (VDD ) IDDM easured at VDD , FB forced above the

regulation point30 A

Q uiescent Battery SupplyC urrent (V + )

IV+ M easured at V+ 50 A

Shutdown Supply Current (VC C ) M easured at VC C , SHDN= G ND 20 A

Shutdown Supply Current (VDD ) M easured at VDD , SHDN= G ND 20 A

Shutdown Battery Supply

C urrent (V + )

M easured at V+ , SHDN= G N D,

VC C = VDD = 0 or 5V20 A

Reference Voltage VREF VC C = 4.5V to 5.5V, IREF = 0 1.985 2.015 V

FAULT PROTECTION

O utput O vervoltage P rotection

Threshold (M AX1987 O nly)M easured at FB 1.95 2.05 V

O utput U ndervoltage Protection

Threshold

M easured at FB with respect to unloaded

output voltage67 73 %

Lower threshold

(undervoltage)-13 -7

I M V P O K , CLKENThreshold

VSYSPOK = 5V;

measured at FB with

respect to unloaded

output voltageUpper threshold

(overvoltage)7 13

%

CLKEND elay tCLKENFB in regulation, measured from the rising

edge of SYSP O K30 s

IM VPO K Delay tI MV POKFB in regulation, measured from the falling

edge ofCLKEN3 ms

VC C Undervoltage L ockout

Threshold

VUVLO

(V C C )

R ising edge, hysteresis = 90mV, PWM

disabled below this level3.95 4.45 V

CURRENT LIMIT AND BALANCE

C urrent-Limit T hreshold Voltage

(Positive, Default)VL IM IT CM P - CM N, CSP - CSN; ILIM = VC C 25 35 mV

V ILIM = 1V 45 55C urrent-Limit T hreshold Voltage

(Positive, Adjustable)VL IM IT

C M P - C M N ,

CSP - C SNV ILIM = 1.5V 70 80

mV


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8 _______________________________________________________________________________________


(C ircuit of Figure 1, V+ = 15V, VC C = VDD = VSHDN

= VTO N = VDPSLP

= VPSI



PARAMETER SYMBOL CONDITIONS MIN MAX UNITS


(Negative)

VL IM IT

(NEG)

CM P - CM N, CSP - CSN; ILIM = VC C ,

SUS = G ND and DPSLP= VC C-27 -45 mV

C urrent-Balance O ffset VOS(IBAL)

(VC M P - VC M N ) - (VC SP - VC SN ) ; I C C I = 0,

-20mV < (V C M P - VC M N ) < 20mV,

0.5V < VC C I < 2.8V

-3 + 3 mV

GATE DRIVERS

DH_Gate-Dri ver On-Resistance R ON (D H ) BST_ - LX_forced to 5V 4.5

H igh state (pullup) 4.5DL _Gate-Dri ver O n-Resistance R ON (D L )

Low state (pulldown) 2.0

VOLTAGE-POSITIONING AMPLIFIER

Input O ffset Voltage VO S -2.5 + 2.5 mV

C ommon-M ode Input

Voltage RangeVC M G uaranteed by C M RR test 0 2.5 V

VC C - VFBH 300O utput-Voltage Swing

(VOA I N+ - VOA I N-) 10mV,

R L = 1k to VC C /2 VFBL 200mV

LOGIC AND I/O

Logic-Input H igh Voltage VIH SUS, DPSLP, SHDN, SYSPO K 2.4 V

Logic-Input Low Voltage V IL SUS, DPSLP, SHDN, SYSPO K 0.8 V

1V Logic-Input H igh Voltage D 0D 5, PSI 0.7 V

1V Logic-Input Low Voltage D 0D 5, PSI 0.3 V

H igh VC C - 0.4

O pen 3.15 3.85

REF 1.65 2.35Four-Level Input Logic Levels

TO N, S0 to S2,

B0 to B2

Low 0.5

V

Note 2: DC output accuracy speci fications refer to the trip level of the error amplifier. T he output voltage has a D C regulation higher

than the trip level by 50% of the output ripp le. When pulse-skipping, the output rises by approximately 1.5% when transition-

ing from continuous conduction to no load.

Note 3: O n-time and minimum off-time specifications are measured from 50% to 50% at the DH M and D HS pins, with LX _ forced to

G N D , B ST _ forced to 5V, and a 500pF capacitor from DH _ to LX _ to simulate external M O SFET gate capacitance. Actual in-

circuit times can be different due to M O SFET switching speeds.

Note 4: The output fault-blank ing time is measured from the time when FB reaches the regulation voltage set by the DAC code.

During power-up, the regulation voltage is set by the boot D AC code (B 0 to B2) . D uring normal operation (SU S = G ND ) , the

regulation voltage is set by the VI D D AC inputs (D 0D 5). D uring suspend mode (SU S = VC C

), the regulation voltage is set

by the suspend D AC inputs (S0 to S2).

Note 5: Specifications to TA = -40C to + 100C are guaranteed by design and are not production tested.


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_______________________________________________________________________________________ 9

OUTPUT VOLTAGE vs. LOAD CURRENT

(VOUT = 1.356V)

M

AX1987/88toc01

LOAD CURRENT (A)

OUTPUTVOLTAGE(V)

302010

1.20

1.25

1.30

1.35

1.40

1.150 40

EFFICIENCY vs. LOAD CURRENT

(VOUT = 1.356V)

M

AX1987/88toc02

LOAD CURRENT (A)

EFFICIENCY(%)

101

60

70

80

90

100

500.1 100

VIN = 12V

VIN = 8V

VIN = 20V

PSI = GNDPSI = VCC


(VOUT = 0.844V)

M

AX1987/88toc03

LOAD CURRENT (A)

OUTPUTVOLTAGE(V)

252015105

0.75

0.78

0.80

0.83

0.85

0.88

0.730 30


(VOUT = 0.844V)

M

AX1987/88toc04

LOAD CURRENT (A)

EFFICIENCY(%)

101

60

70

80

90

100

500.1 100

VIN = 12V

VIN = 8V

VIN = 20V

PSI = GNDPSI = VCC


(VOUT = 0.748V)

M

AX1987/88toc05

LOAD CURRENT (A)

OUT

PUTVOLTAGE(V)

15105

0.68

0.69

0.70

0.71

0.72

0.73

0.74

0.75

0.76

0.77

0.670 20

SUS = VCC


(VOUT = 0.748V)

M

AX1987/88toc06

LOAD CURRENT (A)

EFFICIENCY(%)

101

60

70

80

90

100

500.1 100

VIN = 12V

VIN = 8V

VIN = 20V

PSI = GNDPSI = VCC

-5

-2

-3

-4

0

-1

4

3

2

1

5

-40 -20 0 20 40 60 80 100

REFERENCE VOLTAGE SHIFT

vs. TEMPERATURE

M

AX1987/88toc07

TEMPERATURE (C)

VREF(mV)

SWITCHING FREQUENCY

vs. LOAD CURRENT

M

AX1987/88toc08

LOAD CURRENT (A)

SWITCHINGFREQU

ENCY(kHz)

302010

100

200

300

400

00 40

FORCED-PWM (VPSI = 5V)

SKIP MODE (VPSI = 0)

220

240

280

260

300

320

0 105 15 20 25 30

SWITCHING FREQUENCY

vs. INPUT VOLTAGE

M

AX1987/88toc09

INPUT VOLTAGE (V)

FREQUENCY

(kHz)

IOUT = 20A

NO LOAD

Typical Operating Charact eristics

(C ircuit of Figure 1, V+ = 12V, VC C = VD D = 5V , SUS = G ND,SHDN

=DPSLP

=PSI

= VC C , B0 to B2 set for 1.372V, S0 to S2 set for0.748V, TA = + 25C , unless otherwise speci fied. )


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10 ______________________________________________________________________________________

OUTPUT OFFSET VOLTAGE vs.

POS-NEG DIFFERENTIAL VOLTAGE

M

AX1987/88toc14

POS-NEG DIFFERENTIAL VOLTAGE (mV)

OUTPUTOFF

SETVOLTAGE(mV)

4002000-200-400

-400

-200

0

200

400

600

-600-600 600

60

-4 0

0.1 10 100 10001 10,000

VOLTAGE-P OSITIONING AM PLIFI ER

GAIN AND PHASE vs. FREQUENCY

-2 0

-1 0

0

-3 0

MAX1987/88 toc18

FREQUENCY (kHz)

GAIN(dB)

PHASE(DEGREES)

10

20

30

40

50

180

-180

-108

-7 2

-3 6

-144

0

36

72

108

144

GAIN

PHASE

Typical Operating Characteristics (continued)

(C ircuit of Figure 1, V+ = 12V, VC C = VDD = 5V , SUS = G ND, SHDN= DPSLP= PSI= VC C , B0 to B2 set for 1.372V, S0 to S2 set for0.748V, TA = +25C , unless otherwise speci fied. )

200

240

220

280

260

320

300

340

-40 0 20-20 40 60 80 100

SWITCHING FREQUENCY

vs. TEMPERATURE

M

AX1987/88toc10

TEMPERATURE (C)

FREQUENCY(kHz)

NO LOAD

20A NO LOAD

VOUT = 1.356V

35

36

38

37

39

40

-40 0-20 20 40 60 80 100

OUTPUT CURRENT AT CURRENT LIM IT

vs. TEMPERATURE

M

AX1987/88toc11

TEMPERATURE (C)

MAXIMUML

OADCURRENT(A)

0

20

60

40

80

100

0 105 15 20 25 30

NO LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

(FORCED-PWM MODE)

M

AX1987/88toc12

INPUT VOLTAGE (V)

SUPPLYCURRENT(mA)

ICC + IDD

I+

PSI = VCC

0

0.5

1.5

1.0

2.0

2.5

0 105 15 20 25 30

NO LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

(PULSE SKIPPING)

M

AX1987/88toc13

INPUT VOLTAGE (V)

SUPPLYCURRENT(mA)

ICC + IDD

I+

PSI = GND

0

10

20

30

40

50

0.834 0.839 0.844 0.849 0.854

0.844V OUTPUT-VOLTAGE DISTRIBUTION

M

AX1987/88toc15

OUTPUT VOLTAGE (V)

SAMPLEP

ERCENTAGE(%)

0

5

15

10

20

25

1.995 1.9991.997 2.001 2.003 2.005

REFERENCE VOLTAGE DISTRIBUTION

M

AX1987/88toc16

REFERENCE VOLTAGE (V)

SAMPLEPERCENTA

GE(%)

0

10

5

20

15

25

30

0.98 1.000.99 1.01 1.02

POS-NEG OFFSET GAIN

DISTRIBUTION

M

AX1987/88toc17

POS-NEG OFFSET GAIN

SAMPEPERCENTA

GE(%)


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VPS AM PLIFI ER OFFSET VOLTAGE

vs. COMMON-MODE VOLTAGE

M

AX1987/88toc19

COMMON-MODE VOLTAGE (V)

OFFSETVOLTAGE(V)

4321

20

40

60

80

100

120

140

160

180

00 5

VPS AMPLIFIERDISABLED

POWER-UP SEQUENCEMAX1987/88 toc21

100 s/div

0A

B

C

D

5V

0

5V

0

0

5V

BOOT

VID

A. VSHDN = 0 TO 5V, 5V/divB. VOUT = 0 TO 1.372V TO 0.844V, 500mV/divC. CLKEN, 5V/divD. DDO, 5V/div

RLOAD = 80m

SOFT-STARTMAX1987/88 toc22

100 s/div

0A

B

C

D

5V

0

10A

0

0

BOOT

VID

A. VSHDN = 0 TO 5V, 5V/divB. VOUT = 0 TO 1.372V TO 0.844V, 500mV/divC. I LM , 10A/divD. I LS, 10A/div

RLOAD = 80m

SYSTEM POWER-OKMAX1987/88 toc23

20s/div

0

A

B

C

D

5V

0

5V

BOOT(1.372V)

HIGH FREQ VID(1.356V)

LOW FREQ VID(0.844V)

A. VSYSPOK = 0 TO 5V, 5V/divB. HIGH FREQ: VOUT = 1.356V, 200mV/divC. LOW FREQ: VOUT = 0.844V, 200mV/divD. CLKEN, 5V/div

IM VPOK DELAYMAX1987/88 toc24

1ms/div

0

0

A

B

C

D

5V

0

0

5V

5V

BOOT(1.372V)

A. VSHDN = 0 TO 5V, 5V/divB. VOUT = 0 TO 0.844V, 1V/divC. CLKEN, 5V/divD. IMVPOK, 5V/div



=DPSLP

=PSI


0

0.2

0.6

0.4

0.8

1.0

INDUCTOR CURRENT DIFFERENCE

vs. LOAD CURRENT

M

AX1987/88toc20

LOAD CURRENT (A)

IL(CS)-IL(CM)

0 2010 30 40

PSI = GNDPSI = VCC


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SHUTDOWN SEQUENCEMAX1987/88 toc25

40s/div

00.84V

0

0

A

B

C

D

E

5V

5V

05V

05V

A. VSHDN = 5V TO 0, 5V/divB. VOUT = 0.844V TO 0, 500mV/divC. CLKEN, 5V/divD. IMVPOK, 5V/divE. DDO, 5V/div

RLOAD = 80m

SOFT SHUTDOWNMAX1987/88 toc26

40s/div

0

0.84V

0

A

B

C

D

5V

0

0

A. VSHDN = 5V TO 0, 5V/divB. VOUT = 0.844V TO 0, 500mV/divC. I LM , 10A/divD. I LS, 10A/div

RLOAD = 80m

LOAD TRANSIENT

(VOUT = 1.356V)MAX1987/88 toc27

40s/div

0

1.356V

A

B

C

D

25A

0

0

A. IOUT = 0 TO 25A, 20A/divB. VOUT = 1.356V TO 1.281V, 50mV/divC. ILM , 10A/divD. ILS, 10A/div

LOAD TRANSIENT

(VOUT = 0.844V)MAX1987/88 toc28

40s/div

0

0.844V

A

B

C

D

10A

0

0

A. IOUT = 0 TO 10A, 10A/divB. VOUT = 0.844V TO 0.814V, 20mV/divC. I LM , 10A/div

D. I LS, 10A/div

ENTERING DEEP-SLEEP MODEMAX1987/88 toc29

20s/div

0

1.350V

1.318V

A

B

C

D

5V

0

0

A. VDPSLP = 5V TO 0, 5V/divB. VOUT = 1.350V TO 1.318V, 50mV/divC. LXM, 10V/div

D. LXS, 10V/divSUS = GND, IOUT = 1A

EXITI NG DEEP-SLEEP MODEMAX1987/88 toc30

20s/div

0

1.351V

1.318V

A

B

C

D

5V

0

0

A. VDPSLP = 0 TO 5V, 5V/divB. VOUT = 1.318V TO 1.351V, 50mV/divC. LXM, 10V/div

D. LXS, 10V/divSUS = GND, IOUT = 1A


(C ircuit of Figure 1, V+ = 12V, VC C = VDD = 5V , SUS = G ND, SHDN= DPSLP= PSI= VC C , B0 to B2 set for 1.372V, S0 to S2 set for0.748V, TA = +25C , unless otherwise speci fied. )


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DEEP-SLEEP TRANSITIONMAX1987/88 toc31

40s/div

0

1.350V

1.318V

A

B

C

D

5V

0

0

A. VDPSLP = 5V TO 0, 5V/divB. VOUT = 1.350V TO 1.318V, 50mV/divC. I LM , 10A/divD. I LS, 10A/div

SUS = GND, IOUT = 1A

ENTERING SUSPEND MODEMAX1987/88 toc32

40s/div

0

0.751V

1.318V

A

B

C

D

5V

0

0

A. VSUS = 0 TO 5V, 5V/divB. VOUT = 1.318V TO 0.751V, 500mV/divC. LXM, 10V/divD. LXS, 10V/div

DPSLP = GND, IOUT = 1.0A

EXITI NG SUSPEND M ODEMAX1987/88 toc33

40s/div

0

0.751V

1.318V

A

B

C

D

5V

0

0

A. VSUS = 5V TO 0, 5V/divB. VOUT = 0.751V TO 1.318V, 500mV/divC. LXM, 10V/divD. LXS, 10V/div

DPSLP = GND, IOUT = 1A

SUSPEND TRANSITIONMAX1987/88 toc34

100 s/div

0

0.751V

1.318V

A

B

C

D

5V

0

0

A. VSUS = 0 TO 5V, 5V/divB. VOUT = 1.318V TO 0.751V, 500mV/divC. ILM , 10A/div

D. ILS, 10A/divDPSLP = GND, IOUT = 1A

MAX1987/88 toc35

20s/div

0

1.356V

A

B

C

D

5V

0

0

A. VPSI = 5V TO 0, 5V/divB. VOUT = 1.356V, 50mV/divC. LXM, 10V/div

D. LXS, 10V/divIOUT = 1A

PSI T RANSITION



=DPSLP

=PSI



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Pin Description

MAX1987/88 toc37

20s/div

0

1.356V

1.228V

A

B

C

D

1V

0

0

A. VD3 = 0 TO 1V, 1V/divB. VOUT = 1.356V TO 1.228V, 100mV/divC. I LM , 10A/divD. I LS, 10A/div

DYNAMIC VID TRANSITION

(D3 = 128mV)



=DPSLP

=PSI


MAX1987/88 toc36

20s/div

0

1.356V

1.340V

A

B

C

D

1V

0

0

A. VD0 = 0 TO 1V, 1V/divB. VOUT = 1.356V TO 1.340V, 20mV/divC. ILM , 10A/divD. ILS, 10A/div

DYNAMIC VID TRANSITION

(D0 = 16mV)

PIN NAME FUNCTION

1 TIM ESlew-Rate Adjustment P in. C onnect a resistor from T IM E to G ND to set the internal slew-rate clock. A 235k

to 23.5k resistor sets the clock from 64kH z to 640kHz, fSLEW = 320kHz 47k/RT I ME.

2 TO N

O n-T ime S election Control Input. T his four-level input sets the K-factor value (Table 3) used to determine the

D H on-time (see the O n-Tim e O ne-Shotsection): G N D = 1000kH z (untested), REF = 550kHz,

open = 300kHz, V C C = 200kH z per phase

3, 4, 5B0, B1,

B2

Boot-M ode Voltage Select Inputs. B0 to B2 are four-level digi tal inputs that select the boot-mode VI D code

(Table 6) for the boot-mode multiplexer inputs. During power-up, the boot-mode V ID code is delivered to the

D AC (see the Internal M ultiplexers section).

6, 7, 8S0, S1,

S2

Suspend-Mode V oltage Select Inputs. S0 to S2 are four-level dig ital inputs that select the suspend-mode V ID

code ( Table 5) for the suspend-mode multiplexer inputs. If SU S is high, the suspend-mode V ID code is

delivered to the D AC (see the Internal M ultiplexers section), overriding any other voltage setting (Figure 9).

9 SHDN

Shutdown Control Input. T his input cannot withstand the ba ttery voltage. C onnect to VC C for normal

operation. C onnect to ground to put the IC into its 1A shutdown state. D uring the transition from normal

operation to shutdown, the output voltage is ramped down at the output voltage slew rate programmed by

the TI M E pin. I n shutdown mode, D LM and DL S are forced to VD D to clamp the output to ground. Forcing

SHDNto 12V~ 15V disables both overvoltage protection and undervoltage protection circuits, disables

overlap operation, and clears the fault latch. D o not connectSHDNto >15V.

10 REF

2V R eference O utput. Bypass to GN D with a 0.22F or greater ceramic capaci tor. The reference can source

100A for external loads. L oadi ng REF degrades output-voltage accuracy according to the REF load

regulation error.

11 ILIM

C urrent-Limit A djustment. T he current-limit threshold defaults to 30mV if I LI M is connected to VC C . I n

adjustable mode, the current-limit threshold voltage is precisely 1/20th the voltage seen at IL IM over a

200mV to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately VC C - 1V.


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Pin Description (continued)

PIN NAME FUNCTION

12 VC CAnalog Supply Voltage Input for PWM C ore. Connect VC C to the system supply voltage (4.5V to 5.5V) with a

series 10 resistor. B ypass to G ND with a 1F or greater ceramic capaci tor, as close to the IC as possible.

13 G N D A nalog G round. C onnect the M A X 1987/M A X 1988s exposed pad to analog ground.

14 C C VVoltage Integrator Capacitor C onnection. C onnect a 47pF to 1000pF (270pF typ) capacitor from C C V to

analog ground (G ND ) to set the integration time constant.

15 PO S

Feedback O ffset Ad just Positive Input. T he output shifts by 100% (typ) of the differential input voltage

appearing between PO S and N EG whenDPSLPis low. The common-mode range of PO S and N EG is 0 to

2V. P O S and N EG should be generated from resistor-div iders from the output.

16 NEG

Feedback O ffset Adjust Negative I nput. The output shifts by 100% ( typ) of differential input voltage

appearing between PO S and N EG whenDPSLPis low. The common-mode range of PO S and N EG is 0 to

2V. P O S and N EG should be generated from resistor-div iders from the output.

17 C C IC urrent Balance C ompensation. C onnect a 470pF capacitor between C C I and FB (see theC urrent BalanceC om pensation section) . An addi tional 470k to 1M resistor between C C I and FB for low-frequency

operation.

18 FB

Feedback Input. FB is internally connected to both the feedback input and the output of the voltage-

positioning op amp ( Figure 2). C onnect a resistor between FB and O A IN - (Figure 1) to set the voltage-

positioning gain (see the Setting Voltage Positioningsection).

19 O A IN-

D ual-M ode O p A mp Inverting Input and O p A mp D isable Input. When using the internal op amp for

add itional voltage-positioning ga in ( Figure 1) , connect to the negative terminal of the current-sense resistor

through a 1.0k1% resistor as described in the Setting Voltage Positioningsection. C onnect OA IN - to VC Cto disable the op amp. The logic threshold to disable the op amp is approximately VC C - 1V.

20 O A IN +

O p Amp N oninverting Input. When using the internal op amp for addi tional voltage-positioning ga in

(Figure 1), connect to the positive terminal of the current-sense resistor through a resistor as describ ed in the

Setting Voltage Positioningsection.

21 PSI Power-Status Indicator Input. When PSI is pulled low, the M AX1987/M AX1988 immediately enter pulse-skipping operation, blank the IM VP O K output high, and blank theCLKENoutput low.

22 SYSPO K

System Power-G ood Input. P rimarily, SY SPO K serves as the wired N O R junction of the open-drain power-

good signals for the VC C P and VC C M C H supplies. A falling edge on SY SP O K shuts down the

M AX1987/MAX1988 and sets the fault latch. T oggle SHDNor cycle VC C power below 1V to restart the

controller.

23 IM VPO K

O pen-D rain Power-G ood O utput. A fter output voltage transitions, except during power-up and power-down,

if O UT is in regulation, then IM VP O K is high impedance. IM VP O K is high impedance whenever the slew rate

control is active (output voltage transitions) . I M VP O K is forced low in shutdown. A pullup resistor on IM VP O K

causes additional finite shutdown current. I M VP O K also reflects the state of SYSPO K and includes a 3ms

(min) delay for power-up.

24 CLKENC lock Enable Logic O utput. This inverted logic output indicates when SYSPO K is high and the output voltage

sensed at FB is in regulation. CLKENis forced low during VID transitions.

2530 D 5D0

Low-Voltage VI D DAC C ode Inputs. D 0 is the LSB, and D5 is the M SB of the internal 6-bit VID DAC (T able 4).

The D0D 5 inputs do not have internal pullups. T hese 1.0V logic inputs are designed to interface directly with

the C PU . In all normal active modes (modes other than suspend mode and boot mode) , the output voltage is

set by the VID code indicated by the D 0D 5 logic-level voltages on D0D5. In suspend mode (SU S = high),

the decoded state of the four-level S0 to S2 inputs sets the output voltage. I n boot mode (see the Pow er-U p

Sequence section), the decoded state of the four-level B0 to B2 inputs set the output voltage.


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Pin Description (continued)

PIN NAME FUNCTION

31 DDO

D river-D isable O utput. T his TT L logi c output can be used to disable the driver outputs on slave-switching

regulator controllers, such as the M AX1980 forcing a high-impedance condition and making it possible for

the MAX1987/M AX1988 master controller to operate in low-current SK IP mode. DDOgoes low 32 R T I ME

clock cycles after the M AX1987/M AX1988 complete a transition to the suspend mode or deep-sleep voltage

(see the Low -Pow er Pulse Skippingsection) . A nother 32 clock cycles later, the M AX1987/M AX1988 enter

automatic pulse-skipping operation.

32 BSTMM ain B oost Flying C apacitor C onnection. A n optional resistor in series with BST M allows the D H M pullup

current to be adjusted.

33 LXM M ain Inductor Connection. LXM is the internal lower supply rai l for the DHM high-side gate driver.

34 D H M M a in H igh-Side G a te-D river O utput Swings L XM to B ST M

35 DLM

M ain Low-Side G ate D river O utput. D LM swings from PG ND to VD D . D LM is forced high after the

M AX1987/MAX1988 power down (SHDN

= G ND ) or when the M AX1987 detects an overvoltage fault. T heM AX1988 does not include overvoltage protection.

36 VDDSupply Voltage Input for the DLM and D LS G ate Drivers. Connect to the system supply voltage (4.5V to

5.5V). Bypass VDD to PG ND with a 2.2F or greater ceramic capacitor, as close to the IC as possible.

37 PG N D Power G round. G round connection for the low-side gate drivers DLM and D LS.

38 D LS

Secondary Low-Side G ate Driver O utput. DL S swings from PG N D to VDD . D LS is forced high after the

M AX1987/MAX1988 power down (SHDN= G ND ) or when the M AX1987 detects an overvoltage fault. T he

M AX1988 does not include overvoltage protection.

39 DHS Secondary H igh-S ide G ate-Dri ver Output Swings LXS to BSTS

40 LXS Secondary Inductor Connection. LXS is the internal lower supply rail for the DHS high-side gate driver.

41 BSTSSecondary Boost Flying C apacitor Connection. A n optional resistor in series with BST S allows the D HS pullup

current to be adjusted.

42 V+ Battery Voltage S ense Connection. U sed only for PWM one-shot timing. D H _ on-time is inversely proportionalto input voltage over a range of 2V to 28V.

43 SUS

Suspend-Mode C ontrol Input. When SU S is high, the regulator slews to the suspend voltage level. This level

is set with four-level logic signals at the S0 to S2 inputs. 32 clock cycles after the transition to the suspend-

mode voltage is completed, DDOgoes low (see the Low -Pow er Pulse Skippingsection) . A nother 32 clock

cycles later, the MAX1987/M AX1988 are allowed to enter pulse-skipping operation.

44 DPSLP

D eep-Sleep Control Input. When DPSLPis low, the system enters the deep-sleep state and the regulator

applies the appropriate deep-sleep offset. T he M AX1987/M AX1988 add the offset measured at the P O S and

N EG pins to the output. 32 clock cycles after the deep-sleep transition is completed, DDOgoes low (see the

Low -Pow er Pulse Skippingsection). A nother 32 clock cycles later, the M AX1987/M AX1988 are allowed to

enter pulse-skipping operation.

45 C M P M a in I nductor P ositive C urrent-Sense Input

46 C M N M a in I nductor N egative C urrent-Sense Input

47 CSN Secondary Inductor Negati ve Current-Sense Input

48 CSP Secondary Inductor Posi ti ve Current-Sense Input


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Table 1. Component Selection for Standard Multiphase Applications (Figure 1)

DESIGNATION COMPONENT

Input Voltage Range* 7V to 24V

VID O utput Voltage (D 5D0) 1.356V (D5D0 = 010110)

Boot Voltage (B0 to B2) 1.372V (B2 = REF, B1 = REF, B0 = REF)

Suspend Voltage (S0 to S2) 0.748V (S2 = VC C , S1 = VC C , S0 = GN D)

Deep-Sleep O ffset Voltage (PO S, N EG ) 2.7%

M aximum Load C urrent ( typ) 40A

Inductor (LM , LS)0.6H

Panasonic ETQ P1H 0R6BFA or Sumida C DEP134H-0R6

Switching Frequency 300kHz (TO N = float)

High-Side MO SFET (N H , per phase) Fairchild (2) FDS6694 or Siliconix (2) Si4860D Y

Low-Side MO SFET (N L , per phase) Fairchild (2) FDS6688 or Siliconix (2) Si4362D Y

Input C apacitance (C IN )(6) 10F, 25V

Taiyo Yuden TM K 432BJ106K M or TD K C 4532X5R1E106M

O utput Capacitance (C O UT )(3) 470F, 2.5V Sanyo 2R5TP D 470M or

(4) 330F, 2.5V Panasonic EEFUEO D 33IXR

C urrent-Sense R esistor ( RSENSE, per phase)1.5m

Panasonic ERJM 1WTJ1M 5U

*Input voltages less than 7V require additional input capacitance.

Table 2. Component Suppliers

MANUFACTURER PHONE WEBSITE

BI Technologies 714-447-2345 (USA ) www.bitechnologies.com

C entral Semiconductor 631-435-1110 (USA ) www.centralsemi.com

C oilcraft 800-322-2645 (USA ) www.coilcraft.com

C oiltronics 561-752-5000 (USA ) www.coiltronics.com

Fairchild Semiconductor 888-522-5372 (USA ) www.fairchildsemi.com

International Rectifier 310-322-3331 (USA ) www.irf.com

K emet 408-986-0424 (USA ) www.kemet.com

Panasonic 847-468-5624 (USA ) www.panasonic.com

Sanyo65-281-3226 (Singapore)

408-749-9714 ( USA )www.secc.co.jp

Siliconix (Vishay) 203-268-6261 (USA ) www.vishay.comSumida 408-982-9660 (USA ) www.sumida.com

Taiyo Yuden03-3667-3408 (Japan)

408-573-4150 ( USA )www.t-yuden.com

TDK847-803-6100 ( USA )

81-3-5201-7241 (Japan)www.component.tdk.com

Toko 858-675-8013 (USA ) www.tokoam.com


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MAX1987/MAX198

8


18 ______________________________________________________________________________________

PRELIMINARY

OFF

ON

BSTM

DHM

LXM

DLM

VDDVCC

D0

D1

D3

D4

FB

DAC INPUTS(1V LOGIC)

REF

CREF0.22F

CCCV270pF

PGND

V+

CCV

NEG

CCI

S0

S1SUSPEND INPUTS

(FOUR-LEVEL LOGIC)

POS

CSP

ILIM

TIME

SUS

PSI

MODECONTROL

C3100pF

RTIME28k

R8100k

POWER GROUND

ANALOG GROUND

GND

D5

S2

B0

B1BOOT INPUTS

(FOUR-LEVEL LOGIC)B2

OAIN-

OAIN+

CM N

CM P

IMVPOK

SYSPOK

R12100k

R13100k

R11100k

C21F

TON

FLOAT

(300kHz)

POWER-GOOD

LOGICSIGNALS

R2750

R31.0k

CCCI470pF

R930.1k

INPUT*8V TO 24V

LM

CIN

NH(M)

NL(M)

RCM

CBST(M)0.1F

R1010

5V BIASSUPPLY

C12.2F

DDO

SHDN

DPSLP

CLKEN

MAX1987

MAX1988

LS

CIN

NH(S)

NL(S)

RCS

CBST(S)0.1F

BSTDIODES

R11.5k

R7100k R4

750

R51.0k

R62.74k

CSN

BSTS

DHS

LXS

DLS

RCCI1M

OUTPUT

COUT

COUT

*LOWER INPUT VOLTAGESREQUIRE ADDTIONALINPUT CAPACITANCE

D2

R144.7k

C44.7nF

Figure 1. Standard Application C ircuit (M aster)


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Deta iled Description

5V Bias Supply (VCC and VDD)The M AX1987/M AX1988 require an external 5V bias sup-

ply in addition to the battery. T ypically, this 5V bias sup-

ply is the notebook s 95% efficient 5V system supply.

K eeping the bias supply external to the IC improves effi-

ciency and eliminates the cost associated with the 5V lin-

ear regulator that would otherwise be needed to supply

the PWM circuit and gate drivers. If standalone capabi lity

is needed, the + 5V bias supply can be generated with

an external linear regulator.

The 5V bias supply must provide V C C (PWM controller)

and VD D (gate-drive power), so the maximum current

drawn is:

IBIAS = IC C + fSW (Q G (L O W ) + Q G ( H I G H ))

= 10mA to 100mA ( typ)

where IC C is 1.7mA (typ), fSW is the switching frequency,

and Q G(LOW) and Q G(H IGH) are the M O SFET data sheets

total gate-charge specification limits at VG S = 5V.

V+ and VD D can be connected together if the input

power source is a fixed 4.5V to 5.5V supply. If the 5V

bias supply is powered up prior to the battery supply,

the enable signal (SHDN going from low to high) must

be delayed until the battery voltage is present to ensure

startup.

Free-Running, Constant On-Time PWMController w ith Input Fee dforw ard

The Q uick-PWM control architecture is a pseudo-fixed-

frequency, constant-on-time, current-mode regulator

with voltage feedforward (Figure 2). This architecture

relies on the output filter capacitors ESR to act as the

current-sense resistor, so the output ripple voltage pro-

vides the PWM ramp signal. T he control algorithm is

simple: the high-side switch on-time is determined sole-

ly by a one-shot whose period is inversely proportional

to input voltage, and directly proportional to output volt-

age and the difference between the main and sec-

ondary inductor currents (see the O n-Tim e O ne-Shot

section) . A nother one-shot sets a minimum off-time. Theon-time one-shot is triggered if the error comparator is

low, the low-side switch currents are below the current-

limit threshold, and the minimum off-time one-shot has

timed out. The controller maintains 180 out-of-phase

operation by alternately triggering the main and sec-

ondary phases after the error comparator drops below

the output voltage set point.

On-Time One-Shot (TON )T he core of each p hase contains a fast, low-ji tter,

adjustable one-shot that sets the high-side M O SFET son-time. The one-shot for the main phase simply varies

the on-time in response to the input and feedback volt-

ages. The main high-side switch on-time is inversely

proportional to the input voltage as measured by the V+

input, and proportional to the feedback voltage (VFB ) :

where K is set by the TO N pin-strap connection (T able

3) and 0.075V is an approximation to accommodate the

expected drop across the low-side M O SFET switch.

The one-shot for the secondary phase varies the on-time in response to the input voltage and the difference

between the main and secondary inductor currents.

Two identical transconductance amplifiers integrate the

difference between the master and slave current-sense

signals. The summed output is internally connected to

C C I, allowing adjustment of the integration time con-

stant with a compensation network connected between

C C I and FB . T he resulting compensation current and

voltage are determined by the following equations:

where ZC C I is the impedance at the C C I output.The secondary on-time one-shot uses this integrated

signal (VC C I) to set the secondary high-side M O SFET s

on-time. When the main and secondary current-sense

signals (VC M = VC M P - VC M N and VC S = VC SP - VC SM )

become unbalanced, the transconductance amplifiers

adjust the secondary on time, which increases or

decreases the secondary inductor current until the cur-

rent-sense signals are properly balanced:

This algorithm results in a nearly constant switching fre-

quency and balanced inductor currents, despite the

lack of a fixed-frequency clock generator. T he benefits

of a constant switching frequency are twofold: first, the

t KV V

V

K

V V

V K

I Z

V

M a in O n time Secondary C urrent

Balance C orrection

O N N DC C I

IN

FB

IN

C C I C C I

IN

( ).

.

( ) (

)

20 075

0 075

=+

=

+

+

= +

I g V V g V V

V V I Z

C C I M C M P C M N M C SP C SN

C C I FB C C I C C I

== +

( ) ( )

tK V V

VO N M A IN

FB

IN( )

( . )=

+ 0 075

MAX1987/MAX1

988


______________________________________________________________________________________ 19

PRELIMINARYCONFIDENTIAL INFORMATIONRESTRICTED TO INTEL IMVP LICENSEES

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MAX1987/MAX198

8 frequency can be selected to avoid noise-sensitiveregions such as the 455kH z IF band; second, theinductor ripple-current operating point remains relative-ly constant, resulting in easy design methodology and

predictable output-voltage ripple. The on-time one-

shots have good accuracy at the operating points

specified in the Electrical C haracteristics ( 10% a t200kH z and 300kH z, 12% at 550kH z). O n-times at

operating points far removed from the conditions speci-

fied in the Electrical C haracteristics can vary over awider range. For example, the 550kH z setting typically

runs about 10% slower with inputs much greater than

12V due to the very short on-times required.

O n-times translate only roughly to switching frequencies.

The on-times guaranteed in the Electrical C haracteristicsare influenced by switching delays in the external high-

side M O SFET. Resistive losses, including the inductor,

both M O SFETs, output capacitor ESR , and P C board

copper losses in the output and ground tend to raise

the switching frequency at higher output currents. A lso,

the dead-time effect increases the effective on-time,

reducing the switching frequency. It occurs only in

PWM mode (SUS = low, DPSLP = low) a nd duringdynamic output voltage transitions when the inductor

current reverses at light or negative load currents. With

reversed inductor current, the inductors EM F causes

LX to go high earlier than normal, extending the on-time

by a period equal to the DH-rising dead time. For loads

above the critical conduction point, where the dead-

time effect is no longer a factor, the actual switching

frequency (per phase) is:

where VD R O P 1 is the sum of the parasitic voltage drops

in the inductor discharge path, including synchronous

rectifier, inductor, and P C board resistances; V D R O P 2 is

the sum of the parasitic voltage drops in the inductor

charge path, including high-side switch, inductor, and

PC board resistances; and tO N is the on-time as deter-

mined above.

Current BalanceWithout active current-balance circuitry, the current

matching between phases depends on the M O SFET son-resistance (R DS (O N )) , thermal ballasting, on-/off-time

matching, and inductance matching. For example, vari-

ation in the low-side M O SFET on-resistance ( ignoring

thermal effects) results in a current mismatch that is

proportional to the on-resistance difference:

T hermal ballasting as the loaded M O SFET s heat up

actually improves the current balance. The stronger

M O SFET ( the phase with the lower RDS (O N )) pulls more

current, which heats up the M O SFET more than the

other phase, increasing the thereby reducing the current

mismatch. Taking thermal effects into account, the on-

resistance of the switching M O SFET s can be determined

by the following equation:

where R TA(25) is the on-resistance at room temperature,

IL is the inductor current through the M O SFET , R JA(C /W) is the junction-to-ambient thermal resistance of

the M O SFET package, and R T E MPC O (0.5% /C ) is thetemperature coefficient of the M O SFET. Thermal ballast-

ing can typically reduce the current mismatch by asmuch as a third. U nfortunately, mismatches between on-

times, off-times, and inductor values increase the worst-

case current imbalance making it impossible to

passively guarantee accurate current balancing.

T he M A X 1987/M A X1988 integrate the difference

between the current-sense voltages and adjusts the on-

time of the secondary phase to maintain current bal-

ance. The current balance now relies on the accuracy

of the current-sense resistors instead of the inaccurate,

thermally sensitive on-resistance of the low-side tracking

M O SFET s. With active current balancing, the current

mismatch is simply determined by the current-sense

resistor values and the offset voltage of the transconduc-

tance amplifiers:

where R SENSE = R C M = R C S and VO S ( IB A L ) is the

current-balance offset specification in the ElectricalC haracteristics.

I I IV

RO S BA L LM LS

O S IB A L

SENSE( )

( )= =

RR

R I R RD S O N

TA

TA L JA TEM PC O

( )( )

( )(=

25

252

1

I I IR

RM A IN N D M A IN

M A I N

N D

=

22

1

fV V

t V V VSW

O U T DR O P

O N IN D RO P D RO P

=+( )

+ 1

1 2( )


20 ______________________________________________________________________________________

PRELIMINARY

TON

CONNECTION

FREQUENCY

SETTING

(kHz)

K-FACTOR

(s)

MAX

K-FACTOR

ERROR (%)

VC C 200 5 10

Float 300 3.3 10

REF 550 1.8 12.5

G ND 1000 1.0 12.5

Table 3. Approximate K-Factor Errors


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The worst-case current mismatch occurs immediately

after a load transient due to inductor value mismatches

resulting in different dI/dt for the two phases. The time ittakes the current-balance loop to correct the transient

imbalance depends on the mismatch between the

inductor values and switching frequency.

Dual 180Out-of-Phase OperationThe two phases in the M AX1987/M AX1988 operate 180

out-of-phase to minimize input and output filtering

requirements, reduce electromagnetic interference (EM I) ,

and improve efficiency. This effectively lowers component

count reducing cost, board space, and component

power requirements making the M A X1987/M A X1988

ideal for high-power, cost-sensitive applications.

Typically, switching regulators provide transfer power

using only one phase instead of dividing the poweramong several phases. In these applications, the input

capacitors must support high-instantaneous current

requirements. The high RM S ripple current can lower

efficiency due to I 2R power loss associated with the

input capacitors effective series resistance (E SR ) .

Therefore, the system typically requires several low-

ESR input capacitors in parallel to minimize input volt-

age ripple, to reduce ESR -related power losses, and to

meet the necessary R M S ripple-current rating.

With the M AX1987/M AX1988, the controller shares the

current between two phases that operate 180 out-of-

phase, so the high-side M O SFET s never turn on simulta-

neously during normal operation. The instantaneous

input current of either phase is effectively halved, result-ing in reduced input-voltage ripple, ESR power loss, and

RM S ripple current (see the Input C apacitor Selectionsection). Therefore, the same performance can be

achieved with fewer or less expensive input capacitors.

Transient Overlap OperationWhen a transient occurs, the response time of the con-

troller depends on how quickly it can slew the inductor

current. M ultiphase controllers that remain 180 out-of-

phase when a transient occurs actually respond slower

than an equivalent single-phase controller. In order to

provid e fast transient response, the M A X 1987/

M A X1988 support a phase overlap mode that allows

the individual phases to operate simultaneously whenheavy load transients are detected, effectively reducing

the response time. A fter either high-side M O SFET turns

off, if the output voltage does not exceed the regulation

voltage when the minimum off-time expires, the con-

troller simultaneously turns on both high-side M O SFETs

during the next on-time cycle. This maximizes the total

inductor current slew rate. T he phases remain over-

lapped until the output voltage exceeds the regulation

voltage after the minimum off-time expires.

After the phase overlap mode ends, the controller automat-

ically begins with the opposite phase. For example, if the

secondary phase provided the last on-time pulse before

overlap operation began, the controller starts switching

with the main phase when overlap operation ends.

Integrator Amplifiers/OutputVoltage Offsets

Two transconductance amplifiers provide a fine adjust-

ment to the output regulation point (Fi gure 2). O ne

amplifier forces the D C average of the feedback volt-

age to equal the VID D AC setting. T he second amplifier

is used to create small positive or negative offsets from

the VID D AC setting, using the PO S and NEG pins.

The feedback amplifier integrates the feedback volt-

age, allowing accurate DC output voltage regulation

regardless of the output ripple voltage. The feedback

amplifier has the ability to shift the output voltage by

8% . T he differential input voltage range is at least

80mV total, including D C offset and A C ripple. T he

integration time constant can be set easily with one

capaci tor at the C C V pi n. U se a capaci tor value of

47pF to 1000pF (270pF typ).

The PO S/NEG amplifier is used to add small offsets to

the VID D A C setting in deep-sleep mode (DPSLP =

low) . The offset amplifier is summed directly with the

feedback voltage, making the offset gain independent

of the D AC code. T his amplifier has the ability to offsetthe output by 200mV. To create an output offset, bias

PO S and N EG to a voltage ( typically VO U T or R EF) with-

in their 0 to 2V common-mode range, and offset them

from one another with a resistive divider (Figure 1). If

VPO S is higher than VN EG , then the output is shifted in

the positive direction. If V NEG is higher than VPO S, then

the output is shifted in the negative d irection. T he out-

put offset equals the voltage di fference from PO S to

NEG .

Forced-PWM Operation (Normal Mode)D uring normal mode, when the C PU is actively running

(SU S = low, DPSLP = high, PSI = high), the M AX1987/

M AX1988 operate with the low-noise forced-PWM con-

trol scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gate-drive

waveform to constantly be the complement of the high-

side gate-drive waveform. The benefit of forced-PWM

mode is to keep the switching frequency fairly constant.

Forced-PWM operation comes at a cost: the no-load 5V

bias supply current remains between 10mA to 100mA ,

depending on the external M O SFET s and switching

MAX1987/MAX1

988


______________________________________________________________________________________ 21


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MAX1987/MAX198

8


22 ______________________________________________________________________________________

MAX1987

MAX1988

CSN

CSP

CM P

CM N

VCC

REF

GND

CCV

POS

NEG

FB

OAIN+

OAIN-

TIME

6 BITSBLANK

SKIP

ILIM

19R

R

REF(2.0V)

SHDN

REF

Gm

Gm

DPSLP

R-2RDAC

INTERNAL MULTIPLEXERS, M ODECONTROL, AND SLEW-RATE CONTROL

B0TOB2

S0TOS2

D0D5

SUS

SYSPOK

PSI

DD0

0.9 x REF 1.1 x REF

SYSPOK

CLKEN

IMVPOK

STARTUPDELAY

Q

QT

CM P

CM N

SKIP

FAULT

1.5mV

S

R

Q

R

S

Q

MAIN

MAIN

ON-TIME

ONE-SHOT

TRIGQ

ON-TIME

ONE-SHOT

TRIGQ

BSTM

TON

V+

CCI

DHM

LXM

VDD

DLM

PGND

MAIN PHASEDRIVERS

TRIGQ

ONE-SHOT

MINIMUMOFF-TIME

SECONDARY PHASEDRIVERS

FB

Gm

Gm

CM P

CSP

CM N

CSN

BSTS

DHS

LXS

DLS

Figure 2. M AX1987/M AX1988 Functional D iagram


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frequency. To maintain high efficiency under light-load

conditions, the M AX1987/M AX1988 automatically switch

to the low-power pulse-skipping control scheme afterentering suspend or deep-sleep mode.

D uring output voltage and m ode transitions (PSI =

high) , the M A X1987/M AX1988 use forced-PWM opera-

tion to ensure fast, accurate transitions. Since forced-

PWM operation disables the zero-crossing comparator,

the inductor current reverses under light loads, quickly

discharging the output capacitors. The controller main-

tains forced-PWM operation for 32 clock cycles (set by

R T I ME) after the controller sets the last DA C code value

to guarantee the output voltage settles properly before

entering pulse-skipping operation.

Low-Power Pulse Skipping

D uring deep-sleep mode (DPSLP = low) , low-powersuspend ( SU S = high), or pulse-skipping override mode

(PSI = low), the M AX1987/M AX1988 use an automatic

pulse-skipping control scheme, alternately switching

both phases in order to maintain the current balance.

For deep-sleep mode, when the C PU pulls DPSLP low,

the M A X1987/M A X1988 shift the output voltage to

incorporate the offset voltage set by the PO S and N EG

inputs (Figure 3). 32 R T I ME clock cycles after DPSLP

goes low, the controller pulls the driver-disable output

(DDO) low. A n additional 30 RT I ME clock cycles later,

the M A X1987/M A X1988 enter low-power operation,

allowing automatic pulse skipping under light loads.

When the C P U d rives DPSLP high, the M A X1987/

M A X1988 immediately enter forced-PWM operation,force DDO high, and eliminate the output offset, slew-

ing the output to the operating voltage set by the

D 0D 5 inputs. When either DPSLP transition occurs,

the M A X1987/M A X1988 force IM VP O K h igh and

C LK EN low for 32 R T I ME clock cycles.

When entering suspend mode (SU S driven high) , the

M A X1987/M AX1988 slew the output down to the sus-

pend output voltage set by S0 to S2 inputs (Figure 4).

32 R T I M E clock cycles after the slew-rate controller

reaches the last D A C code ( see the O utput Voltag eTransition Tim ingsection), the DDO is asserted low.A fter an addi t ional 30 R T I M E clock cycles, the

M A X1987/M AX1988 enter low-power operation, allow-

ing pulse skipping under light loads. When the C PU

pulls SU S low, the M A X1987/M A X1988 immediately

enter forced-PWM operation, force DDOhigh, and slewthe output up to the operating voltage set by the D 0D 5

inputs. When either SU S transit ion occurs, the

M AX 1987/M A X1988 blank IM VPO K and CLKEN, pre-

venting IM VP O K from going low and CLKEN from going

high. T he blanking remains active until the slew rate

controller has reached the last D AC code and 32 addi-

tional R T I ME clock pulses have passed.

When PSI is pulled low, the M AX1987/M AX1988 over-ride forced-P WM operation and use the automatic

pulse-skipping control scheme regardless of the state

of the SU S and DPSLP control inputs. O nce PSI ispulled low, the controller asserts the driver-disable out-

put (DDO = low), forces IM VP O K high, and forcesCLKEN low. When PSI is used during mode transitions,

the constant IM VP O K and CLKEN blanking allows

indefinite settling times.

In applications with more than two phases, the driver-

disable signal is used to force one or more slave regula-

tors into a high-impedance state. When the masters

DDOoutput is driven low, the slave controller with driver

disable (M AX1980) forces its D L(SLAVE) and DH (SLAVE)gate drivers low, effectively disabling the slave con-

troller. D isab ling the slave controller allows the

M AX1987/MAX1988 to enter low-power pulse skipping

operation under low-power conditions, improving light-

load efficiency. When DDO is driven high, the slave con-

troller (M A X1980) enables the drivers, allowing normal

forced-PWM operation. For detailed operation with slave

controllers, refer to the M AX1980 data sheet.

Automatic Pulse-Skipping SwitchoverIn skip mode (PSI = low, SU S = high, or DPSLP = low),

an inherent automatic switchover to PFM takes place at

light loads (Figure 5). This switchover is affected by a

comparator that truncates the low-side switch on time at

the inductor currents zero crossing. The zero-crossingcomparator senses the inductor current across the cur-

rent-sense resistors. O nce VC _P - V C _N drops below

1.5mV ( typ) , the comparator forces DL_ low (Figure 2).

This mechanism causes the threshold between pulse-

skipping PFM and nonskipping PWM operation to coin-

cide with the boundary between continuous and

discontinuous inductor-current operation. T he PFM /PWM

crossover occurs when the load current of each phase is

equal to 1/2 the peak-to-peak ripple current, which is a

function of the inductor value (Figure 6). For a battery

input range of 7V to 20V, this threshold is relatively con-

stant, with only a minor dependence on the input voltage

due to the typically low duty cycles.

T he total load current at the PFM /PWM crossover

threshold ( ILOAD(SK IP ) ) is approximately:

where K is the on-time scale factor (Table 3).

IV K

L

V V

VLO A D SK I P

O UT IN O UT

IN( ) =

MAX1987/MAX1

988


______________________________________________________________________________________ 23


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MAX1987/MAX198

8


24 ______________________________________________________________________________________

VOUT

TIMECLOCK

IMVPOK

LX_

PULSESKIPPING

AUTOMATIC PULSE-SKIPPING

SWITCHOVER

OUTPUT TRANSITIONAND SETTLING

OUTPUT TRANSITIONAND SETTLING

DPSLP

DDO

CLKEN

tDD0 = 32 CLKS tSKIP = 30 CLKS tBLANK = 32 CLKS

IMVPOK AND CLKENBLANKING


VPOS - VNEG OFFSET

Figure 3. M AX1987/M AX1988 D eep Sleep Transition

SUS

VOUT

TIMECLOCK

IMVPOK

LX_

PULSESKIPPING

AUTOMATIC PULSE-SKIPPING

SWITCHOVER

OUTPUT SETTLINGOUTPUTTRANSITION

OUTPUT SETTLINGOUTPUTTRANSITION

OUTPUT SET BY S0 TO S2

OUTPUT SET BY D0D5

CLKEN

DDO

16mV PER RTIME CYCLE

tBLANK = 32 CLKStSKIP = 30 CLKS tSLEWtSLEW tDD0 = 30 CLKS



Figure 4. M AX1987/M AX1988 Suspend Transition


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For example, in the standard application circuit this

becomes:

The switching waveforms can appear noisy and asyn-

chronous when light loading activates pulse-skipping

operation, but this is a normal operating condition that

results in high light-load efficiency. Trade-offs between

PFM noise and light-load efficiency are made by varying

the inductor value. G enerally, low inductor values pro-

duce a broader efficiency vs. load curve, while higher

values result in higher full-load efficiency (assuming that

the coil resistance remains fixed) and less output volt-

age ripple. Penalties for using higher inductor values

include larger physical size and degraded load-tran-

sient response, especially at low-input voltage levels.

Current -Limit CircuitThe current-limit circuit employs a unique valley cur-

rent-sensing algorithm that uses current-sense resistorsfrom C M P to CM N and from C SP to C SN as the current-

sensing elements (Figure 1) . If the current-sense signal

of the selected phase is above the current-limit thresh-

old, the P WM controller does not initiate a new cycle

( Figure 2) until the inductor current of the selected

phase drops below the valley current-limit threshold.

When either phase trips the current limit, both phases

are effectively current limited since the interleaved con-

troller does not initiate a cycle with either phase.

Since only the valley current is actively limited, the

actual peak current is greater than the current-limit

threshold by an amount equal to the inductor ripple

current. Therefore, the exact current-limit characteristic

and maximum load capability are a function of the cur-

rent-sense resistance, inductor value, and battery volt-

age. When combined with the undervoltage protection

circuit, this current-limit method is effective in almost

every circumstance.

There is also a negative current limit that prevents

excessive reverse inductor currents when VO U T is sink-

ing current. The negative current-limit threshold is set to

approximately 120% of the positive current limit, and

therefore tracks the positive current limi t when ILIM is

adjusted. When a phase drops below the negative cur-

rent limit, the controller immediately activates an on-

time pulse D L_ turns off, and D H_ turns on allowing

the inductor current to remain above the negative cur-rent threshold.

The current-limit threshold is adjusted with an external

resistive voltage-divider at IL IM . The current-limit thresh-

old voltage adjustment range is from 10mV to 75mV. In

the adjustable mode, the current-limit threshold voltage

is precisely 1/20th the voltage seen at ILIM . T he thresh-

old defaults to 30mV when IL IM is connected to VC C .

The logic threshold for switchover to the 30mV default

value is approximately VC C - 1V.

C arefully observe the PC board layout guidelines to

ensure that noise and D C errors do not corrupt the cur-

rent-sense signals seen by the current-sense inputs

(CM P , CM N , CSP , CSN ) .

MOSFET Gat e Drivers (DH, DL)T he DH _ and D L_ drivers are optimized for driving

moderately sized, high-side and larger, low-side power

M O SFETs. This is consistent with the low duty factor

seen in the notebook C PU environment, where a large

V IN - V O U T differential exists. A n adaptive dead-time

circuit monitors the D L_ output and prevents the high-

side FET from turning on until DL_ is fully off. There must

1 3 3 3

0 6

12 1 3

126 4

. .

.

..

V s

H

V V

VA

=

MAX1987/MAX1

988


______________________________________________________________________________________ 25

PRELIMINARY

INDUCTOR

CURRENT

ILOAD = IPEAK/2

ON-TIME0 TIM E

IPEAKL

VBATT - VOUTit

=

Figure 5. Pulse-Skipping/D iscontinuous C rossover Point

INDUCTOR

CURR

ENT

ILIMIT(VALLEY) = ILOAD(MAX) 2 - LIR

2( )

TIME0

IPEAK

ILOAD

ILIMIT

Figure 6.ValleyC urrent-Lim it Threshold Point


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MAX1987/MAX198

8 be a low-resistance, low-inductance path from the DL_driver to the M O SFET gate in order for the adap tivedea d-tim e circuit to work properly. O therwise, thesense circuitry in the M AX1987/M A X1988 interprets the

M O SFET gate as off while there is actually charge still

left on the gate. U se very short, wide traces (50mils to

100mils wide if the M O SFET is 1in from the device) . T he

dead time at the other edge ( D H_ turning off) is deter-

mined by a fixed 35ns internal delay.

The internal pulldown transistor that drives D L_ low is

robust, with a 0.4 (typ) on-resistance. This helps pre-vent D L from being pulled up due to capacitive cou-

pling from the drain to the gate of the low-side

M O SFET s when LX _ switches from ground to V I N .

Applications with high input voltages and long, induc-

tive D L_ traces can require additional gate-to-source

capacitance to ensure fast rising LX_ edges do not pull

up the low-side M O SFETs gate voltage, causing shoot-

through currents. The capacitive coupling between LX_

and DL _ created by the M O SFETs gate-to-drain

capacitance (C RSS ), gate-to-source capacitance (C ISS- C R SS ), and additional board parasitics should not

exceed the minimum threshold voltage:

Lot-to-lot variation of the threshold voltage can cause

problems in marginal designs. Typically, adding a

4700pF between DL_ and power ground ( C N L in Figure7), close to the low-side M O SFET s, greatly reduces

coupling. D o not exceed 22nF of total gate capacitance

to prevent excessive turn-off delays.

A lternatively, shoot-through currents can be caused by

a combination of fast high-side M O SFET s and slow low-

side M O SFETs. If the turn-off delay time of the low-side

M O SFET is too long, the high-side M O SFETs can turn

on before the low-side M O SFETs have actually turned

off. Adding a resistor less than 5 in series with BST_slows down the high-side M O SFET turn-on time, elimi-

nating the shoot-through currents without degrading

the turn-off time (R BST in Figure 7). Slowing down the

high-side M O SFET also reduces the LX node rise time,

thereby reducing EM I and high-frequency couplingresponsible for switching noise.

Volta ge-Positioning AmplifierT he M A X1987/M A X1988 include an independent op

amp for adding gain to the voltage positioning sense

path. The voltage-positioning gain allows the use of

low-value, current-sense resistors in order to minimize

power dissipation. T his 3M Hz gain-bandwidth amplifier

was designed with low offset voltage (70V typ) to meet

the IM VP -IV output accuracy requirements.

The inverting (O A IN -) and noninverting (O A IN + ) inputs

are used to differentially sense the voltage across the

voltage-positioning sense resistor. T he op amp s output is

internally connected to the regulators feedback input

(FB). The op amp should be configured as a noninvert-ing, differential amplifier as shown in Figures 1 and 10.

The voltage-positioning slope is set by properly selecting

the feedback resistor connected from FB to O A IN - (see

the Setting Voltage Positioningsection). For applicationsusing a slave controller, additional differential input resis-

tors (summing configuration) should be connected to the

slaves voltage-positioning sense resistor (Figures 1 and

10). Summing together both the master and slave cur-

rent-sense signals ensures that the voltage-positioning

slope remains constant when the slave controller is dis-

abled.

In applications that do not require voltage positioning

gain, the amplifier can be disabled by connecting the

O A IN - pin directly to VC C . The disabled amplifiers out-put becomes high impedance, guaranteeing that the

unused amplifier does not corrupt the FB input signal.

The logic threshold to disable the op amp is approxi-

mately VC C - 1V.

Power-Up SequenceThe M AX1987/M AX1988 are enabled when SHDN is dri-

ven high (Figure 8). First, the reference powers up. O nce

V VC

CG S TH IN

RSS

ISS( )

2

1

2

VI L

C VS O AR

LO A D M A X

O UT O UT

( ) ( )

2

2

V

L IV K

Vt

C VV V K

Vt

I

C

V K

Vt

SA G

LO A D M A XO U T

INO FF M I N

O UT O UTIN O UT

INO FF M I N

LO A D M A X

O U T

O U T

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