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¼
¼
¼
SIN
SCLK
LAT
BLANK
SOUT
GND
VCC
TLC59281
IC1
OUT0 OUT15
VCC
¼ ¼
VLED VLED
¼
¼
SIN
SCLK
LAT
BLANK
RIREF
IREF
SOUT
ICn
OUT0 OUT15
DATA
SCLK
BLANK
ERROR
READ
¼
VLED VLED
RIREF
IREF
Controller
GND
VCC
VCC
3
LAT
TLC59281
www.ti.com SBVS139B –JANUARY 2010–REVISED JANUARY 2011
16-Channel, Constant-Current LED DriverCheck for Samples: TLC59281
1FEATURES APPLICATIONS• LED Video Displays
2• 16 Channels, Constant-Current Sink Outputwith On/Off Control • Message Boards
• Illumination• 35-mA Capability (Constant-Current Sink)• 10-ns High-Speed Constant-Current Switching
DESCRIPTIONTransient TimeThe TLC59281 is a 16-channel, constant-current sink• Low On-Time ErrorLED driver. Each channel can be turned on/off by• LED Power-Supply Voltage up to 17 Vwriting serial data to an internal register. The
• VCC = 3.0 V to 5.5 V constant-current value of all 16 channels is set by a• Constant-Current Accuracy: single external resistor.
– Channel-to-Channel = ±1%– Device-to-Device = ±1%
• CMOS Logic Level I/O• 35-MHz Data Transfer Rate• 20-ns BLANK Pulse Width• Operating Temperature: –40°C to +85°C
Typical Application Circuit (Multiple Daisy-Chained TLC59281s)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. © 2010–2011, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
TLC59281
SBVS139B –JANUARY 2010–REVISED JANUARY 2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT PACKAGE-LEAD ORDERING NUMBER TRANSPORT MEDIA, QUANTITY
TLC59281DBQR Tape and Reel, 2500TLC59281 SSOP-24/QSOP-24
TLC59281DBQ Tube, 50
TLC59281RGER Tape and Reel, 3000TLC59281 QFN-24
TLC59281RGE Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit thedevice product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER TLC59281 UNIT
VCC Supply voltage: VCC –0.3 to +6.0 V
IOUT Output current (dc) OUT0 to OUT15 40 mA
VIN Input voltage range SIN, SCLK, LAT, BLANK, IREF –0.3 to VCC + 0.3 V
SOUT –0.3 to VCC + 0.3 VVOUT Output voltage range
OUT0 to OUT15 –0.3 to +18 V
TJ(MAX) Operating junction temperature +150 °CTSTG Storage temperature range –55 to +150 °C
Human body model (HBM) 2 kVESD rating
Charged device model (CDM) 500 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not supported.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGSOPERATING FACTOR TA < +25°C TA = +70°C TA = +85°C
PACKAGE ABOVE TA = +25°C POWER RATING POWER RATING POWER RATING
SSOP-24/QSOP-24 14.3 mW/°C 1782 mW 1140 mW 927 mW
QFN-24 (1) 24.8 mW/°C 3106 mW 1988 mW 1615 mW
(1) The package thermal impedance is calculated in accordance with JESD51-5.
2 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59281
TLC59281
www.ti.com SBVS139B –JANUARY 2010–REVISED JANUARY 2011
RECOMMENDED OPERATING CONDITIONSAt TA= –40°C to +85°C, unless otherwise noted.
TLC59281
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC Supply voltage 3.0 5.5 V
VO Voltage applied to output OUT0 to OUT15 17 V
VIH High-level input voltage 0.7 × VCC VCC V
VIL Low-level input voltage GND 0.3 × VCC V
IOH High-level output current SOUT –1 mA
IOL Low-level output current SOUT 1 mA
IOLC Constant output sink current OUT0 to OUT15 2 35 mA
TA Operating free-air temperature range –40 +85 °CTJ Operating junction temperature range –40 +125 °CAC Characteristics: VCC = 3 V to 5.5 V
fCLK (SCLK) Data shift clock frequency SCLK 35 MHz
TWH0 SCLK 10 ns
TWL0 SCLK 10 ns
TWH1 Pulse duration LAT 20 ns
TWH2 BLANK 20 ns
TWL2 BLANK 20 ns
TSU0 SIN–SCLK↑ 4 nsSetup time
TSU1 LAT↑–SCLK↑ 100 ns
TH0 SIN–SCLK↑ 3 nsHold time
TH1 LAT↑–SCLK↑ 10 ns
© 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TLC59281
D (%) = - 1IOUTn
(I + I + ... + I + I )OUT0 OUT1 OUT15OUT14
16
´ 100
D (%) =Ideal Output Current
- (Ideal Output Current)(I + I + ... I + I )OUT0 OUT1 OUT14 OUT15
16´ 100
I = 42 ´OUT(IDEAL)
1.20
RIREF
100
(I at V = 3.0 V)OUTn CC
(I at V = 5.5 V) (I at V = 3.0 V)OUTn CC OUTn CC-
5.5 V 3 V-
D (%/V) = ´
100
3 V 1 V-
´
(I at V = 1 V)OUTn OUTn
(I at V = 3 V) (I at V = 1 V)-OUTn OUTn OUTn OUTnD (%/V) =
.
TLC59281
SBVS139B –JANUARY 2010–REVISED JANUARY 2011 www.ti.com
ELECTRICAL CHARACTERISTICSAt VCC = 3.0 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC59281
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –1 mA at SOUT VCC – 0.4 VCC V
VOL Low-level output voltage IOL = 1 mA at SOUT 0 0.4 V
IIN Input current VIN = VCC or GND at SIN, SCLK, LAT, and BLANK –1 1 mA
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,ICC1 1 2 mARIREF = 27 kΩ
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,ICC2 4.5 8 mARIREF = 3 kΩSupply current (VCC)
SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V,ICC3 7 18 mARIREF = 3 kΩ
SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V,ICC4 16 40 mARIREF = 1.5 kΩ
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩIOLC Constant output current 31 34 37 mA(see Figure 6), at OUT0 to OUT15
All OUTn for constant-current driver, all outputs offIOLKG Output leakage current BLANK = high, VOUTn = VOUTfix = 17 V, RIREF = 1.5 kΩ 0.1 mA
(see Figure 6), at OUT0 to OUT15
Constant-current error All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩΔIOLC ±1 ±3 %(channel-to-channel) (1) at OUT0 to OUT15
Constant-current error All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩΔIOLC1 ±1 ±6 %(device-to-device) (2) at OUT0 to OUT15
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩΔIOLC2 Line regulation (3) ±0.5 ±1 %/Vat OUT0 to OUT15
All OUTn = ON, VOUTn = 1 V to 3V, VOUTfix = 1 V,ΔIOLC3 Load regulation (4) ±1 ±3 %/VRIREF = 1.5 kΩ, at OUT0 to OUT15
VIREF Reference voltage output RIREF = 1.5 kΩ 1.16 1.20 1.24 V
(1) The deviation of each output from the average of OUT0–OUT15 constant-current. Deviation is calculated by the formula:
(2) The deviation of the OUT0–OUT15 constant-current average from the ideal constant-current value.Deviation is calculated by the following formula:
Ideal current is calculated by the formula:
(3) Line regulation is calculated by this equation:
(4) Load regulation is calculated by the equation:
4 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59281
VCC
VCC
SCLK
SIN
LAT
BLANK
IREF
GND
GND
16
MSB
MSB
0 15
LSB
SOUT
OUT0 OUT1 OUT14 OUT15
16-Channel Constant-Current Sink Driver
TI Reserved
Data
On/Off Control Shift Register
(1 Bit x 16 Channels)
16
0 15
LSB
On/Off Control Data Latch
(1 Bit x 16 Channels)
¼
16
TLC59281
www.ti.com SBVS139B –JANUARY 2010–REVISED JANUARY 2011
SWITCHING CHARACTERISTICSAt VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 130 Ω, RIREF = 1.5 kΩ, and VLED = 5.5 V. Typical values atVCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC59281
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR0 SOUT (see Figure 5) 5 15 nsRise time
tR1 OUTn (see Figure 4) 10 30 ns
tF0 SOUT (see Figure 5) 5 15 nsFall time
tF1 OUTn (see Figure 4) 10 30 ns
tD0 SCLK↑ to SOUT 8 20 ns
LAT↑ or BLANK↓ to OUTn sink current ontD1 12 30 nsPropagation delay time (see Figure 10)
LAT↑ or BLANK↑ to OUTn sink current offtD2 12 30 ns(see Figure 10)
On/off latch data = all '1', 20 ns BLANK low leveltON_ERR Output on-time error (1) –8 +8 nsone-shot pulse input (see Figure 4)
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low level one-shot pulse width (TWL2).tOUT_ON indicates the actual on-time of the constant-current driver.
FUNCTIONAL BLOCK DIAGRAM
© 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TLC59281
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
BLANK
OUT15
OUT14
OUT13
OUT12
OUT11
1
2
3
4
5
6
18
17
16
15
14
13
Thermal Pad
(Bottom Side)
TLC59281
SC
LK
24
OU
T5
7
SIN
23
OU
T6
8
GN
D22
OU
T7
9
VC
C21
OU
T8
10
IRE
F20
OU
T9
11
SO
UT
19
OU
T10
12
GND
SIN
SCLK
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
SOUT
BLANK
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TLC59281
TLC59281
SBVS139B –JANUARY 2010–REVISED JANUARY 2011 www.ti.com
DEVICE INFORMATION
SSOP-24/QSOP-24 QFN-24DBQ PACKAGE RGE PACKAGE
(TOP VIEW) (TOP VIEW)
NOTE: Thermal pad is not connected to GND internally. The thermal pad must be connected to GND via the PCB pattern.
6 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59281
TLC59281
www.ti.com SBVS139B –JANUARY 2010–REVISED JANUARY 2011
TERMINAL FUNCTIONSTERMINAL
NAME DBQ RGE I/O DESCRIPTION
Serial data input for driver on/off control. When SIN = high level, data '1' are written into LSBSIN 2 23 I of the on/off control shift register at the rising edge of SCLK.
Serial data shift clock. Schmitt buffer input. All data in the on/off control shift register areSCLK 3 24 I shifted toward the MSB by 1-bit synchronization of SCLK. A rising edge on SCLK is allowed
100 ns after a rising edge of LAT.
Edge triggered latch. The data in the on/off control data shift register are transferred to theon/off control data latch at this rising edge. At the same time, the data in the on/off control shift
LAT 4 1 I register are replaced with TI reserved data for production test. LAT must be toggled only onceafter the shift data are updated to avoid the on/off control latch data being replaced with TIreserved data in the shift register. The reserved data is not a fixed number.
Blank, all outputs. When BLANK = high level, all constant-current outputs (OUT0–OUT15) areBLANK 21 18 I forced off. When BLANK = low level, all constant-current outputs are controlled by the on/off
control data in the data latch.
Constant-current value setting, OUT0–OUT15 sink constant-current is set to desired value byIREF 23 20 I/O connection to an external resistor between IREF and GND.
Serial data output. This output is connected to the MSB of the on/off data shift register. SOUTSOUT 22 19 O data changes at the rising edge of SCLK.
Constant-current output. Each output can be tied together with others to increase theOUT0 5 2 O constant-current. Different voltages can be applied to each output.
OUT1 6 3 O Constant-current output
OUT2 7 4 O Constant-current output
OUT3 8 5 O Constant-current output
OUT4 9 6 O Constant-current output
OUT5 10 7 O Constant-current output
OUT6 11 8 O Constant-current output
OUT7 12 9 O Constant-current output
OUT8 13 10 O Constant-current output
OUT9 14 11 O Constant-current output
OUT10 15 12 O Constant-current output
OUT11 16 13 O Constant-current output
OUT12 17 14 O Constant-current output
OUT13 18 15 O Constant-current output
OUT14 19 16 O Constant-current output
OUT15 20 17 O Constant-current output
VCC 24 21 — Power-supply voltage
GND 1 22 — Power ground
© 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TLC59281
VCC
INPUT
GND
VCC
SOUT
GND
OUTn
GND
VCC
VCC
GND
IREF OUTn
RIREF
RL
CL
(1)VLED
VCC
VCC
GND
SOUT
CL
(1)
¼¼
VCC
RIREF
VOUTFIX
VOUTn
OUT0VCC
OUTn
OUT15GND
IREF
TLC59281
SBVS139B –JANUARY 2010–REVISED JANUARY 2011 www.ti.com
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Figure 1. SIN, SCLK, LAT, BLANK Figure 2. SOUT
Figure 3. OUT0 Through OUT15
TEST CIRCUITS
(1) CL includes measurement probe and jig capacitance.(1) CL includes measurement probe and jig capacitance.
Figure 4. Rise Time and Fall Time Test Circuit forFigure 5. Rise Time and Fall Time Test Circuit forOUTn
SOUT
Figure 6. Constant-Current Test Circuit for OUTn
8 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59281
T , T, T , T , T :WH0 WH1WL0 WH2 WL2
INPUT(1)
CLOCK
INPUT(1)
DATA/CONTROL
INPUT(1)
T , T , T , T :SU0 SU1 H0 H1
TSU TH
VCC
VCC
GND
VCC
GND
GND
50%
50%
50%
TWH TWL
t , t , t , t , t , t , t :R0 R1 F0 F1 D0 D1 D2
INPUT(1) 50%
50%
90%
10%
OUTPUT
tD
t or tR F
V or VOL OUTn
V or VOH OUTn
GND
VCC
TLC59281
www.ti.com SBVS139B –JANUARY 2010–REVISED JANUARY 2011
TIMING DIAGRAMS
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 7. Input Timing
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Output Timing
© 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TLC59281
tD0
SIN
OUTn(1)
OUTn(2)
OUTn(3)
OUTn(4)
ON
OFF
LAT
On/Off Control
Latch Data (Internal)
SOUT
SCLK
Shift Register
LSB Data (Internal)
ON
BLANK
ON
OFFOFF
ON
ON
OFFON
ON
OFFOFF
OFF
ON
OFF
tWH2
TWH0
TH1
TWH1
13 14 15 161 2 3 4 5 1 2 3 4 5 6
TSU0
TH0
TWL0
t /tR0 F0
tD2tD1
tWL2
tOUTON
Shift Register
LSB+1 Data (Internal)
Shift Register
MSB Data (Internal)
Shift Register
MSB-1 Data (Internal)
DATA
0A
DATA
0A
DATA
15BDATA
14B
DATA
13BDATA
12B
DATA
3BDATA
2B
DATA
1B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11CRSV 0A
DATA
0B
DATA
1A
DATA
15BDATA
14B
DATA
13BDATA
4B
DATA
3BDATA
2BRSV DATA DATA DATA DATARSV 1A
DATA
14A
DATA
15BRSV RSV RSV RSV RSVRSV 14A
DATA
15ARSV RSV RSV RSV RSVRSV 15A
DATA
15B
DATA
15ARSV RSV RSV RSV RSVRSV 15A
DATA
15B
DATA
15BDATA
14B
DATA
13BDATA
12B
DATA
11B
DATA
3BDATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
DATA
10C
Previous On/Off Latch Data Latest On/Off Latch Data
TSU1
tD1 tD2
tD1
tR1
tF1
¼ ¼ ¼
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV RSV
RSV RSVRSVRSVRSV RSV
DATA
1B
DATA
14B
TLC59281
SBVS139B –JANUARY 2010–REVISED JANUARY 2011 www.ti.com
(1) On/off latched data are '1'.(2) On/off latched data are changed from '1' to '0' at the second LAT signal.
(3) On/off latched data are changed from '0' to '1' at the second LAT signal.
(4) On/off latched data are '0'.
Figure 9. Timing Diagram
10 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59281
100000
10000
10000 5 10 15 20 35
Output Current (mA)
Refe
rence R
esis
tor
()
W
25
1440
5040
33602520
1680
25200
10080
30
2016
4000
3000
2000
1000
0
-40 -20 0 20 40 60 80
Free-Air Temperature ( C)°
Po
we
r D
issip
atio
n R
ate
(m
W)
100
TLC59281DBQ
TLC59281RGE
40
35
30
25
20
15
10
5
00 0.5 1.0 1.5 2.0 2.5 3.0
Output Voltage (V)
Ou
tpu
t C
urr
en
t (m
A)
T = +25 C°AI = 35 mAO
I = 30 mAO
I = 20 mAO
I = 10 mAO
I = 5 mAOI = 2 mAO
40
39
38
37
36
35
34
33
32
31
300 0.5 1.0 1.5 2.0 2.5 3.0
Output Voltage (V)
Ou
tpu
t C
urr
en
t (m
A)
I = 30 mAO
T = 40- °CA
T = +25 C°A
T = +85 C°A
4
3
2
1
0
1
2
3
4
-
-
-
-
-40 -20 0 20 40 60 80 100
Ambient Temperature ( C)°
DI
(%)
OL
C
I = 35 mAO
V = 5 VCC
V = 3.3 VCC
4
3
2
1
0
1
2
3
4
-
-
-
-
0 10 20 30 40
Output Current (mA)
DI
(%)
OLC
T = +25 C°A
V = 5 VCC
V = 3.3 VCC
TLC59281
www.ti.com SBVS139B –JANUARY 2010–REVISED JANUARY 2011
TYPICAL CHARACTERISTICSAt VCC = 3.3 V and TA = +25°C, unless otherwise noted.
REFERENCE RESISTOR POWER DISSIPATION RATEvs OUTPUT CURRENT vs FREE-AIR TEMPERATURE
Figure 10. Figure 11.
OUTPUT CURRENT vs OUTPUT CURRENT vsOUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 12. Figure 13.
ΔIOLC vs AMBIENT TEMPERATURE ΔIOLC vs OUTPUT CURRENT
Figure 14. Figure 15.
© 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TLC59281
Time (12.5 ns/div)
CH1 (2 V/div)
CH2 (2 V/div)
CH3 (2 V/div)
CH3-OUT15
(BLANK = 20 ns)
C 2-OUT0
(BLANK = 20 ns)
H
CH1-BLANK
(20 ns)
I = 35 mA
T = +25 C
R = 130
C = 15 pF
VLED = 5.5 V
°
W
OLC
A
L
L
TLC59281
SBVS139B –JANUARY 2010–REVISED JANUARY 2011 www.ti.com
TYPICAL CHARACTERISTICS (continued)At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
CONSTANT-CURRENT OUTPUTVOLTAGE WAVEFORM
Figure 16.
12 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59281
R (k ) =WIREF
V (V)IREF
I (mA)OLC
´ 42
TLC59281
www.ti.com SBVS139B –JANUARY 2010–REVISED JANUARY 2011
DETAILED DESCRIPTION
SETTING FOR THE CONSTANT SINK CURRENT VALUE
The constant-current values are determined by an external resistor (RIREF) placed between IREF and GND. Theresistor (RIREF) value is calculated by Equation 1.
Where:VIREF = the internal reference voltage on the IREF pin (typically 1.20 V) (1)
IOLC must be set in the range of 2 mA to 35 mA. The constant sink current characteristic for the external resistorvalue is shown in Figure 10. Table 1 describes the constant-current output versus external resistor value.
Table 1. Constant-Current Output versus External Resistor Value
IOLCMax (mA, Typical) RIREF (kΩ)
35 1.44
30 1.68
25 2.02
20 2.52
15 3.36
10 5.04
5 10.1
2 25.2
CONSTANT-CURRENT DRIVER ON/OFF CONTROL
When BLANK is low, the corresponding output is turned on if the data in the on/off control data latch are '1' andremains off if the data are '0'. When BLANK is high, all outputs are forced off. This control is shown in Table 2.
Table 2. On/Off Control Data Truth Table
ON/OFF CONTROL LATCH DATA CONSTANT-CURRENT OUTPUT STATUS
0 Off
1 On
When the IC is initially powered on, the data in the on/off control shift register and data latch are not set to therespective default value. Therefore, the on/off control data must be written to the data latch before turning theconstant-current output on. BLANK should be at a high level when powered on because the constant-currentmay be turned on as a result of random data in the on/off control latch.
The on/off data corresponding to any unconnected OUTn outputs should be set to ‘0’ before turning on theremaining outputs. Otherwise, the supply current (ICC) increases while the LEDs are on.
© 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TLC59281
¼
On/Off Control Shift Register (1 Bit 16 Channels)´
On/Off Control Data Latch (1 Bit 16 Channels)´ 16 Bits
To Constant Current Driver Control Block
¼SOUT
13 12 3 2
LSB
On/Off Data
for
OUT3
On/Off Data
for
OUT2
On/Off Data
for
OUT13
On/Off Data
for
OUT12
SIN
SCLK
¼
13 12 3 2
LSB
LAT
15 14
On/Off Data
for
OUT15
On/Off Data
for
OUT14
15 14
1 0
On/Off Data
for
OUT1
On/Off Data
for
OUT0
1 0
MSB
MSB
On/Off Data
for
OUT13
On/Off Data
for
OUT12
On/Off Data
for
OUT15
On/Off Data
for
OUT14
11
11
4
4
On/Off Data
for
OUT3
On/Off Data
for
OUT2
On/Off Data
for
OUT1
On/Off Data
for
OUT0
TLC59281
SBVS139B –JANUARY 2010–REVISED JANUARY 2011 www.ti.com
REGISTER CONFIGURATION
The TLC59281 has an on/off control data shift register and data latch. Both the on/off control shift register andlatch are 16 bits long and are used to turn the constant-current drivers on and off. Figure 17 shows the shiftregister and latch configuration. The data at the SIN pin are shifted in to the LSB of the shift register at the risingedge of the SCLK pin; SOUT data change at the rising edge of SCLK. The timing diagram for data writing isshown in Figure 18. The driver on/off is controlled by the data in the on/off control data latch.
The on/off data are latched into the data latch by a rising edge of LAT after the data are written into the on/offcontrol shift register by SIN and SCLK. At the same time, the data in the on/off control shift register are replacedwith TI reserved data for production test. Therefore, LAT must be input only once after the on/off data update toavoid the on/off control data latch being replaced with TI reserved data in the shift register. When the IC initiallypowers on, the data in the on/off control shift register and latch are not set to the default values; on/off controldata must be written to the on/off control data latch before turning the constant-current output on. BLANK shouldbe high when the IC is powered on because the constant-current may be turned on at that time as a result ofrandom values in the on/off data latch. All constant-current outputs are forced off when BLANK is high.
Figure 17. On/Off Control Shift Register and Latch Configuration
14 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59281
Previous On/Off Latch Data
SIN
OUTn(1)
ON ON
ON
ON
OFF
OFF
OFF OFF
OFF
OFF
OFF
LAT
On/Off Control
Latch Data (Internal)
SOUT
OUTn(2)
Latest On/Off Latch Data
SCLK
1 2 3 4 5 1 2 3 4 5 613 14 15 16
Shift Register
LSB Data (Internal)
BLANK
ON
OFF
ON
OFFOUTn(3)
ON
OFFOUTn(4)
Shift Register
LSB+1 Data (Internal)
Shift Register
MSB Data(Internal)
Shift Register
MSB 1 Data(Internal)-
¼ ¼ ¼
DATA
0A
DATA
0A
DATA
15BDATA
14B
DATA
13BDATA
12B
DATA
3BDATA
2B
DATA
1B
DATA
0B
DATA
15B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11CRSV 0A
DATA
1A
DATA
15BDATA
14B
DATA
13BDATA
4B
DATA
3BDATA
2B
DATA
15C
DATA
14C
DATA
13C
DATA
12CRSV 1A
DATA
14A
DATA
15BRSV 14A
DATA
1ARSV 15A
DATA
15B
DATA
1ARSV 15A
DATA
15BDATA
14B
DATA
13BDATA
12B
DATA
11B
DATA
3BDATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
DATA
10C
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV RSV RSV RSV RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
DATA
1B
DATA
14B
TLC59281
www.ti.com SBVS139B –JANUARY 2010–REVISED JANUARY 2011
(1) On/off latched data are '1'.(2) On/off latched data are changed from '1' to '0' at the second LAT signal.
(3) On/off latched data are changed from '0' to '1' at the second LAT signal.
(4) On/off latched data are '0'.
Figure 18. On/Off Control Operation
LAYOUT CONSIDERATIONS
The output current transient time in the TLC59281 is very fast. In addition, all outputs turn on or off at the sametime to minimize the output on-time error. This high current demand can cause GND to shift in the entire system,and lead to false triggering of signals. To overcome this issue, design all GND lines to be as wide and short aspossible in order to reduce parasitic inductance and resistance.
© 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TLC59281
TLC59281
SBVS139B –JANUARY 2010–REVISED JANUARY 2011 www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2010) to Revision B Page
• Added Layout Considerations section ................................................................................................................................ 15
Changes from Original (January 2010) to Revision A Page
• Changed SO-24 to SSOP-24/QSOP-24 in Package/Ordering Information table ................................................................. 2
• Changed SO-24 to SSOP-24/QSOP-24 in Dissipation Ratings table .................................................................................. 2
• Changed SO-24 to SSOP-24/QSOP-24 in DBQ pinout ....................................................................................................... 6
16 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC59281
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
TLC59281DBQ ACTIVE SSOP DBQ 24 50 Green (RoHS& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC59281
TLC59281DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC59281
TLC59281RGER ACTIVE VQFN RGE 24 3000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC59281
TLC59281RGET ACTIVE VQFN RGE 24 250 Green (RoHS& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR TLC59281
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
TLC59281RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TLC59281RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC59281RGER VQFN RGE 24 3000 367.0 367.0 35.0
TLC59281RGET VQFN RGE 24 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 2
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.Refer to the product data sheet for package details.
RGE 24 VQFN - 1 mm max heightPLASTIC QUAD FLATPACK - NO LEAD
4204104/H
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
PACKAGE OUTLINE
www.ti.com
4224376 / A 07/2018
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RGE0024C
A
0.08 C
0.1 C A B
0.05 C
B
SYMM
SYMM
4.1
3.9
4.1
3.9
PIN 1 INDEX AREA
1 MAX
0.05
0.00
SEATING PLANE
C
2X 2.5
2.1±0.1
2X
2.5
20X 0.5
1
6
7
12
13
18
19
24
24X
0.30
0.18
24X
0.50
0.30
(0.2) TYP
PIN 1 ID
(OPTIONAL)
25
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE BOARD LAYOUT
4224376 / A 07/2018
www.ti.com
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
2X
(0.8)
2X(0.8)
(3.8)
( 2.1)
1
6
7 12
13
18
1924
25
24X (0.6)
24X (0.24)
20X (0.5)
(R0.05)
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(Ø0.2) VIA
TYP
(3.8)
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
EXAMPLE STENCIL DESIGN
4224376 / A 07/2018
www.ti.com
VQFN - 1 mm max height
RGE0024C
PLASTIC QUAD FLATPACK- NO LEAD
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 20X
(3.8)
(0.57)
TYP
(0.57)
TYP
4X ( 0.94)
1
6
712
13
18
1924
24X (0.24)
24X (0.58)
20X (0.5)
(R0.05) TYP
METAL
TYP
25
(0.19)
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