16.2 Types of Semiconductor · 2016. 6. 8. · 1 16.2 Types of Semiconductor Memories (1) Computer memory can be divided into 2 types: main memory and mass storage memory. The main

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16.2 Types of Semiconductor Memories (1)

Computer memory can be divided into 2 types: main memory and mass storage memory. The main memory is usually of the random-access type. A random-access memory (RAM) is one in which the time required for writing and reading information is independent of the physical location in which the information is stored. RAMs should be contrasted with serial or sequential memories. Sequential access means that the accessing a piece of information will take a varying amount of time, depending on which piece of information was accessed last. The device may need to seek (e.g. to position the read/write head correctly), or cycle (e.g. to wait for the correct location in a revolving medium to appear below the read/write head). Floppy disk and hard disk are of this type.

Sedra-Smith 6th ed.

2

CPUHD

RAM

ROM

MEMORIEMEMORIE* OS* SW* dati storici

> lettura/scrittura> permanente> accesso sequenziale

* OS “live”* dati operativi (da elaborare/elaborati)

> lettura/scrittura> labile> accesso casuale

* dati di sistema - avvio (boot loader) - descrizione HW (bios)

> lettura> permanente> accesso casuale

©RICHARD C. JAEGER 6/5/97

MMIICCRROOEELLEECCTTRROONNIICIRCUIT DESIGNCIRCUIT DESIGN

MEMORIEMEMORIEa semiconduttorea semiconduttore

RAM ROM Random Access Memory Read Only Memory

Architettura matrice matrice

Accesso casuale casuale

Permanenza labile perenne

Lettura/scrittura sì solo lettura

Contenuto dati operativi dati di sistema

4

Types of Semiconductor Memories (2)

Source: G. Chou at ProMOSSedra-Smith 6th ed.

5

Dynamic Memory Cell (1)

Where can we find DRAMs?

Sedra-Smith 6th ed.



Row Decoder

12

N

12 rows

M

One Storage Cell

Row Address

Column Decoder

2M

1 2

M

Read/write Circuit

Data Out

Data In

2 columnsN

Cell Array

Column Address

Bitline

Wordline

1 2N

Sense Amplifiers

Row

D e c o d e r

Figure 9.2 - Block diagram of basic memory array



BL

Wordline

BL__

D = D1 D = D2

__

MA1 MA2

Figure 9.5 - Basic memory cell formed from the two-inverter latch and two access

transistors MA1 and MA2



BL BL__

Read "0"

+3 V

1.5 V 1.5 V

MP1 MP2

MA1 MN1 MN2

0 V 3 V

MA2

D1 D2

WL WL

Sense Amplifier

CBLCBL

Precharge

Figure 9.7 - Reading data from a 6-T cell with a "0" stored in the cell



BL__

BL

+1.5 V+1.5 V

+3 V +3 V

MA1 MA2

offMP1

offMN2

i2

MP2

MN1

i1

+3 V

0 V 3 V

WL

D DS S

G G

D1

D2

Figure 9.8 - Conditions immediately following activation of the wordline



BL BLWordline

MA1 MA2

Storage Cell

Sense Amplifier

Precharge

MPC

D1D

2

Figure 9.23 - Memory array including a sense amplifier



Read "1"

+3 V+3 V

1.5 V 1.5 V

MP1 MP2

i1

MA1 MN1

BL

MN2

0 V3 V

+3 V

MA2

i2

BL__

D1 D2

G

D

G

DS S

CBL CBL

Figure 9.11 - Reading data from 6-T cell with a "1" stored in the cell



0 V +3 V

Write "0"

+3 V

MP1 MP2

i1

MA1 MN1

BL

MN2

0 V 3 V

WL

MA2

i2

BL__

D1 D2

WL

CBL CBL

Figure 9.12 - Memory cell set up for a write "0" operation with a "0" already stored in the

cell



0 V +3 V

Write "0"

+3 V+3 V

MP1 MP2

i1

MA1 MN1

BL

MN2

0 V3 V

+3 V

MA2

i2

BL__

D1 D2

CBLCBL

Figure 9.13 Memory cell set up for a write "0" operation with a "1" previously in the cell



Bitline

CBL CC

Wordline

MA

Figure 9.15 - One-transistor (1-T) storage cell in which binary data is represented by the

presence or absence of charge on CC



0 V

+3V

VC

CC

S D

G

BL

iC

iC

MA

Figure 9.16 - Writing a "0" into the 1-T cell



+3 V

+3 V

VC

CC

BL

D S

G

iC

iC

MA

Figure 9.17 - Conditions for writing a "1" into the 1-T cell



A0

A0

_A

1A

2A

1

_A

2

_V

DD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

1 (001)

2 (010)

3 (011)

4 (100)

5 (101)

6 (110)

7 (111)

A0

A1

A2

0 (000)

Figure 9.31 - NMOS static NOR address decoder



VDD

W1

B1

B2

B3

B0

W3

W0

2W

Fig. 9.42 - Basic structure of a NMOS static ROM with four 4-bit words:

W0 = 0010 W1 = 1000 W2 = 0110 W3 = 0110

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Mask-Programmable ROMs and PROMs

Mask-programmable ROMs To avoid having to custom-design each ROM from scratch, ROMs are manufactured using a process known as mask programming. MOSFET can be included at all bit locations, but only the gates of those transistors where 0s are to be stored are connected to the word lines.

Programmable ROMs PROMs are ROMs that can be programmed by the user, but only once (They are frequently seen in computer games, or such products as electronic dictionaries). A typical PROM comes with all bits reading as 0, burning a fuse during programming causes its bit to read as 1. The memory can be programmed just once after manufacturing by "blowing" the fuses (using a PROM blower), which is an irreversible process.

22

EPROMs (1)

Erasable-Programmable ROMs It is a type of computer memory chip that retains its data when its power supply is switched off. Once programmed, an EPROM can be erased only by exposing it to strong ultraviolet light (wavelength=2537A). EPROMs are easily recognizable by the transparent window in the top of the package, through which the silicon chip can be seen, and which permits UV light during erasing.

Sedra-Smith 6th ed.

Microelectronic Circuits, International Sixth Edition Sedra/Smith Copyright © 2011 by Oxford University Press, Inc.

Figure 16.31 (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell.

Its structure and programming principle are illustrated below. EPROMs (2)

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EPROM

Typ. 2 V 7 V

EPROM Scrittura/Cancellazione

25 V

16 V Gnd

Write (Program) process – hot-carrier injection Erase process – UV light

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EEPROMs

A more versatile PROM is the electrically erasable PROM (EEPROM). As the name implies, an EEPROM can be erased and reprogrammed electrically without the need for ultraviolet illumination. The difference between EPROM and EEPROM lies in the thickness of the insulating layer — in an EPROM it is about 25 nm thick whereas in an EEPROM it is much thinner — typically around 10 nm. This thinner insulating layer allows for lower voltages to be used for programming.

EEPROM

Transistore

Scrittura e Cancellazione

29

Flash Memory

Flash memory is a form of non-volatile computer memory that can be electrically erased and reprogrammed. Unlike EEPROM, it is erased and programmed in blocks consisting of multiple locations. Flash memory costs far less than EEPROM and therefore has become the dominant technology wherever a significant amount of non-volatile, solid-state storage is needed.

Source: Samsung ElectronicsSedra-Smith 6th ed.

Flash Memory

• Struttura NOR– scrittura: Channel Hot Electrons (CHE)– cancellazione: Fowler-Nordheim Tunneling

Read

Write

Erase

12 V

12 V

12 V > VT2

12 V

12 V

VT1 < 5 V < VT2

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16.2 Types of Semiconductor · 2016. 6. 8. · 1 16.2 Types of Semiconductor Memories (1) Computer memory can be divided into 2 types: main memory and mass storage memory. The main