IEEE Catalog Number: ISBN:

CFP1221B-PRT 978-1-4673-0184-8

2012 VIII Southern Conference on Programmable Logic (SPL 2012)

Bento Gonçalves, Spain 20 – 23 March 2012

An Open-Source Framework for Heterogeneous MPSoC Generation 1Eduardo Wächter, Carlo Lucas, Everton Carara and Fernando Moraes A Co-Design Methodology for Processor-Centric Embedded Systems with Hardware 7Acceleration Using FPGA Sol Pedre, Tomas Krajnik, Elias Todorovich and Patricia Borensztejn HardNoC: A Platform to Validate Networks on Chip through FPGA Prototyping 15 Guilherme Heck, Ricardo Guazzelli, Rafael Soares, Fernando Moraes and Ney Calazans Memory Bandwith Reduction in Video Coding Systems Through Context Adaptive 21Lossless Reference Frame Compression Dieison Silveira, Gustavo Sanchez, Mateus Grellert, Vinicius Possani and Luciano Agostini

Real Time QHDTV Motion Estimation Architecture Design for DMPDS Algorithm 27Gustavo Freitas Sanchez, Marcelo Porto, Sergio Bampi and Luciano Agostini Hardware-Based Computation of the Roughness Index for Infrared Imagers 33 Rodolfo Redlich, Gonzalo Carvajal, Miguel Figueroa and Juan Pablo Moreno A High Performance and Low Memory Bandwidth Architecture for Motion Estimation 39 Targeting High Definition Digital Videos Alba Sandyra Bezerra Lopes, Ivan Saraiva Silva and Luciano Volcan Agostini Memory Efficient FPGA Implementation of Motion and Disparity Estimation for the 45Multiview Video Coding Felipe Sampaio, Bruno Zatt, Sergio Bampi and Luciano Agostini

A Fast Interpolative Wordlength Optimization Method for DSP Systems 51Enrique Sedano, Juan A. López and Carlos Carreras Low Cost and High Throughput Multiplierless Design of a 16 Point 1-D DCT of the 57New HEVC Video Coding Standard Ricardo Jeske, José Cláudio De Souza Jr., Gustavo Wrege, Ruhan Conceição, Mateus Da Silva, Júlio Mattos and Luciano Agostini An MPEG-4 AAC Decoder FPGA Implementation for the Brazilian Digital Television 63Adriano Renner and Altamiro Susin Very High Throughput FPGA Design for Vertical Rotational Transform of HEVC 69Emergent Video Coding Standard

Henrique Vianna, Virginia Andersson, Gustavo Sanchez and Luciano Agostini

The Impact of Operating System Adoption in an Embedded Project: a Case Study 74Ricardo Jasinski, Maiko Moroz and Volnei Pedroni Integration of IPs into the M8051 Microcontroller 81Thiago Mussolini, Tales Pimenta, Robson Moreno, Paulo Crepaldi and Leonardo Zoccal Revisiting Atari 2600 on an FPGA 87Guilherme Flach, Calebe Conceição, Marcelo Johann and Ricardo Reis Real-Time Scheduling Coprocessor for NIOS II Processor 93Martín Varela, Ricardo Cayssials, Edgardo Ferro and Eduardo Boemo Memory-Mapped I/O Over Dual Port BRAM on FPGA 99 Rodrigo Melo, David Caruso and Salvador Tropea

FPGA Design of H.264/AVC Intra-Frame Prediction Architecture for High Resolution 105Video Encoding Cláudio Diniz, Altamiro Susin and Sergio Bampi FPGA Based Hardware Architecture for Motion Vector Predicton in H.264/AVC 111Encoders Targeting HD1080p Resolution Daniel Palomino, Felipe Sampaio, Sergio Bampi, Altamiro Susin and Luciano Agostini Towards a Video Processing Architecture for SBTVD 117Marcelo Negreiros, Altamiro Susin, Alexsandro Bonatto, Andre Borin and Henrique Klein Optimized 16x16 Discrete Cosine Transform Architecture for Homogeneity-Based 123 H.264/AVC Intra Mode Decision Renato Souza, Roger Porto, Leomar Da Rosa Jr. and Luciano Agostini

FPGA Implementation of Robust Asynchronous Wrappers for Globally–Asynchronous 129Locally–Synchronous Systems (GALS) Duarte L. Oliveira, Lester De Abreu Faria and Eduardo Lussari A High Throughput Configurable FFT Processor for WLAN and WiMax Protocols 135Renan Oliveira Netto and Jose Luis Guntzel HW/SW FPGA Design for Active Control of Flexible Structures 140Leonardo Bandeira Soares, Marco Terres, Sebastião Gomes, Vitor Gervini and Vagner Rosa An Efficient Packing Algorithm Based on Constraint Satisfaction Problem Technique 146Meng Yang and Jiarong Tong

Background Subtraction Algorithm for Moving Object Detection in FPGA 151Camilo Sánchez-Ferreira, Jones Yudi Mori and Carlos Humberto Llanos Image Convolution Processing: a GPU versus FPGA Comparison 157Lucas Russo, Emerson Pedrino, Edilson Kato and Valentin Roda FPGA Implementation of Hardware Countermeasures 163Raúl Jiménez-Naharro, Guillermo Feria-Revilla, Manuel Sánchez-Raya, Juan-Antonio Gomez-Galan and Fernando Gómez-Bravo

Applying in Education an FPGA-Based Methodology to Emulate ASIC Soft Cores and 169Test ICs Cezar Rodolfo Wedig Reinbrecht, Julio Leao Da Silva Jr and Eric Ericson Fabris Historic Behavior of the Electronic Technology: the Wave of Makimoto and Moore's 174Law in the Transistor's Age Pablo A. Salvadeo, Angel C. Veca and Rafael Castro Lopez Adapting a Low Complexity Datapath to MIPS-1 179Leonardo Casillo and Ivan Saraiva A Basic Processor for Teaching Digital Circuits and Systems Design with FPGA 185Maicon Pereira, Paulo Vieira, André Raabe and Cesar Zeferino

FPGA Implementation of the Parity Check Node for Min-Sum LDPC Decoders 191Fernando Gutierrez, Graciela Corral-Briones and Damián Morero Design of an 8192-Bit RSA Cryptoprocessor Based on Systolic Architecture 197Claudia Patricia Renteria Mejia, Vladimir Trujillo and Jaime Velasco-Medina Secure Configuration Schemes for FPGA-based Systems with Simple Key 203Management Abdelghani Errandani, Abderrahim Doumar and Eric Châtelet

Generic Construction of Monitors for Floating Point Unit Designs 209Oscar Goñi, Oswaldo Cadenas and Elías Todorovich FPGA Implementation of Large-scale Matrix Inversion Using Single, Double and 217Custom Floating-Point Precision Janier Arias-Garcia, Carlos Humberto Llanos, Mauricio Ayala-Rincon and Ricardo Jacobi B-Spline Generation in FPGA 223Luiz Marcelo Chiesse Da Silva and Maria Stela Veludo De Paiva Implementation of a Fully Pipelined BCD Multiplier in FPGA 228Carlos Minchola

Clock Gating and Clock Enable for FPGA Power Reduction 234Juan Oliver, Juan Curto, Diego Bouvier, Manuela Ramos and Eduardo Boemo WL-Emap: Wirelength Prediction Based Technology Mapping for FPGAs 239Rodrigo Savage, Senthilkumar Rajavel and Ali Akoglu A Novel Application of FPGA-Based Partial Dynamic Reconfiguration System with 245CBSC Chenguang Guo