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ECE 218A Lab 3 Report 1.6GHz Low Noise Amplifier

Pen-Chin Pan (6064612)

Luis Chen (5977160)

December 5, 2005

11E91E8 5E9

-40

-30

-20

-10

0

10

-50

20

freq, Hz

dB(S

(1,1

))

m2

dB(S

(2,1

))

m1m7 m8

dB(S

(2,2

)) m3

dB(l

arge

_sig

nal_

bias

..SP

1.S

P.S

(1,1

))

m5

dB(l

arge

_sig

nal_

bias

..SP

1.S

P.S

(2,1

))

m6

dB(l

arge

_sig

nal_

bias

..SP

1.S

P.S

(2,2

))

m4

m2f req=dB(S(1,1))=-10.959

1.608GHz

m1f req=dB(S(2,1))=15.232

1.608GHz

m7f req=dB(S(2,1))=13.637

1.398GHz

m8f req=dB(S(2,1))=13.274

1.749GHz

m3f req=dB(S(2,2))=-13.093

1.608GHz

m5f req=dB(large_signal_bias..SP1.SP.S(1,1))=-8.860

1.600GHz

m6f req=dB(large_signal_bias..SP1.SP.S(2,1))=16.498

1.600GHz

m4f req=dB(large_signal_bias..SP1.SP.S(2,2))=-18.481

1.600GHz

S21

S11

S22

S-parameter Measurement vs. Simulation

3dB BW = ~400MHz

Introduction

Narrow band tuned Low-Noise Amplifiers are commonly used in wireless communication front-ends due to its amplification with low noise performance. It is commonly known that in a receiver system, the first stages within a receiving chain need to provide substantial gain and low noise figure in order for the entire system to have adequate noise performance. Designing and building a 1.6GHz LNA requires investigation into both in-band and out of band stability analysis, bilateral gain and noise match with microstrip matching network, DC bias design, and finally PCB parasitic modeling. Approach: Upon receiving the specifications, we first evaluate the small-signal model of NE34018 in ADS in terms of stability, gain circles, and noise circles. After determining good bilateral matching impedance, we designed a shut-series microstrip lossless matching network. Then we design the active bias circuit and test the amplifier design with NE34018’s large-signal model with added PCB parasitics (component and via holes) for full evaluation. Specification: Goal Accomplishment

Gain > 15dB 15.23dB Bandwidth (3 dB) > 100MHz 439MHz

|S22| < -10dB @ 1.6GHz -13.1dB @ 1.6GHz Noise Figure < 1.6dB 1.88dB

Power Supply +3.5V, -2.5V +3.5V, -2.5V Vds 2V 1.96V

Id 10mA 10.36mA

2

Design Procedure Stability Evaluation:

We observe that the transistor is unstable at frequencies below 4.5GHz (K < 1). From the Load stability circle, we could calculated the required stabilizing resistor value

3

By picking a constant conductance point at the Load stability circle, we could derive a load-side shunt stabilizing resistor of 60 Ohm using smith chart.

After placing the load-side shunt stabilizing resistor (60Ohm), we could see the circuit is stable above 1.6GHz. However, there remains some instability at lower frequencies, which would require low-frequency stabilizing resistors.

4

Gain and Noise Circles:

Here we plotted the source gain circles (gacir), load gain circles (gpcir), and noise figure circles (nfcir).

5

We assume the load is

conjugately matched to output for all gamma_S , so we plot noise circles and gacir on source plane. We picked a point on gacir2 that is furthest from the source stability circle and within the 1.5dB NF circle. This way, we only gave up 2dB of gain in exchange for <1.5dB Noise Figure and stability.

After picking gamma_S point on gacir, we could plug into equations to calculate gamma_L, which would lead to the design of matching network. The calculated gamma_L value landed inside -1dB gpcir.

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Matching Network: From the above gain circles and NF circles, we found out: Gamma_L = -0.181 + j*0.292, Z_L= 50*(0.596 + j*0.395) Gamma_S = 0.550 + j*0.512, Z_S = 50*(0.935 + j*2.204) Using Smith chart, we obtained the lengths of shunt-series microstrip matching network. We could verify it by using the following testbench:

Designed value: Z_S = 50*(0.935 + j*2.204) Z_L= 50*(0.596 + j*0.395)

Gamma_S, Z_Source

Gamma_L, Z_Load

7

System Simulation with Ideal Linear Model:

With linear and ideal microstrip lines, we achieved: Gain 17.07 dB Bandwidth (3 dB) 390 MHz |S22| -45.2 dB Noise Figure 0.72 dB

8

System Simulation with NON-Ideal Linear Model: Now we replace ideal microstrip into MSUB model and calculate their physical dimension from LineCalc. Ground via models are included to accurately model the inductive parasitic. Also T-junctions models are employed to increase modeling accuracy as well. With linear and NON-ideal microstrip lines, we achieved: Gain 17.99 dB Bandwidth (3 dB) 400 MHz |S22| -26.9 dB Noise Figure 0.97 dB Comparing to ideal T-line simulation, this result provides more realistic insight considering possible parasitics. For example, increase in NF and decrease in S22 may be results of including real-world parasitic models.

9

System Simulation with NON-Ideal NON-Linear Model: In order to fully and accurately account for non-ideality and non-linearity existing within the device or PCB/components, we must verify our design with simulation of a non-linear transistor model. First of all, the non-linear transistor requires DC bias circuits. Active DC Bias: The biasing is implemented with active bias circuit in order to provide a stable bias point to the LNA. From the device’s Spec sheet, we found the transconductance gm of the GaAs FET to be 30mS and threshold voltage Vth to be -0.69V, thus from Id=gm(Vgs-Vth), we determined that the Vgs required for an Id of 10mA to be -0.36V. We tested the bias point in ADS, and determined Vgs to be -0.52V. We then chose Ic of the bias circuit to be 1mA. With Vgs, Ic and Vds known, we chose bias resistors to give the correct bias point.

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LNA (excluding biasing network) with non-linear model and non-linear microstrip models:

System simulation testbench (including DC biasing):

These two short T-line section is to model Microstrip line connecting from matching network to SMA connector. Ideally, they should not change the result.

DC Active Biasing Network

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Result: With NON-linear model and NON-ideal microstrip lines, we achieved: Gain 15.14dB Bandwidth (3 dB) 310 MHz |S22| -17.4 dB Noise Figure 1.06dB The NON-linear transistor model caused our gain to degrade by almost 3dB, yet it seems to provide better overall stability than the linear model. In fact, the amplifier is overstablized (min K value = 1.4) and we could gain more S21 headroom by adjusting stability resistor value.

Stabilizing resistor changed to 100 Ohm from 60 Ohm.

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New result after increasing stabilizing resistor: After adjusting stabilizing resistor value, we achieved: Gain 16.6dB Bandwidth (3 dB) 310 MHz |S22| -19.2 dB Noise Figure 1.03dB The amplifier now has adequate gain margin (1.6dB above spec) to handle any other unexpected non-ideality within the final circuit assembly. We would proceed to PCB fabrication and assembly with this design.

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PCB Layout Fabricated and Assembled PCB:

DC bias is fed through the matching network’s inductive shunt stubs. Such implementation avoids addition RF choke which introduces additional parasitic and costs.

Also notice the long GND via’s along the end of shunt stubs. These “sliders” could be used to fine-tune stub length to account for via’s length and inductance.

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Test Result Stability Spectrum Analyzer setup Cable Loss -2.28dB Input -30dBm Span 2Ghz Attenuation 10-dB Res BW 100kHz

m1freq=TraceA=-72.930

1.512GHz

0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.50.6 2.6

-77.5

-77.0

-76.5

-76.0

-75.5

-75.0

-74.5

-74.0

-73.5

-73.0

-78.0

-72.5

freq, GHz

Tra

ceA

m1 m1freq=TraceA=-72.930

1.512GHz

RF_in = -30dBm, Attenuation = -10dBm, cable loss = -2.5dB

We can see that with the signal generator off, the LNA output is very low across the entire desired frequency range. The highest output was at -72.93 dB.

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m2freq=SA_span_2ghz..TraceA=-27.550

1.605GHz

0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.50.6 2.6

-65

-60

-55

-50

-45

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-35

-30

-70

-25

freq, GHz

SA

_sp

an

_2

gh

z..T

race

A

m2

m2freq=SA_span_2ghz..TraceA=-27.550

1.605GHz

With the signal generator on at 1.6Ghz, the only signal present at the output is detected at 1.6Ghz with no other signals in the neighborhood.

-45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50-50 55

-80

-75

-70

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-30

-85

-25

freq, MHz

SA

_lo

w_freq_sp

ur..T

race

A

m3

m3freq=SA_low_freq_spur..TraceA=-27.930

800.4kHz

We then took a closer look at the output spectrum, and did a sweep across all interested frequencies. We found an output at about 800Khz, which we suspect that it is due to the SA’s local oscillator generating a signal at the output.

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1E91E8 1E10

-40

-30

-20

-10

0

10

-50

20

freq, Hz

dB(S

(1,1

))

m2

dB(S

(2,1

))

m1

dB(S

(2,2

))

m3

dB(la

rge_

sign

al_b

ias.

.SP

1.S

P.S

(1,1

))

m5

dB(la

rge_

sign

al_b

ias.

.SP

1.S

P.S

(2,1

))

m6

dB(la

rge_

sign

al_b

ias.

.SP

1.S

P.S

(2,2

))

m4

m2freq=dB(S(1,1))=-10.959

1.608GHz

m1freq=dB(S(2,1))=15.232

1.608GHz

m3freq=dB(S(2,2))=-13.093

1.608GHz

m5freq=dB(large_signal_bias..SP1.SP.S(1,1))=-8.980

1.600GHz

m6freq=dB(large_signal_bias..SP1.SP.S(2,1))=16.584

1.600GHz

m4freq=dB(large_signal_bias..SP1.SP.S(2,2))=-19.222

1.600GHz

S21

S11

S22

S-parameter Measurement vs. Simulation

S Parameter Measurements S21 (Gain) 15.232 dB S22 -13.093 dB Bandwidth 439 MHz

1E9 1E101E8 2E10

-60

-55

-50

-45

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-35

-30

-25

-20

-15

-10

-5

0

5

10

15

-65

20

freq, Hz

dB

(S(1

,1))

dB

(S(1

,2))

dB

(S(2

,1))

m7m9m10

dB

(S(2

,2))

m8

m7freq=dB(S(2,1))=15.232

1.608GHzm8freq=dB(S(2,2))=-13.093

1.608GHzm9freq=dB(S(2,1))=12.574

1.798GHzm10freq=dB(S(2,1))=12.641

1.359GHz

S21

S11

S22

S12

We met the spec for gain and bandwidth as well as S22. Our measurements came out to be very close to the simulated results as shown in the illustration above.

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Noise Figure

Frequency (Mhz)

NF (dB)

1600 2.28 1590 2.1 1580 1.86 1570 1.92 1560 1.96 1550 1.95 1540 1.98 1530 2.08 1520 2.16 1510 2.18 1500 2.71

Our measurements for Noise Figure came out to be little bit high. The lowest NF is at 1580Mhz. The measured NF is higher than our simulated result. Variations in the testing environment are probably the cause to this discrepancy. Wires to the supply voltage could inject extra unwanted noise to the circuit as well. Gain Compression Pin (dBm)

Pout (dBm)

Gain

-50 -46.8 -5.7 -45 -41.8 -5.7 -40 -36.9 -5.6 -35 -31.9 -5.6 -30 -26.9 -5.6 -25 -21.9 -5.6 -20 -16.9 -5.6 -19 -15.9 -5.6 -18 -14.9 -5.6 -17 -13.9 -5.6 -16 -13.05 -5.45 -15 -12.3 -5.2 -14 -11.62 -4.88 -13 -11.11 -4.39 -12 -10.7 -3.8 -11 -10.4 -3.1 -10 -10.19 -2.31 -5 -9.46 1.96 0 -8.77 6.27 5 -8.06 0.56

Our measured P1dB input power is at -13dBm, shown on the table above.

NF vs Frequency

0

0.5

1

1.5

2

2.5

3

1480 1500 1520 1540 1560 1580 1600 1620

Frequency (Mhz)

NF

(dB

)

Pout vs Pin

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0

-60 -50 -40 -30 -20 -10 0 10

Pin(dBm)

Pout

(dB

m)

P1dB = -13dBm

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Cost Analysis and Power Dissipation Bill of Materials: Amplifier

Component Part Number Quantity Price

(1000+)

NEC 34018 GaAs

HJ-FET NE85639RTR-ND 1 $2.57 Chip capacitors GRM155R61A154KE19-ND 4 $0.12 Chip resistors ERJ-S02F2000X-ND 2 $0.60 Leaded resistor 2 $0.05 Tantulum capacitor 3 $0.30 Variable Resistor 2 $0.30 2N3906 BJT 2N3906TFR 2 $0.17 SUBTOTAL $5.59 Eval board PCB board PCB Express Mini Board 1 $51 SMA Connector SMA 4959-ND 2 $14.64 SUBTOTAL $74.64 GRAND TOTAL $71.23 The cost of this amplifier would be dominated by the PCB, and SMA connector’s costs. However, at large scale manufacturing, the costs of PCB would drastically decrease. Power Dissipation: To measure DC power dissipation, we measured the voltage drop at resistor R12 and R10. Then we calculate the total DC current from these measurements, and therefore calculate the DC dissipation. Total DC current: 11.3mA+.505mA=11.805mA DC voltage: 3.5V Power Dissipated: 3.5V x 11.805mA = 41.32mW

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f req

1.600 GHz

SP2.MaxGain1

17.683

SP2.SP.nf (2)

1.012

SP2.SP.NFmin

0.445

SP2.StabFact1

1.259

mag_delta

0.378

freq

1.600 GHz

...e_signal_bias..SP2.MaxGain1

17.551

...ge_signal_bias..SP2.SP.nf(2)

1.030

...e_signal_bias..SP2.SP.NFmin

0.457

...e_signal_bias..SP2.StabFact1

1.254

mag_delta

0.378

Sensitivity of Circuit Under Device/Supply Variations Since the discrete component count is greatly reduced by lumped microstrip matching network, the amplifier is less prone to critical component (discrete matching network) variation under the assumption of adequate PCB fabrication precision (ie. PCB trace dimensions). Thus, we will only perform test on varying supply voltages. Varying Supply Voltage We test our circuit with 10% supply voltage variation: V_positive = 3.5V + 0.35V = 3.85V V_negative = -2.5V – 0.25V = -2.75V

S-parameter performance was not affected much under supply variation. S-parameters overlap for before and after 10% variation. Noise and stability were not jeopardized with 10% supply voltage variation. Conclusion: our LNA could withstand 10% change in supply without degrading gain, noise, S22 performances. This also proves that our failure in meeting the 1.6dB NF spec is most likely due to measurement setup and environment interferences.

Such variation yields the following DC bias: Id = 11.8mA (18% deviation from ideal 10mA) Vd = 2.17V (8.5% deviation from ideal 2V)

Original bias point

After 10% supply variation

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Conclusion The design and fabrication of 1.6GHz Low Noise Amplifier requires thorough understanding of narrow-band tuned microwave amplifier design principles and sgreat care in modeling circuit parasitic (device non-linearity, non-ideality, and PCB parasitic such as vias and discrete components). After several iteration of ADS simulation and optimization of circuit parameters, our LNA performs up to all specifications with the exception of noise figure. As illustrated in above sections, this failure is most likely due to environmental interference and could be improved by applying shielding to avoid interferer during future noise figure measurements.