1654 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER 2018

2/3 and 1/2 Reconfigurable Switched CapacitorDC–DC Converter With 92.9% Efficiency at

62 mW/mm2 Using Driver Amplitude DoublerToru Sai , Member, IEEE, Yoshitaka Yamauchi, Student Member, IEEE, Hajime Kando, Tatsuya Funaki,

Takayasu Sakurai, Fellow, IEEE, and Makoto Takamiya, Senior Member, IEEE

Abstract—A 2/3 and 1/2 reconfigurable switched capacitor (SC)dc–dc converter is developed for a per-core dynamic voltagescaling of many-core microprocessors. The power conversion effi-ciency and the output power density of the SC dc–dc converter in2/3 mode is degraded, because full-swing and half-swing driversfor power transistors are mixed and the resistive loss of thepower MOSFETs with the half-swing drivers is large. To solvethe problem, a fully integrated driver amplitude doubler (DAD) isproposed. In DAD, the gate amplitude of the power MOSFETs isincreased from half-swing to full-swing by generating a 1/3 inputvoltage sampled from a flying capacitor. In the fabricated 2.7-Vinput SC dc–dc converter mounting four 100-nF 0402 (0.4 mm ×0.2 mm × 0.2 mm) multilayer ceramic chip capacitors on 180-nmCMOS die achieves the highest efficiency of 92.9% at the outputpower density of 62 mW/mm2 in the published step-down SCdc–dc converters.

Index Terms—Switched capacitor (SC), DC-DC converter, step-down, driver amplitude doubler (DAD), multilayer ceramic chipcapacitor (MLCC), power density.

I. INTRODUCTION

TO ENABLE an energy-efficient operation of many-coremicroprocessors, a fine-grained per-core dynamic voltage

scaling is required [1]. As the number of the cores increases,the required number of the power supply voltages (VDD’s) alsoincreases. Integrated voltage regulators (IVRs) are the solutionto generate multiple VDD’s on a chip, because increasing thenumber of off-chip voltage regulators is not practical. Key met-rics of IVRs are the power conversion efficiency (η), the outputpower (POUT), the form factor, the output power density (PD)(=POUT / area), and the cost.

The design target of this brief is to develop an IVRwith (1) η > 90%, (2) PD > 50mW/mm2, and (3) a low-cost bulk CMOS process. The conventional IVRs, however,

Manuscript received August 28, 2017; revised October 4, 2017; acceptedOctober 5, 2017. Date of publication October 12, 2017; date of current ver-sion October 29, 2018. This work was supported by Murata ManufacturingCompany, Ltd. This brief was recommended by Associate Editor H.-J. Chiu.(Corresponding author: Toru Sai.)

T. Sai, Y. Yamauchi, T. Sakurai, and M. Takamiya are with the Instituteof Industrial Science, University of Tokyo, Tokyo 153-8505, Japan (e-mail:sai@iis.u-tokyo.ac.jp).

H. Kando is with the Innovative Technology Development Department,Murata Manufacturing Company Ltd., Shiga 520-2393, Japan.

T. Funaki is with the JISSO Technology Development Department,Murata Manufacturing Company Ltd., Shiga 520-2393, Japan.

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSII.2017.2762347

Fig. 1. η vs. PD of state-of-the-art step-down DC-DC converters.

do not satisfy the design target. Fig. 1 shows η and PDof the state-of-the-art step-down DC-DC converters with theswitching frequency (f SW), the output voltage (VOUT), andthe output current (IOUT) including both buck convertersand switched-capacitor (SC) DC-DC converters. The designtarget of this brief is shown. In the fully integrated buckconverter [2], η of 72% is comparable to η = 67% of anideal LDO and η is too low due to the low quality fac-tor (Q = 4.5) of the on-chip inductor. In the buck converterwith on-interposer inductor [3], the lack of the scalability ofinductor [2] is a problem in IVRs, though both η = 90% andPD = 2.6W/mm2 satisfy the design target. In the fully inte-grated SC DC-DC converters using the bulk CMOS process,η = 79.76% [4], 81% [8], and PD = 1.3mW/mm2 [5] do notsatisfy the design target, which indicates the tradeoff betweenη and PD. In the fully integrated SC DC-DC converters usingthe deep trench capacitor process [6], η = 90% and PD =3.71W/mm2 are achieved. This approach does not satisfy thedesign target, because the deep trench capacitor process is notlow-cost and not generally available. In the SC DC-DC con-verters with off-chip capacitors, PD = 1.0mW/mm2 [7] do notsatisfy the design target.

To achieve the design target, in this brief, a 2/3 and1/2 reconfigurable SC DC-DC converter mounting four 100-nF0402 (0.4mm × 0.2mm × 0.2mm) multilayer ceramic chipcapacitors (MLCCs) on 180-nm CMOS die is developed

1549-7747 c© 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

SAI et al.: 2/3 AND 1/2 RECONFIGURABLE SC DC–DC CONVERTER WITH 92.9% EFFICIENCY AT 62mW/mm2 USING DAD 1655

Fig. 2. (a) Proposed 2/3 and 1/2 reconfigurable SC DC-DC converter.(b) Timing chart of conventional and proposed converter in 2/3 mode.

for the dynamic voltage scaling. The developed SC DC-DCconverter with the proposed fully-integrated driver amplitudedoubler (DAD) achieved η = 92.9% and PD = 62mW/mm2

at the input voltage (V IN) of 2.7V, VOUT of 1.71V, and IOUTof 100mA.

II. SC DC-DC CONVERTERS WITH

DRIVER AMPLITUDE DOUBLER

A. Gate Amplitude in 2/3 SC DC-DC Converters

In this chapter, the problem of the conventional 2/3 SCDC-DC converter is explained. Then, a new SC DC-DC con-verter with the proposed DAD is introduced. Fig. 2 (a) shows

Fig. 3. Proposed driver amplitude doubler (DAD).

Fig. 4. Gate/source/drain voltages of all power transistors in conventionalSC DC-DC converter in 2/3 mode.

a circuit schematic of the proposed 2/3 and 1/2 reconfigurableSC DC-DC converter with two flying capacitors (CFLY1 andCFLY2). In this brief, V IN is 2.7V and VOUT is 1.8V and 1.35Vin 2/3 and 1/2 mode, respectively, because all nine power tran-sistors are 1.8-V core transistors in 180-nm CMOS process.Fig. 2(b) shows a timing chart of the conventional and theproposed SC DC-DC converter in 2/3 mode. In the conven-tional SC DC-DC converter, the amplitude Φ1H and Φ2H is0.9V, because DAD in Fig. 2(a) is not used and VX is con-nected to VOUT. In contrast, in the proposed SC DC-DC con-verter, the amplitude Φ1H and Φ2H is doubled to 1.8V, becauseVX of 0.9V is generated by the proposed DAD shown in Fig. 3.

Figs. 4 and 5 show gate/source/drain voltages of all powertransistors in the conventional and the proposed SC DC-DCconverter in 2/3 mode, respectively. The conventional SCDC-DC converter is based on [4]. In the conventional SCDC-DC converter in Fig. 4, the resistive loss of M1, M2, M5,and M6 is large, because |VGS| of M1, M2, M5, and M6 is 0.9Vdue to the 0.9-V amplitude Φ1H and Φ2H. Thus, four powertransistors (M1, M2, M5, and M6) are weak ON out of theworking seven power transistors (M1, M2, M4, M5, M6, M8,and M9). Fig. 6 shows a simulated |VGS| dependence of ONresistance of pMOSFET. When |VGS| is reduced from 1.8Vto 0.9V, the ON resistance increases to x3, which degrades η

and PD. To achieve both high η and high PD, the full-swing(=1.8-V amplitude) |VGS| is the primary design goal. In theproposed SC DC-DC converter in Fig. 5, the resistive loss ofM1, M5, and M6 is reduced, because |VGS| of M1, M5, andM6 is doubled to 1.8V because of the 1.8-V amplitude Φ1Hand Φ2H thanks to DAD, thereby achieving higher η and PDthan the conventional SC DC-DC converter.

1656 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER 2018

Fig. 5. Gate/source/drain voltages of all power transistors in proposed SCDC-DC converter in 2/3 mode.

Fig. 6. Simulated VGS dependence of ON resistance of pMOSFET for powertransistor.

B. Proposed Driver Amplitude Doubler

How to generate VX of 0.9V is explained in Fig. 5. BothCFLY1 and CFLY2 are implemented with off-chip capacitors,while both CX1 and CX2 are implemented with on-chip MOSgate capacitors. DAD with and without CX2 block is discussed.In DAD without CX2 block, VX is 0.9V in Φ2 phase, becauseVX is connected to V1 of 0.9V. In Φ1 phase, VX goes above0.9V, because the charge (Q1) from the non-overlap clock gen-erator to drive the gate voltage of the power transistors (M1,M2, M5, and M6) from 2.7V to 0.9V is injected to VX. InDAD without CX2 block, VX in Φ1 phase is shown as,

VX = CX1V1 + CGVIN

CX1 + CG, (1)

where CG is the total gate capacitance of the power transis-tors (M1, M2, M5, and M6), CGV IN is the charge amount ofCG in Φ2 phase. Because V1 is equal to 1/3 V IN, Eq. (1) isrewritten as,

VX =13 CX1 + CG

CX1 + CGVIN. (2)

Fig. 7. Simulated CX1 or CX1 + CX2 dependence of VX.

Fig. 8. Simulated waveforms of VOUT, VX, �1H with CX2.

When CG is zero, VX is equal to 1/3 V IN. Actually, how-ever, CG is not neglected and VX is above 1/3 V IN (= 0.9V).When VX goes above 0.9V, M7 will be turned on, which isnot acceptable. Fig. 7 shows the SPICE simulated CX1 depen-dence of VX. To obtain VX of 0.9V, large CX1 is required andthe die area overhead is increased, which is not acceptable.

To prevent the rise of VX and the large area overhead ofCX1, DAD with CX2 block is proposed. In DAD with CX2block, in Φ2 phase, CX1 is charged to 0.9V and CX2 is chargedto 0V. VX in Φ1 phase is shown as,

VX = CX1V1 + CX2 · 0V + CGVIN

CX1 + CX2 + CG

=13 CX1 + CG

CX1 + CX2 + CGVIN. (3)

When CX2 is designed to be equal to 2 CG, VX is equal to1/3 V IN, which achieves the design target. Fig. 8 shows thesimulated waveforms of VOUT, VX, and Φ1H of Fig. 5 withCX2 block at IOUT = 100mA, f SW = 5MHz. The voltage VXsamples V1 by CX1 in Φ2 phase then holds V1 to 0.9V inΦ1 phase thanks to DAD with CX2 block. Fig. 7 shows thesimulated CX1 + CX2 dependence of VX. CX1 is fixed to 416pFand CX2 is varied. To obtain VX of 0.9V, the total requiredcapacitance (CX1 + CX2) is reduced by 84%, because CX2 ispre-charged to 0V instead of 0.9V. Thanks to the CX2 block,the area overhead of CX1 + CX2 is reduced.

III. MEASURED RESULTS

Fig. 9 shows a die photo and a layout of the 2/3 and1/2 reconfigurable SC DC-DC converter directly mountingfour 100-nF 0402 (0.4mm × 0.2mm × 0.2mm) MLCCs(GRM022R60G104ME15) on 180-nm CMOS die. In Fig. 2(a),all nine power transistors are 1.8-V core transistors and other

SAI et al.: 2/3 AND 1/2 RECONFIGURABLE SC DC–DC CONVERTER WITH 92.9% EFFICIENCY AT 62mW/mm2 USING DAD 1657

Fig. 9. Die photo and layout of reconfigurable SC DC-DC converter.

Fig. 10. Die photo of reconfigurable SC DC-DC converter on PCB.

Fig. 11. Thermal shock test.

block also use 3.3-V I/O transistors. Die size is 3.3mm by1.8mm and the core area is 2.1mm by 1.3mm. Four MLCCsare used for CIN, CFLY1, CFLY2, and COUT. CX1 of 416pFand CX2 of 69pF are implemented on the die. V IN is fixed to2.7V. Fig. 10 shows a die mounted on PCB.

The mounting of MLCCs on the silicon die is also reportedin [9], however, the reliability of the mounting may be anissue, because the coefficients of thermal expansion of MLCCsand the silicon are different. To verify the reliability of themounting, the thermal shock testing is done using the ther-mal shock chamber (Espec TSA-71H-W). Fig. 11 shows thethermal profile of the one cycle of the thermal shock test-ing specified in the testing standard (JIS C 60068-2-14 [10]).η of three SC DC-DC converters in 2/3 mode and IOUT of100mA before and after the 101-cycle thermal shock are mea-sured and compared. The measured η change is very small(Sample 1: η = 92.88% to 92.96%, Sample 2: η = 93.08%to 93.14%, and Sample 3: η = 92.87% to 92.99%), indicatingthat the mounting of MLCCs on the silicon die is reliable.

Fig. 12. Measured clock frequency dependence of efficiency in (a) 2/3 modeand (b) 1/2 mode at different IOUT.

Fig. 13. Measured VOUT dependence of efficiency in 2/3 and 1/2 mode withvaried clock frequency at IOUT = 10mA.

Fig. 12 shows the measured clock frequency dependence ofη in 2/3 and 1/2 mode at different IOUT. In 2/3 mode and IOUTof 100mA, the peak η of 92.9% is obtained at 4MHz and VOUTof 1.71V, achieving POUT of 171mW and PD of 62mW/mm2.In 2/3 mode and IOUT of 10mA, the peak η of 94.6% isobtained at 600kHz and VOUT of 1.75V, achieving POUT of17.5mW and PD of 6.4mW/mm2. In 1/2 mode and IOUT of100mA, the peak η of 92.7% is obtained at 4MHz and VOUT of1.28V, achieving POUT of 128mW and PD of 47mW/mm2. In1/2 mode and IOUT of 10mA, the peak η of 94.5% is obtainedat 500kHz and VOUT of 1.31V, achieving POUT of 13.1mW andPD of 4.8mW/mm2. Fig. 13 shows the measured VOUT depen-dence of η in 2/3 and 1/2 mode with varied clock frequency at

1658 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER 2018

Fig. 14. Measured IOUT dependence of efficiency in 2/3 and 1/2 mode.

Fig. 15. Measured VOUT and Clk at IOUT = 100mA in 2/3 mode.

Fig. 16. Measured VOUT and Clk at IOUT = 100mA in 1/2 mode.

IOUT = 10mA. The operation of the 2/3 and 1/2 reconfigurableSC DC-DC converter is demonstrated.

Fig. 14 shows the measured IOUT dependence of η of theproposed 2/3 and 1/2 reconfigurable SC DC-DC converter at5MHz. In 2/3 mode, the peak η of 93.3% is obtained at IOUTof 70mA and VOUT of 1.74V, achieving POUT of 122mWand PD of 45mW/mm2. In 1/2 mode, the peak η of 92.8%is obtained at IOUT of 90mA and VOUT of 1.30V, achievingPOUT of 117mW and PD of 43mW/mm2.

Figs. 15 and 16 show the measured waveforms of VOUT andClk of the SC DC-DC converter in 2/3 and 1/2 mode, respec-tively. V IN is 2.7V and f SW is 5MHz. The peak-to peak spikenoise are 127mV and 83mV in 2/3 and 1/2mode, respectively.

Table I shows the comparison with the state-of-the-artstep-down SC DC-DC converters. The proposed SC DC-DCconverter using the low-cost bulk CMOS process and MLCCsachieved the highest η of 92.9% at PD = 62mW/mm2 in thepublished step-down DC-DC converters, achieving the designtarget.

TABLE ICOMPARISON WITH STATE-OF-THE-ART STEP DOWN SC DC-DC

CONVERTERS

IV. CONCLUSION

The 2/3 and 1/2 reconfigurable 2.7-V input SC DC-DC con-verter mounting four 100-nF 0402 MLCCs on 180-nm CMOSdie is developed for IVRs. The reliability of the mounting ofMLCCs on the silicon die is measured and verified. Thanks tothe proposed fully-integrated DAD, the SC DC-DC converterin 2/3 mode at VOUT of 1.71V and IOUT of 100mA achievedthe highest η of 92.9% at PD = 62mW/mm2 in the publishedstep-down DC-DC converters.

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