2.4.2.A Programming Tutorial - Socorro … · Web view2.4.2.A Programming Tutorial Subject Digital Electronics - PLTW Keywords APB Last modified by Sanchez, Gerardo - Teacher Math,

Activity 2.4.2 Programmable Logic Devices: PLD Mode – Digital MiniSystem (DMS)IntroductionWhen circuit designs become too large or complex to realistically breadboard, designers often use a Programmable Logic Device to (PLD) to prototype and test a circuit. A PLD is an integrated circuit whose logic function is user-configurable. Unlike discrete logic gates—such as the AND, OR, NAND, and NOR gates, whose functionality is fixed when they are manufactured—a PLD must be programmed before use.

The first user-configurable PLD was introduced in 1978. This PLD was called a Programmable Array Logic (PAL), and it contained 24 user input/output signals. Over the three decades since the PAL was first introduced, the complexity of the devices and level of integration has increased significantly. The current state-of-the-art for PLDs is the Field Programmable Gate Array (FPGA). The FPGA referenced in this activity is the Cmod S6.

In this activity, you will learn how to use the Circuit Design Software (CDS) to program the FPGA on the DMS.

EquipmentThese instructions assume that all necessary software has been installed and configured by your teacher in the DE classroom. If you are not in a DE classroom environment, and you wish to install all software associated with the Digital MiniSystem, please refer to the DMS Startup Instructions.

DMS: PLD Module (Cmod S6)

Hardware Platform: Digital MiniSystem (DMS) PLD Module (Cmod S6)

Circuit Design Software (CDS): Multisim 14.0

Xilinx Programming Software (XPS): LabVIEW 2014 FPGA Module Xilinx Tools 14.7Note: Xilinx 14.7 is used to create a bit file and load it to the FPGA. When you use the process outlined in this document, it is not necessary to open Xilinx tools to load the FPGA.

© 2014 Project Lead The Way, Inc. Digital Electronics Activity 2.4.2 Programmable Logic Devices: PLD Mode (DMS) – Page 1

PIO25

PIO24

PIO48

PIO1

Note: Xilinx does not support Windows 8

PLD Module (Cmod S6) Transfer → Export to PLD ProcessPart 1: Setting Up the CDS (Multisim) in PLD Mode

1. Start the CDS.Select: Options → Global options.

2. Select: Options → Global options → Paths → Miscellaneous → Xilinx tools path.Make sure the Xilinx tools path is set to: C:\NIFPGA\programs\Xilinx14_7\ISENote: Your instructor may provide a different path for you to navigate to.

3. Select: Apply. Select: OK.

This is a one-time setup, which your instructor may have already completed.

Note: If your classroom supports both the Digital Logic Board (DLB) and Digital MiniSystem (DMS), you will need to check the path given in step 2 in Global Options to make sure the correct Xilinx Software is selected.


4. Create a new folder and name it “Tutorial”. Make sure this folder is in a location you typically have access to if using a computer that does not have full admin rights.

5. Select: File → New (Ctrl+N)

This will open the PLD Wizard. Select: PLD design.


6. New PLD Design – Step 1 of 3:

a. Select: Use standard configuration

b. Select: Digilent CmodS6c. Select: Next


a. PLD Design name: Name this file “Tutorial”. Note: The XPS, which you will use later in this tutorial, does not accept numbers, spaces, and some special characters in file names. Select: Next.



For this example, we will program a simple OR gate. Select: “Uncheck all” and then individually select the desired connectors. Use BTN0, BTN1, and LD0. Select: Finish.

The CDS will open a sheet in PLD mode with two port connectors on the left (the buttons) and one on the right (the LED).

9. To remove a port connector, simply delete it.

10.To add a port connector, select Place → Connector. Then choose the appropriate connector for the design.

11.To change port connector names and functions (Mode), right-click a connector and choose Properties.

To ignore the error message that follows a change, select YES.


Part 2: Simulating a PLD Mode Design in the CDS (Multisim)The PLD design mode possesses a different list of components; the components from one mode do not work in the other. You can, however, use the simulation feature within PLD Mode to test whether the circuit is working before programming the DLB.

Components are found and placed in PLD Mode the same way they were in Design Mode. The available PLD logic components are generic and therefore do not have part numbers.

12.To place an OR gate: Select: PLD Logic → OR2

13.To place inputs for simulation: Select: Sources → INTERACTIVE_DIGITAL_CONSTANT

14.To place an output for simulation: Select: Indicators → Probe

15.Save the circuit to the Tutorial project folder you created. From the simulation toolbar, select the green arrow Run (F5) and verify the circuit works before exporting.


Part 3: Exporting the Design to the PLD Module

16.Connect your PLD Module (CmodS6) should be via USB to the computer.

17.Having verified your gate is working, Select: Transfer → Export to PLD. As long as there are no errors, the PLD Export dialog box will open.

18.PLD Export – Step 1 of 2Select: Program the connected PLD. The Save box should have a check mark in it.Select: Next


19.PLD Export – Step 2 of 2

Xilinx tool:

Under the Xilinx tool drop-down menu, Select: NI LabVIEW FPGA Xilinx ISE 14.7 (2014) 64-bit or NI LabVIEW FPGA Xilinx ISE 14.7 (2014) 32-bit

Programming file: Select: Browse. Set your location for the programming file.

PLD part number: The PLD part number is auto-populated.

Advanced settings:

Xilinx user constraint files (*.ucf): Under the Advanced settings select the button on the right side “three dot box” of the Xilinx user constraint files row and set path to C:\Program Files\National Instruments\Circuit Design Suite 14.0\pldconfigSelect: “Digilent Cmod S6.ucf” from the pldconfig folder.Select: Open

Allow unmatched LOC constraints: Yes.

Select: Finish.

20. If errors occur, tell your teacher so that steps can be taken to check for proper installation of driver, Multisim, and Xilinx software. If the device is not found:

a. check whether the USB cable is connected.b. check the user constraint path under PLD export Step 2.c. check the Xilinx tools path under Global Settings.d. check your Device Manager to see whether “Digilent USB Device” is found.


Exporting to the PLD will take several minutes.

21.Test the OR gate on the PLD.

Using Both Hardware Platforms (DMS and DLB)If you are using only one hardware option, disregard this optional information below.

If your classroom is using both hardware platforms (Digital MiniSystem and Digital Logic Board), check whether the CDS is pointing to the correct version of Xilinx, the correct drivers, and the correct user constraint file each time you “Transfer → Export to PLD”. If you have trouble transferring the project to the PLD, check the following settings.

Digital MiniSystem (DMS) Option Global Settings

o Options → Global options → Paths → Miscellaneous → Xilinx tools patho C:\NIFPGA\programs\Xilinx14_7\ISE

Transfer → Export to PLS Settingso Xilinx tool: “NI LabVIEW FPGA Xilinx ISE 14.7 (32-bit or 64-bit)”o Xilinx user constraint file: “Digilent Cmod S6.ucf”

Digital Logic Board (DLB) Option Global Settings

o Options → Global options → Paths → Miscellaneous → Xilinx tool patho C:\NIFPGA\programs\Xilinx12_4\ISE

Transfer → “Export to PLS Settings”o Xilinx tool: “Xilinx ISE Design Suite 12.4 (32-bit or 64-bit)”o Xilinx user constraint file: “DEFB.ucf”


Conclusion

1. Look up the names and definitions for the following programmable logic acronyms:

a. PLD:

b. PAL:

c. GAL:

d. CPLD:

e. FPGA:

2. The evolution of programmable logic devices from the simple PALs of the late 1970s to the FPGAs of today is a classic example of Moore’s Law. What is Moore’s Law?


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2.4.2.A Programming Tutorial - Socorro … · Web view2.4.2.A Programming Tutorial Subject Digital Electronics - PLTW Keywords APB Last modified by Sanchez, Gerardo - Teacher Math,