2568 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12

2568 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005

Comparing Carbon Nanotube Transistors—The IdealChoice: A Novel Tunneling Device DesignJoerg Appenzeller, Senior Member, IEEE, Yu-Ming Lin, Member, IEEE, Joachim Knoch,

Zhihong Chen, Member, IEEE, and Phaedon Avouris, Member, IEEE

Abstract—Three different carbon nanotube (CN) field-effecttransistor (CNFET) designs are compared by simulation andexperiment. While a C-CNFET with a doping profile similar toa “conventional” (referred to as C-CNFET in the following) p-orn-MOSFET in principle exhibits superior device characteristicswhen compared with a Schottky barrier CNFET, we find that ag-gressively scaled C-CNFET devices suffer from “charge pile-up”in the channel. This effect which is also known to occur in floatingbody silicon transistors deteriorates the C-CNFET off-state sub-stantially and ultimately limits the achievable on/off-current ratio.In order to overcome this obstacle we explore the possibility ofusing CNs as gate-controlled tunneling devices (T-CNFETs). TheT-CNFET benefits from a steep inverse subthreshold slope anda well controlled off-state while at the same time delivering highperformance on-state characteristics. According to our simula-tion, the T-CNFET is the ideal transistor design for an ultrathinbody three-terminal device like the CNFET.

Index Terms—Carbon nanotube (CN), field-effect transistor(FET), tunneling (T) device.

I. INTRODUCTION

CARBON nanotubes (CN) have been identified as animportant subset of one-dimensional structures with the

highest potential to risk ratio for emerging logic applicationssuch as nano field-effect transistors (nano-FETs) [1]. Whileseveral major technology related questions still need to beaddressed, it becomes increasingly obvious that from a materialprospective and from the standpoint of electrostatics a semi-conducting CN is an excellent choice for a three-terminal FETdesign. In particular the possibility to obtain ballistic transportover several hundred nanometers at room temperature [2]–[4]together with a very large Fermi velocity of around 10 cm/s [5]allows for high-performance on-state characteristics [6]–[9].At the same time, the large energetic spacing between one-di-mensional (1-D) subbands due to quantization along the tubeperimeter results in energy gaps for semiconducting CNsranging from several hundred meV to more than 1 eV de-pending on the tube diameter [5]. The right choice ofcan thus ensure in principle a good transistor off-state as well.The tube diameter also has direct relevance for the electrostaticcontrol in a CNFET. CNFETs are ultrathin body devices [10]

Manuscript received April 27, 2005; revised August 5, 2005. The review ofthis paper was arranged by Editor S. Datta.

J. Appenzeller, Y.-M. Lin, Z. Chen, and P. Avouris are with the IBM T.J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail:[email protected]).

J. Knoch is with the Institute for Thin Film and Interfaces, D-52425 Jülich,Germany.

Digital Object Identifier 10.1109/TED.2005.859654

that do not suffer from severe mobility degradation as typicallyobserved for silicon MOSFETs with nanometer dimensions[11]. This makes nanotubes extremely suitable for aggressivescaling of the channel length well into the nanometer rangewhile preserving long-channel type electrical characteristics[12].

With the intrinsic advantages of CNs established, the mainquestion to address is: What device geometry is ideally suitedto enable optimum device performance? How do we makebest use of the intrinsic potential of CNs as three-terminaldevices? In this paper, we will discuss the major benefits anddisadvantages of various CN-based transistor designs usingexperimental results and simulations we have performed. Wedemonstrate through experiments and simulation that a noveldevice approach—the tunneling-CNFET (T-CNFET) is ideallysuited for nanotube-based transistor applications in terms ofboth, intrinsic switching speed as well as power delay product.

Fig. 1 illustrates the three different device concepts underconsideration schematically. CN (i) denotes an undoped, in-trinsic nanotube or portion of the same while CN (p) and (n)indicate doping of a certain segment of the nanotube. Differentfrom Fig. 1(a), in Fig. 1(b) and (c) and only part of the nan-otube is gated. It is worth mentioning that our arguments applywhether the gate is located underneath or on top of the nan-otube. In fact, tighter gate control can be achieved in all casesby wrapping the gate dielectric (called oxide in the figure) andthe gate (typically a metal of appropriate work function) aroundthe nanotube.

II. ELECTRICAL CHARACTERISTICS OF SB-CNFETS AND

C-CNFETS AND THE DISADVANTAGES OF THE TWO DESIGNS

The two device concepts that have been discussed so farin the literature are the Schottky barrier (SB) CNFET wheremetal source/drain contacts are directly connected to the gatecontrolled nanotube channel and the C-CNFET with a dopingprofile along the nanotube that resembles a “conventional”MOSFET. In fact, sophisticated doping profiles have only veryrecently been introduced into the design of nanotube devices[13]–[15]. There is a twofold reason that SB-CNFETs arestill the most common CN device layout: First, controlleddoping is not an easy task to accomplish since ion implantationtechniques that are employed to create a doping profile inconventional semiconductors cannot be used in the case ofnanotubes. The reason being that removing any carbon atomsthat actually form the tube and replacing them by a dopantwould destroy the desired nanotube properties. Thus, dopingof CNs requires controlling the electrostatics of the nanotube

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APPENZELLER et al.: COMPARING CARBON NANOTUBE TRANSISTORS 2569

Fig. 1. Three device concepts under consideration. (a) Gating occurs over theentire nanotube channel including the contact areas. In (b) and (c) a p/i/p or n/i/pdoping profile exists along the tube. Only the intrinsic portion of the nanotubeis gated.

environment by molecules [13], additional gates [14] or metalions [15] instead. Second, only if SB-CNFETs are aggressivelyvertically scaled by reducing the gate oxide thickness orby introducing high- dielectrics some inherent disadvantagesbecome apparent. Fig. 2 illustrates this second fact for anSB-CNFET with a thin gate dielectric of 10 nm SiO .Since the gate acts on the entire intrinsic nanotube channelup to the metal contacts, on-currents are observed for bothnegative and positive gate voltages. Ambipolar characteristicsare obtained due to hole injection for negative gate voltagesand electron injection for positive with a very distinct drainvoltage dependence [12], [16], [17]. The insets of Fig. 2show the current injection at the source and drain electrodesschematically. One key ingredient is that the width of the SB atthe metal/nanotube interface decreases with decreasing and

[10], [18] such that electrons as well as holes can tunneldirectly from the metal contact into the nanotube channel. Inthis sense, a CN with a 1 nm always exhibits a rathersmall SB width. The other important aspect is that transportinside the nanotube is ballistic and the drain voltage dropscorrespondingly exclusively at the electrodes.

Since switching always involves a change of the SB width,the term SB CNFET has been established to describe this typeof nanotube device [19], [20]. The gate voltage alters the tun-neling probability and thus the current through the device. Thisis true even for zero SB height. While a clear advantage of asmall SB width is the ability to obtain decent on-currents inan SB-CNFET even for moderate barrier heights, it is also theease of current injection that limits the achievable off-currents

as apparent from Fig. 2. The smaller the energy gapof the nanotube used, the higher . In addition, it has been

Fig. 2. Experimental data on a titanium contacted SB-CNFET for threedifferent V of �1.0, �0.7, and �0.4 V.

pointed out that for an SB-CNFET the inverse subthresholdslope is always larger than 60 mV/dec[20]. It is this set of arguments that makes it desirable to explorealternative device concepts.

Recently, it has been proposed to adopt a different scheme fora CN-based transistor. By introducing a p/i/p or n/i/n doping pro-file along the nanotube channel with highly doped areas closeto the contacts and by gating only the undoped portion of thetube, so-called C-CNFETs [see Fig. 1(b)] have been realized[13]–[15]. These structures resemble conventional p- and n-typeMOSFETs with the difference that the gated region is undopedas appropriate for an ultrathin body device. The advantages ofthis approach are as follows: 1) Due to the doping profile car-rier injection of the minority carrier type (e.g., holes in an n-typeC-CNFET) from the drain side is suppressed and unipolar de-vice characteristics with low off-currents can be obtained and2) since switching does not involve the contact area close tothe metal electrodes, is limited by thermal emission as ina conventional MOSFET instead of direct tunneling as in anSB-CNFET and correspondingly S-values of 60 mV/dec areattainable1.

However, a critical aspect is ignored in these arguments. In-deed, under certain conditions, electron (hole) pile-up occurs inthe gated region of the p-type (n-type) C-CNFET [21]. In caseof a p-type C-CNFET electrons are injected from the drain sideinto the gated region and cannot leave the device toward thesource [see inset of Fig. 3(b)]. These charges can prevent thegate from effectively moving the bands to turn the device off.The higher the drain voltage the more pronounced the effect. Aswe show here for the first time, this phenomenon can be particu-larly harmful for transistors that are aggressively scaled in termsof their gate length . In Fig. 3(a) and (b) experimental char-acteristics for two different C-CNFETs are presented. While a

1Note that the slope of the subthreshold swing and the threshold voltage it-self in a CNFET both critically depend on the details of the environment. Sincethe charge state of the underlying substrate has not been perfectly controlledin the presented experiments, S-values substantially larger than 60 mV/dec andthreshold voltage variations of ∼0.5 V from device to device are not untypical.


Fig. 3. Experimental results on two C-CNFETs with different gate length ofL = 200 nm and 40 nm respectively. The equivalent gate oxide thickness(EOT) is 4 nm. In both cases, the same drain voltages of �0.1, �0.3, �0.5,and �0.7 V were used. The legend for b) is the same as for a). The inset in b)illustrates schematically the situation that is referred to as pile-up in the text.Gap energies are believed to be around E = 0.7 eV.

C-CNFET with an 200 nm shows low off-currents andalmost no drain voltage dependence in the subthreshold regionof the transistor, a similarly designed device2 with a gate lengthof only 40 nm on the other hand shows drastically deterioratedoff-state performance. Note that the current and gate voltageaxes are identical for the two plots. In both cases it is ensuredthat long-channel type characteristics are obtained by using a4-nm-thick aluminum oxide gate dielectric layer. Output char-acteristics are monitored to verify that a proper current satura-tion is observed for high enough drain voltages. When de-creases so does the probability for scattering in the island thatis formed underneath the gate. Even for rather long scatteringlengths, as in case of CNs, this results in a different distribu-tion of carriers in the island depending on the size of the gate.

2Details of the sample fabrication can be found elsewhere [14], [23]. The gapenergy of the nanotubes used here is around 0.7 eV. Doping of the p-type regionsclose to source and drain is accomplished by applying a negative voltage to anadditional back gate.

In the case of perfect ballistic transport conditions, carriers thatwere injected from the drain cannot leave the gated region to-ward the source again—the result is a substantial carrier pileupdifferent from what is typically observed in conventional fullydepleted devices [22]. On the other hand a finite scattering prob-ability enhances the escape rate into the source. The smaller thesystem, the more ballistic it behaves and the more drastic thepileup effect.3 The larger the drain voltage the smaller (morenegative) the gate voltage for which the subthreshold character-istics starts deviating from the ideal behavior. The inverse sub-threshold slope in the pile-up dominated gate voltage range be-comes very large and the aggressively scaled C-CNFET behaveslike a “leaky” transistor.

Interestingly, it is the same physics aspect that gives rise toboth, the particular switching behavior in an SB-CNFET andthe pile-up of charge in case of a C-CNFET. In the context ofan SB-CNFET, we have pointed out above that a very abruptband bending occurs. This situation has been described usingthe expression: “small SB width.” It is the same phenomenonwhich allows for the band-to-band tunneling (BTB-tunneling)from the doped nanotube segment into the gated C-CNFET re-gion. Because of the small diameter of a nanotube the gatecan strongly affect the bands inside the tube channel resulting ina high tunneling probability for electrons and holes. In case ofthe SB-CNFET it is the tunneling from the metal contact into thenanotube conduction or valence band. In case of the C-CNFETit is the tunneling through the band gap from the conduction intothe valence band and vice versa.

III. GATE CONTROLLED TUNNELING AND A NOVEL

T-CNFET DEVICE LAYOUT

So far, we have discussed why the particular tunneling be-havior in CNFETs is harmful for aggressively scaled nano-tran-sistors. Now, we want to ask the question, whether it is possibleto make use of this property to our advantage. In this context,we recently explored gate controlled tunneling in a C-CNFET inmore detail [24]. While electrical characteristics show a mono-tonic current decrease for increasing gate voltage within a cer-tain -range [see, e.g., Fig. 3(a)], increasing the gate voltagefurther (making it more positive) results in an abrupt increaseof . This situation is illustrated in Fig. 4. For high enoughpositive gate voltages the conduction band of the gated nan-otube segment is pushed below the Fermi level in the highlyp-doped source and drain regions of the C-CNFET. Charge thatwas able to pile-up in the intrinsic nanotube region can nowleave the device toward the source by a second band-to-band(BTB) tunneling process. This opens another channel for carrier(hole) transport from source to drain and increases abruptlyas apparent for 0 V in Fig. 4. The important finding ofthis experiment is that in addition to the normal operation of

3Note that it is possible that part of the observed pile-up difference betweenthe short and the long nanotube device is related to the use of differentsource/drain metal contacts. Paladium, which has a closer Fermi level line-upto the nanotube valence band than titanium, has been used for the shorterC-CNFET. The supply of holes from the drain is thus somewhat higher for theL =40 nm case adding to the effect of scattering as discussed in the text.


Fig. 4. Subthreshold characteristics of a C-CNFET withL = 200 nm atT =300 K for V = �0.5 V. Two subthreshold regions with different S-values areapparent. The steep inverse slope of S � 40 mV/dec is achieved through BTBtunneling. The inset shows how characteristics of a device with short L wouldlook like for two different drain voltages.

the C-CNFET it is also possible to utilize gate controlled tun-neling for switching and that in this way it is possible to achieveS-values smaller than 60 mV/dec at room-temperature [24].

Since the energy gaps of the p-doped and the gated regionof the CNFET act as energy filters during the BTB-tunnelingprocess, high energetic carriers in the Fermi distribution areless involved in current flow. By eliminating the high energetictail of the Fermi distribution, the electronic system gets effec-tively “cooled down”—the entire system acts like a conventionalMOSFET at a lower temperature. While in principle, by uti-lizing BTB tunneling, S values smaller than 60 mV/dec are alsoachievable in silicon MOSFETs [25], experimentally this situ-ation has not yet been realized [26], [27]. On the other hand,CNs offer the ideal combination of intrinsic properties to makegate controlled tunneling a viable approach for nano-devices.The important aspects are: 1) ballistic transport in the channel:2) ultrasmall and : 3) small effective masses for electronsand holes: 4) same effective masses of electrons and holes, and:5) a direct energy band gap. While 1) ensures a high current levelin the device, 2)–5) all support a high tunneling probability forthe BTB tunneling process. Moreover, aspects 2) and 3) are thedetermining factors for the actual value of S as will be discussedbelow.

In order to make gate controlled tunneling a relevant approachfor device applications, it is not enough that an abrupt transitionbetween the transistor on- and off-state can be achieved. It alsohas to be ensured that high on-currents that translate into a highdevice performance are obtained at the same time. A C-CNFETis not the right choice in this context. With two BTB-tunnelingevents involved in the current transport and the aforementionedproblem of a distinct drain voltage dependence due to chargepile-up in the gated nanotube area, C-CNFET characteristicswould even for ideally scaled conditions exhibit too low currentlevels and undesirable drain voltage effects. Here we proposefor the first time a T-CNFET [see also Fig. 1(c)] that eliminatesall the previously discussed disadvantages of other CNFET lay-

Fig. 5. Conduction and valence band for a T-CNFET according to oursimulation at V = �0.5 V and V = �0.65 V. The device is in the onstate. The inset shows the corresponding output characteristics of the transistor.The parameter set used for the calculation is: E = 0.7 eV, t = 1 nm,t = 1 nm, and m = 0.1 m .

outs and ideally benefits from the concept of gate controlled tun-neling discussed before.

To explain the operation principle of the T-CNFET wewill use Fig. 5 that indicates the band bending situation inthe on-state of the tunneling device. Fig. 5 is the result of aself-consistent calculation as will be discussed below. The xaxis displays the position inside the nanotube and the y axisshows the electron/hole energy relative to the conduction bandin the n-type region. The plot contains the local density of statesinformation as a gray scale with light and dark areas indicatinga high and a low density of states respectively. For negativedrain voltage conditions the p-type T-CNFET can be turnedon by applying negative gate voltages as for a conventionalp-FET. As illustrated in Fig. 5, hole injection from the n-dopedsource region by tunneling into the intrinsic nanotube segmentis enabled by the gate and can be disabled by more positive .The critical BTB tunneling process occurs at an x axis valueof around zero. Since ballistic transport conditions prevail,this hole current can reach the drain electrode unimpeded. Theenergy of the holes remains the same throughout the entirenanotube channel and there is no second tunneling barrierto overcome as in the C-CNFET case. Besides resulting ina higher on-current—if comparing the tunneling currents ina C-CNFET with those in a T-CNFET, this also implies thatno charge pile-up can occur in the gated region due to theabsence of a cavity-like structure as in the case of a C-CNFET.At the same time inverse subthreshold slopes smaller than 60mV/dec at room-temperature are achievable as discussed inthe context of the C-CNFET. Since the drain voltage cannotimpact the tunneling probability between the n- and i-regionin a well tempered i.e., “long-channel” type transistor, sub-threshold characteristics are drain voltage independent asdesirable. Another interesting aspect of this device concept is


Fig. 6. Experimental results (symbols) and simulations (lines) on thedependence of the inverse subthreshold on gate oxide thickness (t = EOT)for the three device concepts under evaluation.

that conventional-looking output characteristic are obtaineddespite the completely different switching mechanism behindthe T-CNFET. Small drain voltage operation is possible as in aregular MOSFET. The inset of Fig. 5 indicates that both a linearand a saturation region exist in the characteristics of aT-CNFET4. The linear behavior for small is a result of thelinear increase of open states in the drain region with the drainvoltage. Saturation occurs, as in any ballistic MOSFET, due tothe exponential decrease of current from the drain to the sourcefor large enough 5. Last, the same T-CNFET can operateas both an n-type or a p-type tunneling device. By reversingsource and drain in Fig. 5 and applying a positive voltage to then-type part of the tube an n-type T-CNFET is obtained.

While there are a number of advantages of the T-CNFET, themost appealing aspect is clearly the extremely small S-valuesthat can be obtained. To illustrate this aspect Fig. 6 shows ex-perimental and simulation results (details will be discussed inSection IV.) of S as a function of the gate oxide thickness forthe various device concepts discussed in this paper. As has beenpointed out before [20] S varies dramatically with gate oxidethickness for the SB-CNFET due to the strong dependence ofthe SB width at the metal/nanotube interface on the gate field.In fact S is proportional to for a planar gated device geom-etry [28]. A more detailed analysis [29] reveals that

(1)

4Note that much higher on-current levels are obtained in our simulation ifcompared with the experimental results obtained for SB-CNFETs and C-CN-FETs shown in Figs. 2–4. This is a result of the fact that experimentally SBscan easily reduce the maximum attainable on-current. Only recently Chen et al.[36] have pointed out how to avoid the formation of substantial SBs by com-bining the right type of tube diameter with certain metal contacts. This workproves that in principle almost reflection free injection from the contact into thenanotube is feasible as is assumed in our simulations. It is also because of thiswork that we did not perform simulations for various nanotube diameters andcorrespondingly different energy gaps. Those tubes that have been identified asideally suited for device applications do not differ substantially in terms of theirband gaps.

5Note that the total current through a ballistic device is the current from sourceto drain minus the one from drain to source. Since the drain voltage does notimpact the current from source to drain in a well tempered device, decreasingthe current component from the drain to the source to zero by increasing V

results in a saturation of the device current.

Since the SBs in the contact area are always in series with what-ever band bending situation exists for a given gate voltage insidethe nanotube channel, S can never be smaller than 60 mV/decfor an SB-CNFET. This is not a result of short channel effectsdue to a diminished gate control. Indeed, for both, the experi-mental results and the simulations presented here it is ensuredthat long channel type transistor characteristics are obtained.Consequently, the C-CNFET exhibits a constant inverse sub-threshold slope of 60 mV/dec in the same plot. The same figurealso contains our findings on the T-CNFET. For a nanotube di-ameter of 1 nm and an effective mass of 0.1 mS-values smaller than 60 mV/dec are predicted for 10 nm(assuming a dielectric constant of 4). The functional de-pendence of is similar to that of the SB-CNFET with themain difference that 0. Note that (1) holds for theT-CNFET as well. We find that the condition 1(with being measured in units of and in nanome-ters) marks the transition to an S-value smaller than achievablein a conventional MOSFET design. The importance of an ultra-thin body and a thin gate oxide layer becomes apparent fromthis expression. In addition, Fig. 6 includes two experimentaldata points for devices operating in the BTB-tunneling regimewith gate oxides of 4 and 10 nm, respectively. The gen-eral agreement with the predicted behavior is apparent and theobserved S-values are clearly well below those obtained for theSB-CNFET.

IV. SELF-CONSISTENT QUANTUM SIMULATION OF

ULTRATHIN-BODY DEVICES

In the last paragraphs we started to compare experimentalresults on CN transistors with simulations we have performedusing the nonequilibrium Green’s function (NEGF) formalism[30]. Our simulations consider a CNFET consisting of a nan-otube in contact with two semi-infinite source/drain metalliccontacts. The charge in and current through the CNFET is calcu-lated self-consistently using the NEGF formalism together witha modified 1-D Poisson equation due to Young [31] that ac-counts for the impact of gate oxide thickness and tube diameteron the electrostatics. A quadratic dispersion relation is assumedin the conduction and valence band; the complex band structurein the semiconductor gap is taken into account by an energy de-pendent effective mass [32]. Transport through the nanotube istreated ballistically. Although our approach simplifies the ac-tual situation e.g., by assuming that the metal contacts behaveas ideal conductors with a quadratic dispersion and free electronmass, excellent quantitative agreement between experiment andsimulation has been recently demonstrated [24]. This impliesthat the critical aspects of a CNFET are properly accounted forin our simulation and that it is justified to use our simulationtools to make predictions about more aggressively scaled nan-otube devices than are available to date. It is also possible inthis way to perform a more direct comparison of the three de-vice concepts discussed in this paper. By utilizing an identicalparameter set in terms of geometry and material specific aspects(e.g., effective mass and tube diameter) it is ensured that it isonly the device design that results in differences in the transistorperformance.


Fig. 7. Simulated performance of a C-CNFET and a T-CNFET for variousdrain voltages. The parameter set used for both calculations is: E = 0.7 eV,t = 1 nm, t = 1 nm, L = 20 nm, m = 0.1 m , and T = 380 K.

V. PREDICTED SPEED AND POWER ADVANTAGES OF T-CNFETS

At this point one may argue that a T-CNFET should alwaysbe inferior to a conventional C-CNFET in terms of its on-stateperformance. Employing tunneling can be expected to reducethe maximum achievable -values. The question is whetherthis can be overcompensated by the steeper inverse subthresholdslope.

To address this issue, we have performed simulations for bothtypes of devices. Fig. 7 shows the resulting subthreshold char-acteristics for moderately scaled CNFETs with gate lengths of

20 nm and an equivalent oxide thickness (EOT) of1 nm.6 As expected higher on-currents can be achieved withthe C-CNFET. However, even for rather low drain voltages thep-type C-CNFET shows a substantially deteriorated off-stateperformance due to electron pile-up in the gated channel region.In fact, at 0.6 V the device behaves like a MOSFETexhibiting severe short-channel effects (SCEs). As mentionedabove, this is a result of two effects, the strong electrostaticcontrol by the gate that allows for injection from the valenceband of the p-doped drain region into the conduction band ofthe gated channel region as illustrated in the inset of Fig. 3(b)and the small assumed here. From our simulation for

0.4 V it is more obvious that the device indeed first shows aconventional switching with an inverse subthreshold slope of

10 between 0.4 V and 0.1 V before pile-upbecomes relevant for 0.1 V.

On the other hand, the p-type T-CNFET characteristics forthe same drain and gate voltage range show a quite differentbehavior. The first thing to notice is a distinct drain voltage de-pendence that resembles the one presented in the context of anSB-CNFET in Fig. 2. While for the left—p-type—branch theaforementioned steep switching behavior due to BTB-tunnelingwith no particular drain voltage dependence is observable as de-sired, we notice that the T-CNFET exhibits a clear n-type branch

6For this parameter set it is ensured that the charging energy e =2 � C issmaller than k T at the temperature considered. This justifies to neglect theCoulomb interaction in our simulation.

Fig. 8. Total capacitance C = (1=C + 1=C ) for the T-CNFET inFig. 7 as a function of gate voltage for various applied drain voltages.

as well. The increase of for large enough positive gate volt-ages is a result of BTB-tunneling on the drain side of the tran-sistor—an undesirable leakage path in this device layout. Thecharacteristics of a T-CNFET are those of an SB-CNFET butwith much steeper inverse subthreshold slope (see Fig. 6) andhigher ratio. Also notice, that the value of S in caseof a T-CNFET does not deteriorate with increasing tempera-ture [33]. While both, the SB-CNFET and the C-CNFET exhibitS-values proportional to temperature in the relevant T-range fortransistor operation between 300 K and 380 K, S is temperatureindependent for a T-CNFET. This means that high temperatureoperation has no negative impact on the device characteristicsof a T-CNFET.

We now want to quantify the performance advantages of aT-CNFET in comparison with a C-CNFET taking into accountall of the above effects. A metric to characterize the switchingspeed in a device is the gate delay for agiven ratio. Here includes contributions from thegeometrical gate capacitance and the quantum capacitance

of the nanotube (see also [34] and [35]). Since CNs are ef-fectively 1-D conductors, the relatively small 1-D-density ofstates allows to experimentally realize -values thatare comparable to which is proportional to . Be-cause of this situation the quantum capacitance cannot be ig-nored in a scaled CNFET.7 What makes the situation compli-cated is that also depends on the coupling betweenthe contacts—the electron (or hole reservoirs)—and the gatedchannel region [29] and in addition on the drain and the gatevoltage.

Fig. 8 illustrates how changes for the T-CNFET consid-ered here as a function of drain and gate voltage. The first aspectto notice is that is indeed not a constant even well above

7At this point, we ignore parasitic capacitance contributions from fringingfields between the source (drain) electrode and the gate that may ultimately limitthe achievable high-frequency performance of the nanotube transistor. We alsodo not consider any channel- or gate-to-substrate capacitance because it is as-sumed that these effects can be suppressed by the choice of a proper substrate.


Fig. 9. Gate delay � for the C-CNFET and the T-CNFET discussed in Fig. 7.Superior device characteristics are obtained for the T-CNFET for any V . Theinset shows the power-delay product for both device layouts.

the threshold voltage (for 0.45 V) as would be thecase in a conventional MOSFET device. In fact, the total capaci-tance increases by a factor of four from its minimum value withdecreasing (more negative) gate voltage and increasing (morepositive) drain voltage. These trends can be qualitatively under-stood as follows: Making more negative increases the trans-mission of holes from the n-doped source region of theT-CNFET into the gated channel region. Since[29] this increases the quantum capacitance and thus the total ca-pacitance 1 1 . On the other hand, making

more negative reduces the amount of charge injected fromthe drain side. As discussed above, this is also the reason for thesaturation of as a function of . Consequently, the quantumcapacitance decreases and accordingly.

For our analysis, we use the value that corresponds tothe applied voltage conditions. That is, for an ratio of1000, at 0.3 V the gate voltage is 0.6 Vas apparent from the marked area in Fig. 7 for the T-CNFET8.Using Fig. 8 we find 0.3 V 0.57 pF/cm. Thedashed line and hollow circles in Fig. 8 denote the trend ofwith . The larger , the smaller the total capacitance of thesystem—which implies that the drain voltage has a stronger im-pact on the total capacitance of the system than the gate voltageunder the conditions considered here.

By performing the type of analysis described above for both,the T-CNFET and the C-CNFET, we are able to evaluate thegate delay as a function of at a fixed ratio of1000.9 Fig. 9 illustrates our findings for a bias ranging from 0.1to 0.8 V. We notice that the T-CNFET shows the expected mono-tonic behavior of as a function of . As in a conventional

8Note that the simulation for V =-0.3 V which is not explicitly shown inFig. 7 coincides with the V =-0.4 V curve for the relevant gate voltage range.Also note, that we have assumed here that the threshold voltage of the T-CNFETcan be adjusted freely to ensure that the gate voltage swing always covers therange from V =0 to V =V —i.e. that the simulated curve for V =-0.3 V canbe shifted by +0.3 V toward positive gate voltages by the use of the appropriategate metal.

9Guo etal. [37] have previously studied � as a function of I /I to point outthe intrinsic advantages of CNFETs when compared with conventional siliconMOSFETs.

MOSFET, the ratio is not a constant and consequentlythe gate delay improves for increasing . However, there is afinite size -window that allows for CNFET operation. Sincewe claimed an ratio of 1000, a drain voltage above 0.65V cannot be used. As discussed in the context of Fig. 7, theoff-current of the T-CNFET is strongly drain voltage depen-dent and deteriorates for increasing . At the low side,the steep inverse subthreshold slope allows for excellent deviceperformance even at a supply voltage of only 0.2 V.

On the other hand, the situation in the C-CNFET is character-ized by a much smaller -window. Due to the above discussedcharge pile-up, the C-CNFET fails to support an on-/off-cur-rent ratio of 1000 for -values above 0.5 V. Below around

0.3 V the inverse subthreshold slope limits the use ofthe C-CNFET for 380 K. Interestingly, the gate delayis always larger for the C-CNFET despite the higher absoluteon-current value shown in Fig. 7. There is a twofold reason forthis behavior: First, the better S-value of a T-CNFET results ina higher on-current for most . This is illustrated in Fig. 7 for

0.3 V by the shaded areas and the dashed lines. Second,the smaller quantum capacitance [29] in the T-CNFET due tothe tunneling process involved in the on-state characteristics re-sults in a reduced total capacitance. Both effects improve thegate delay in the T-CNFET relative to the C-CNFET.

Even for a of 0.4 V where both devices show the samegate delay, the T-CNFET is the superior device concept. Due tothe smaller total capacitance, the power delay product which isplotted in the inset of Fig. 9 always exhibits a smaller value forthe T-CNFET than for the C-CNFET.

VI. SUMMARY

The chain of arguments presented in this paper can be sum-marized as follows. To increase the performance of an FET,short gate lengths and high mobilities are required. Sincenanotubes typically exhibit very small diameters they allow forexcellent gate control while not suffering from mobility degra-dation. This is the key to an aggressive -scaling. However, ul-trathin body devices—as CNFETs—always show an increasedprobability for tunneling processes. Charge pile-up does notallow to employ well established device concepts similar tothose of conventional n- or p-type MOSFETs in this case. In-stead, it is required to transition from a device that operatesbased on the gate control of a thermal emission current to a gatecontrolled tunneling device. We have shown that this transitionis not only necessary but actually also beneficial for the overalldevice performance in terms of switching speed and power con-sumption by introducing the T-CNFET.

ACKNOWLEDGMENT

One of the authors, J. Appenzeller, would like to thank Dr.D. Frank for valuable discussions on the topic of performanceversus power consumption and Dr. P. Solomon for sharing hisinsights into the design of ultimately scaled silicon MOSFETs.

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Joerg Appenzeller (SM’04) received the M.S.and Ph.D. degrees in physics from the TechnicalUniversity of Aachen, Aachen, Germany in 1991 and1995. His Ph.D. dissertation investigated quantumtransport phenomena in low dimensional systemsbased on III/V heterostructures.

He worked for one year as a Research Scientistin the Research Center, Juelich, Germany, before hebecame an Assistant Professor with the TechnicalUniversity of Aachen in 1996. During his profes-sorship he explored mesoscopic electron transport in

different materials including CNs and superconductor/semiconductor-hybridedevices. From 1998 to 1999, he was with the Massachusetts Institute of Tech-nology, Cambridge, as a Visiting Scientist, exploring the ultimate scaling limitsof silicon MOSFET devices. Since 2001, he has been with the IBM T.J. WatsonResearch Center, Yorktown, NY, as a Research Staff Member mainly involvedin the investigation of the potential of CNs for a future nanoelectronics.

Yu-Ming Lin (M’04) received the B.S. degree inphysics from National Taiwan University, Taipei,Taiwan, R.O.C., in 1996, and the M.S. and Ph.D.degrees in electrical engineering and computerscience from Massachusetts Institute of Technology,Cambridge, in 2000 and 2003, respectively. HisPh.D. study focused on experimental and theoreticalstudies of thermoelectric properties of bi-basednanowires fabricated using a nonlithographicself-assembly process.

In July 2003, he joined the IBM T. J. Watson Re-search Center, Yorktown Heights, NY as a Postdoctoral Fellow, where he iscurrently involved in the transport study of CN transistors.


Joachim Knoch received the M.S. and Ph.D. degreesin physics from the Technical University of Aachen,Aachen, Germany in 1998 and 2001, respectively.

At the University of Aachen he investigatedquantum transport in superconductor/semicon-ductor hybrids based on III-V heterostructures aswell as worked on the modeling and realizationof ultrashort-channel silicon MOSFETs. FromSeptember 2001 to December 2002 he was with theMicrosystems Technology Laboratory, Massachu-setts Institute of Technology, Cambridge, where he

worked on InP-HEMT devices. Currently, he is a Research Scientist at theInstitute of Thin Films and Interfaces, Research Center Juelich, Germany. Heis involved in the exploration of electronic transport in alternative field-effecttransistor devices such as CN field-effect transistors, and ultrathin body SBdevices and MOSFETs based upon strained silicon.

Zhihong Chen (M’05) received the Ph.D. degree inphysics from the University of Florida, Gainesville,in 2003. Her doctoral dissertation concerned opticaland electrical properties of single-wall CNs.

In 2004, she joined the IBM T. J. Watson ResearchCenter, Yorktown Heights, NY, as a PostdoctoralFellow. Her current research involves the investi-gation of nanotube based electronic devices andtheir potential to be the building blocks of futurenanoelectronics.

Phaedon Avouris (M’00) received the B.S. degreefrom the Aristotelian University, Thessaloniki,Greece, and the Ph.D. degree in physical chemistryfrom Michigan State University, East Lansing, in1994.

After postdoctoral work at the University of Cal-ifornia, Los Angeles, and AT&T Bell Laboratories,Murray Hill, NJ, he joined the Research Divi-sion, IBM T.J. Watson Research Center, YorktownHeights, NY, in 1978. Over the years, his researchhas involved a wide variety of subjects ranging

from laser studies of fast phenomena, surface physics and chemistry, scanningtunneling microscopy, and atom manipulation. He is Manager of NanometerScale Science and Technology. His current research is focused on experimentaland theoretical studies of the electrical properties and transport mechanismsof CNs, molecules and other nanostructures. The work includes the design,fabrication and study of model CN and molecular electronic devices andcircuits. He has published over 300 scientific papers.He is co-editor of theSpringer-Verlag book series on nanoscience and is currently serving on theAdvisory Editorial Boards of Nano Letters, Nanotechnology, InternationalJournal of Nanoscience, Journal of Nanoengineering and Nanosystems,Journal of Computational and Theoretical Nanoscience, Surface Review andLetters, and the Journal of Electron Spectroscopy.

Dr. Avouris has been elected Fellow of the American Academy of Arts andSciences, the American Physical Society, the Institute of Physics of the U.K.,the IBM Academy of Technology, the American Association for the Advance-ment of Science, American Vacuum Society and the New York Academy ofSciences. He is also member of the ACS and MRS. He received the Irving Lang-muir Prize of the American Physical Society, the Medard W. Welch Award of theAmerican Vacuum Society, the Feynman Prize for Molecular Nanotechnology,the ACSIN Nanoscience Prize, the Raper Award of IEEE, the DistinguishedAlumnus Award from Michigan State University, and a number of IBM Corpo-ration “Outstanding Technical Achievement” awards.

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2568 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12