4-bit EMBEDDED MPU based SEQUENCER

Kaviraj Chopra

MONSOON

Design Goals

Run time, Reconfigurability.

A Generic MCB

Support both Distributed and Centralised Control.

Meet design time requirements.Sequencer design is the `Critical Path’.

MONSOON

Possible Implementations:

Finite State Machine based approach. Optimal design with regards to logic density and timing

requirements. However fundamental design is locked. Limited reconfiurability

of parameters possible. But to reconfigure control firmware has to be modified.

Embedded MPU based approach. Abstracts control from the firmware designer and provides

complete system control to the designer at a higher level(PAN). Reconfigurability in terms of both parameters and control is

feasible at software level rather then firmware level. The design approach is generic and is reusable for sub-ordinate

boards like Clock and Bias Board with very few modifications. Speeds up the so-called “CRTICAL PATH”( Design Plan

Roadmap) and reduces the design time considerably.

MONSOON

Sequencer Architecture

text

SEQUENCER

text

Data [15 : 0]

Address [15: 0]

Address Stack16x12

Loop AddrStack16X12

Loop Count Stack16x12

PatternMemory

1536 x 32

Sequence BusOutput Multiplexer

Address Decoder Data

CtlR

eg[15:0]

ProgramMemory256 X 64

StkP

tr[3:0] Stk

RdD

ata

[11:

0]

StkW

rData

[11:0]

LAS

RdD

ata

[11:

0]

LAS

Ptr[3:0]

LASWr

LCS

RdD

ata

[11:

0]

LCS

WrD

ata[11:0]

LCS

Ptr[3:0]

LCSWr

SD[15:0]

Brd

Clk

[8:2

]

StkWr

Opc

ode[

31:0

]

Cod

ePtr

[7:0

]

Pat

Ptr

[10:

0]

ControlRegister

Sequencer Memory 4096 X 16

Sel

[8:2

]

Mod

e[1:

0]

Dev

_Ad[

4:0]

Instruction Decode & Execution Unit

AddressFiber Interface

Demux

FIBER INTERFACE CONTROL

LdSel

LdClkCfg LdMod LdDA

Sel_CR

Sel_SeqMemSel_SeqBus

SA[15:0]

SeqBus

LAS

WrD

ata[11:0]

MONSOON

4- BIT EMBEDDED MPU

Control Requirements Load Output Registers (Set) Iteration ( for & while) Branching (if-else) Delay (wait)

MONSOON

A. Load Output Instructions: ( 7)

1. LPP: Load Pattern Pointer: 4 Nibble (16 bit)

2. IPP: Increment Pattern Pointer: 1 Nibble (4-bit)

3. DPP: Decrement Pattern Pointer: 1 Nibble (4-bit)

4. LDA: Load Device Address (12-bit)

5. LMR: Load Mode Register 3 Nibble (12-bit)

6. LSR: Load Select Register 3 Nibble (12-bit)

7. LCR: Load Clock Register 3 Nibble (12-bit)

MONSOON

B. Branch and Loop Instructions: (5)

8. CAL: Call Subroutine : 4 Nibble (16 bit)

9. RET: Return 1 Nibble (4-bit)

10. JCB: Jump if Control Bit Set 5 Nibble (20-bit)

11.   LPB: Loop Begin 4 Nibble (16-bit)

12. LPE: Loop End 1 Nibble (4-bit)

MONSOON

C. DELAY INSTRUCTIONS (4)

13. DUS: Delay micro Seconds 3 Nibble (12-bit)

14. DUS: Delay micro Seconds 3 Nibble (12-bit)

15. DSC: Delay System Clock 3 Nibble (12-bit)

16. NOP: No Operation 1 Nibble (4-bit)