4 PDT Soln - Vidyalankar Coaching Classesvidyalankar.org/.../prelim_paper_soln/SemIII/ETRX/4_PDT_Soln.pdf · 1001 01110 Step 2: Add 25 to is complement of 17. 1 1 0 0 1 ... Step 1

1013/SY/Pre_Pap/Elec/PDT_Soln 81

Vidyalankar S.Y. Diploma : Sem. III

[DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques

Prelim Question Paper Solution

(i) (48 BA)16

(48 BA)16 (01001000 1011 1010)2

(ii) Function of following IC's IC74138 1:8 Demux.

IC74139 Dual 1:4 Demux IC74154 1:16 Demux IC74155 Dual 1:4 Demux

(iii) Fanin Fanin is defined as the number of inputs a gate has propagation delay is defined as time delay between the instant of application of an input pulse and the instant of occurrence of the corresponding output pulse.

(iv) Propagation delay (or speed of operation)

The delay times are measured between the 50 % voltage levels of input and output waveforms.

There are two delay times tPHL when output goes from High to Low tPLH when output goes from Low to High Propagation delay is average of above two delay times.

Fanout : This is number of similar gates which can be driven by a gate. High fanout is advantageous because it reduces the need for additional drivers to drive more gates.

1. (a)

1. (a)

1. (a)

1. (a)

4

0100 1000 1011 1010

8 B A

Input

Output

50 %

50 %

tPHL tPLH

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(v) Minterm : A minterm is a special case product (AND) term. A minterm is a product term

that contains all of the input variables (each literal no more than once) make up a Boolean expression.

Maxterm : A maxterm is a special case sum (OR) term. A maxterm is a sum term that

contains all of the input variables (each literal no more than once) that makes a Boolean expression.

(vi) Circuit diagram of D flip-flop using logic gate (vii) The BCD addition discussed so far can be summarized as follows:

(viii) Difference between EPROM and EEPROM

Parameter EPROM EEPROM 1) Technique used for

erasing Exposure to ultraviolet light

A voltage of 20 to 25 volts is applied

2) Selective erasing Not possible. All the locations get erased.

Possible. A particular location only can be erased.

3) Time required for erasing.

Long 10 to 15 min. Short 10 ms.

4) Need to remove PROM from circuit

It is necessary to remove the PROM

Not necessary to remove PROM.

5) Cost Less expensive Very expensive.

1. (a)

1. (a)

1. (a)

1. (a)

i/ps fanout = 3

Q

Q

S

R

D

Clk

Add two BCD Numbers A and B

Answer is correct. No correction

required.

Sum 9, carry = 0 Sum 9, carry = 1 Sum > 9, carry = 0

Add 6 to the sum to get correct answer

Add 6 to the sum to get the correct

answer

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(i) D-Flip Flop from a R-S Flip Flop

(ii) Consider B2, B1, B0 are binary inputs. D0 D7 are Decimal outputs.

Functional Table :

B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0

1. (b)

1. (b)

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(iii) (1) (247)10 + (463)10 (2) (42)10 – (27)10 Race around condition of SR flipflop

In S.R flipflop, the input condition R=S=1 is not allowed as it leads to a state Q = Q 1 and Q = Q which violates the fact that both Q & Q is complements of eachother.

2. (a)

B1 B0 B2

D0

D1

D2

D3

D4

D5

D6

D7

1. (b) 0010 0100 0111

+ 0100 0110 0011 1010 110 0000 0100 0110 1011 + 110 0001 0010 0100 0111

0

1

1

9’s complement of 27 99 27

72 + 1 73

0100 0010

+ 0111 0011 1011 0101

+ 110 0001

= 15

5

1 Vidyala

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This situation is known as Racearound condition. The Best method to avoid the possibility of Racearound condition is to

isolate the outputs and inputs of flipflop. Racearound condition can be avoided by providing the clock pulse lasts for

a time inte less than the propagation delay. ABC + ABD + ABC + CD + BD

= ABC + ABC + CD + B (D + AD) ( A + A B = A + B)

= ABC + ABC + CD + B (D + A)

= ABC + ABC + CD + BD + BA

= AB (C + 1) + ABC + CD + BD ( 1 + A = 1)

= AB + ABC + CD + BD

= B (A + A C ) + CD + BD ( A + AB = A + B)

= B (A + C ) + CD + BD

= AB + B C + CD + BD

Now consider CD + B is of form AB + AC also we have identify

AB + A C + BC = AB + AC . Thus in above equation A = D, B = C and C = B. Thus value CD + BD remains unchanged if BC is added to it. i.e. CD + BD + BC = CD + BD = AB + B C + CD + BD + BC

= AB + B (C + C ) + CD + BD ( A + A = 1)

= AB + B + CD + BD = B (1 + A) + CD + BD ( 1 + A = 1) = B + CD + BD = B (1 + D ) + CD ( 1 + A = 1) = B + CD ABC + ABD + ABC + CD + BD = B + CD

Half Subtractor using logic gates

For difference output For the borrow output

For D output For B output Difference D = A B + AB Borrow Bo = AB D = A B

2. (b)

2. (c)

Half Subtractor

A B

D B0 Vidy

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Truth table for Half subtractor

Inputs Outputs A B Difference D

(A B) Borrow B0

0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0

Logic diagram

Working :

If Clk = 0 then the flip-flop is disabled. Hence there is no change in output

If Clk = 1 and D = 0 then S= 0 and R = 1. Hence irrespective of the present state the next state is Qn+1= 0 and n 1Q = 1. This is the reset condition.

If Clk = 1 and D = 1 then S= 1 and R = 0. Hence irrespective of the present state the next state is Qn+1= 1 and Qn+1 = 0. This is the set condition.

2. (d)

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Subtract using is 1's & 2’s complement (i) 2517 using 1's complement (25)10 = (11001)2 (17)10 = (10001)2

Step 1: Take is complement of 17. 1001 01110

Step 2: Add 25 to is complement of 17. 1 1 0 0 1 + 0 1 1 1 0 final cy 0 0 1 1 1 As the final cary is ‘I’ add to the final cary and it indicates the result is

positive.

Step 3: 1 1 1 0 0 1 1 1 + 1 cy 1 0 0 0 2517 = 8 (11001)2 (10001)2 = (1000)

2517 using 2’s complement. (25)10 = (11001)2 & (17)10 = (10001)2

Step 1: Take 2’s complement of 17. 10001 01111

Step 2: Add 25 with 2’s complement of 17. 1 1 1 1 + 1 1 0 0 1 1 0 1 0 0 0 (8)10

As the final carry is one. It indicates the result is positive & in its true form.

10 10 10(25) (17) (8)

(ii) 17 25 using 1's complement. Step 1: Take is complement of 25

(25)10 = (11001)2 1's

Complment 00110.

Step 2: Add 17 to the 1’s complement of 25 1 0 0 0 1 + 0 0 1 1 0 1 0 1 1 1 As final carry is zero it indicates that result is negative & in its one’s

complement form.

2. (e)

2 25 R 2 12 1 2 6 0 2 3 0 2 1 1 0 1

2 17 R

2 8 1 2 4 0

2 2 0 2 1 0

0 1

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Step 3: Take 1’s complement of result.

10111 1'sComplement

(01000)2 = (8)10

(17)10 (25)10 = (8)10 17 25 using 2’s complement. Step 1 : Take 2’s complement of 25

(25)0 = (11001)2 2's

Complment (00111)2

Step 2 : Add 17 to 2’s complement of 25 1 1 1 1 0 0 0 1 + 0 0 1 1 1 1 1 0 0 0 As the final carry is zero it indicates the result is negative and in its

2’s complement form. Step 3 : 2’s complement of result. (11000)2 (01000)2 (17)10 (25)10 = (8)10 F (A, B, C, D) = m (0, 1, 2, 3, 4, 5, 7, 8, 9, 11, 14)

f ( A, B, C, D) = ABCD AC AD AB BC BD Difference between Combinational Circuits and Sequential Circuits

Combinational Circuits Sequential Circuits

1) In combinational circuits the output depends only on the present set of inputs at any instant of time.

In sequential circuits the output depends not only on the present set of inputs but also the previous output.

2) No concepts of memory are used. To store the previous output memory is used.

3) Outputs are lost when input signals are removed.

Output signals are retained till the next levels of inputs are applied.

4) e.g., MUX DEMUX, ENCODER, DECODER.

e.g., FLIP FLOPS, COUNTERS SHIFT RESISTERS.

2. (f)

3. (a)

AB CD 00 01 11 10 00 0

1

4

1 12

8

1

01 1

1

5

1 13

9

1

11 3

1 7

1 15

11

1

10 2

1 6

14

1 10

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5) Clock is not used in combinational Logic Circuits

Clock is the main feature of sequential Circuits.

6)

INPUTS OUTPUTS

INPUT

The memory element referred to in the sequential circuit is the flip-flop or latch, which are capable of storing binary information. The latch is the basic element of any sequential circuit. 3 bit Twisted ring counter

Table represents the mode of operation for 3bit Johnson counter

Clear CLK Q2 Q1 Q0

initially 0 0 0 1 ↑ 0 0 1 1 ↑ 0 1 1 1 ↑ 1 1 1 1 ↑ 1 1 0 1 ↑ 1 0 0 1 ↑ 0 0 0

Waveform

3. (b)

Combinational Logic

Memory

Combinational Logic Circuit

D0 Q0

FF0

D1 Q1

FF1

D2 Q2

FF2

CLR

CLR

Q2

1 5 2 3 4 6

Q0

Q1

Q2

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Difference between Synchronous and Asynchronous Counters Asynchronous Counter Synchronous Counter

1) In an Asynchronous Counter the output of one Flip Flop acts as the clock Input of the next Flip Flop.

In a Synchronous Counter all the Flip Flop’s are connected to a common clock signal.

2) Speed is High. Speed is Low. 3) Only JK or T Flip Flop can be used

to construct Asynchronous Counter. Synchronous Counter can be designed using JK, RS, T and D Flip Flop.

4) Problem of Glitch arises. Problem of Lockout. 5) Only serial count either up or down

is possible. Random and serial counting is possible.

6) Settling time is more. Settling time is less. 7) Also called as serial counter. Also called as Parallel Counter. 8)

Comparison between CMOS and TTL families Parameter CMOS TTL

1) Device used n-channel MOSFET and p-channel MOSFET

Bipolar junction transistor

2) VIH(min) 3.5 V(VDD = 5V) 2V 3) VIL(max) 1.5V 0.8V 4) VOH(min) 4.95V 2.7V 5) VOL(max) 0.05V 0.4V 6) High level noise margin VNH = 1.45V 0.4V 7) Low level noise margin VNL = 1.45V 0.4V 8) Noise immunity Better than TTL Less than CMOS 9) Propagation delay 105ns (Metal gate CMOS) 10ns. (Standard

TTL) 10) Switching speed Less than TTL Faster than CMOS 11) Power dissipation per

gate PD = 0.1 Mw. Hence used for battery backup applications.

10 mW

12) Speed power product 10.5pJ 100 pJ 13) Dependence of PD on

frequency PD increases with increase in frequency.

PD does not depend on frequency.

14) Fan out Typically 50. 10 15) Unconnected inputs Unused inputs should be

returned to GND or VDD. They should never be left floating.

Inputs can remain floating. The floating inputs are treated as logic 1s.

16) Component density More than TTL since MOSFETs need smaller space while fabricating an IC.

Less than CMOS since BJT needs more space.

3. (c)

3. (d)

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Parameter CMOS TTL 17) Operating areas MOSFETs are operated as

switches. i.e. in the ohmic region or cut off region.

Transistors are operated in saturation or cut off regions.

18) Power supply voltage Flexible from 3V to 15V. Fixed equal to 5V. 1:64 demultiplexer tree using only 1:16 demux

Master Slave JK Flip Flop, using NAND gates

3. (e)

3. (f)

A B C D

1 : 16

demux

A B C D

A B C D

1 : 16

demux

A B C D

A B C D

1 : 16

demux

A B C D 1 : 16

demux

0

1

15

16 17

31

32

33

47

48

49

63

1 : 4

demux

I/P

Logic O

Enable

Enable

Enable

Enable

input

Enable

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Master is positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond to the negative level. Hence when the clock = I (positive level) the master is active and the slave is inactive, whereas when clock = 0 (low level) the slave is active and the master is inactive.

Clock = , J = 1, K = 1. Clock = 1 : Master active, slave inactive. Therefore, outputs of master will toggle. So S and R also will be inverted. Clock = 0 : Master inactive, slave active. Therefore, outputs of the slave will toggle. These changed output are returned back to the master inputs. But since clock = 0, the master is still inactive. So it does not respond to

these changed outputs. This avoids the multiple toggling which leads to the race around condition.

Thus the master slave flip flop will avoid the race around condition. Circuit diagram

A B Y = AB 0 0 1

0 1 1

1 0 1

1 1 0 Operation : Case 1: A = 0, B = 0 For this case Q1 works in normal mode and transistors Q2 and Q3 both will be OFF and voltage at Vx point will be VCC and this is sufficient to turn ON Q4 and D1 (because to turn ON Q4 and D1 voltage Vx = VB4 = VBE4 + VD1 = 0.7 + 0.7 = 1.4 V) so Q4 and D1 both will be ON when output V0.

4. (a)

A

BY = AB

Multi emitter i/p stage Phase Splitter

Totem pole o/p stage

AB

RB1

VB1

VB2

VBC1

VBE2

VBE3

VBE4Q1 Q2

Q3

Q4

D1

RE2

RC2 RC3

IC3

Vx

o/p

VD

VCC

VB4

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V0 = Vx VBE4 VD1 = VCC VBE4 VD1 = 5 0.7 0.7 = 3.6 V = logic 1 V0 = logic 1

Case 2: A = 0, B = 1

Case 3: A = 1, B = 0

Case 4: A = 1, B = 1 For this case, transistor Q1 works in inverse mode due to this Q2 and Q3 both will be ON and voltage at Vx = VCE2 + VCE2 (sat) + VBE3 = 0.2 + 0.7 = 0.9 V This voltage is not sufficient to turn ON Q4 and D1 because it is less than 1.4 V. So Q4 and D1 both will be OFF and output V0 = VCE3 (sat) = 0.2 V = logic 0. Transfer Characteristics of TTL NAND gate : Transfer characteristics gives relationship between input given and output appeared. It shows valid region for operating TTL gate. (i) VI < Va : If VI at one or more of the input is less than Va, then Q1 works in

normal mode and transistor Q2 and Q3 both will be turn off and voltage at Vx = VCC due to this transistor Q4 and diode D1 is conduct and output V0 will be

Vo = VCC VBE4 (ON) VD1 = 5 0.7 0.7 Vo = 3.6 V = logic 1

(ii) VI > VC : When VI of all inputs is greater than VC, transistor Q2 and Q3 conduct because Q1 works in inverse mode and voltage at Vx = 0.9 V. This is not sufficient to turn on Q4 and D1, so both will be off and output Vo = VCE3 (sat)

= 0.2 V = logic 0

(iii) Va < VI < VC : This range is the transition range where translation occurs from a logic 1 to logic 0 output.

same as case (I)

V0

VIN

a

b

c

Va 0.7 V

VIL

VbVc

1.4 VVIH

0 V

logic 1 VOH = 3.6 V

logic 0 VOL 0.2 V

slope = 1.4

slope = 6.2

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Assume that all inputs are tied together and VI is increased from 0, then Q1 base current is gradually diverted from the emitter of Q1 to the collector of Q1 due to this Q2 will be conduct. This conduction occurs at VI 0.7 V. i.e. point a on characteristics Q2 is now operating in active region with a gain. From input to collector determined by the ratio RE2 / RC2. Since Q4 remains ON, the output follows the gain characteristics of Q2 and therefore decreases at a slope of 1.6 [point a to b on transfer characteristics]. At point b, the input is high enough to cause Q3 to conduct this conduction effectively reduces the emitter impedance of Q2 and hence increases the gain. So will get steep slope region between points b and c. Q4 turns OFF at point c and output is at logic 0 state.

Parameters :

i) Propagation delay = HL LHP Pt t

2

= 10 nsec.

ii) Power dissipation = 10 mW iii) Fanout :

This is the number of similar gates which can be driven by a gate.

Fanout = min OH OL

1H 1L

I I,

I I

= 400 16

min ,40 1.6

= min (10, 10) = 10

iv) Noise Margin High state noise margin

NMH = V0H V1H = 2.4 2.0 = 0.4 V

Low state noise margin NML = V1L V0L = 0.8 0.4 = 0.4 V (i) (52)10 (65)10 (52)10 = (110100)2 (65)10 = (1000001)2 Using 1’s complement 0 1 1 0 1 0 0 + 0 1 1 1 1 1 0

1 1 1 0 0 1 0 Take 1’s complement (0 0 0 1 1 0 1)2 13

4. (b) 2 65 1 2 32 0 2 16 0 2 8 0 2 4 0 2 2 0 1

2 52 0 2 26 0 2 13 1 2 6 0 2 3 1 1

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Using 2’s complement 0 1 1 0 1 0 0 + 0 1 1 1 1 1 1 1 1 1 0 0 1 1

Two’s complement of answer (0 0 0 1 1 0 1)2 13

(ii) (101011)2 (11010)2

I : 8 Demux using 1:2 demux

Truth table for 1:8 Demux

Select inputs Selected Demux Output

S2 S1 S0 0 0 0

Demux1 Y0 = Dm

0 0 1 Y1 = Din 0 1 0

Demux2 Y2 = Din

0 1 1 Y3 = Din 1 0 0

Demux3 Y4 = Din

1 0 1 Y5 = Din

1 1 0 Demux4

Y6 = Din

1 1 1 Y7 = Din

4. (c)

Using 1’s complement Using 2’s complement 1 0 1 0 1 1 1 0 1 0 1 1 + 1 0 0 1 0 1 + 1 0 0 1 1 0 1 0 1 0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 1

Ans. : (0 1 0 0 0 1)2

Carry

Discard

1 : 2 Demux

(1)

Y0

Y1

1 : 2 Demux

(2)

Y2

Y3

1 : 2 Demux

(3)

Y4

Y5

1 : 2 Demux

(4)

Y6

Y7

1 : 4 Demux

(1)

S2 S1

S0

Data input Din

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Minimize using Kmap (i) F = m (0, 3, 5, 6, 9, 10, 12, 15) = A B C D A B C D A B C D A B C D

A B C D A B C D A B C D A B CD

= A B ( C D C D) A B (CD C D) + AB ( CD CD) A B CD +C D)

rearranging the term = A B ( C D) AB ( C D)

= A B (C D) + (C D)

= C D C D A B A B

take C D X & A B Y

= C D A C D B

= X Y XY

= X Y putting value of X & Y = C D A B

rearranging the term Y = A B C D (ii) F = m ( 0, 1, 2, 3, 11, 12, 14, 15)

4. (d)

00 1 1 1 1

01

11 1 1 1

10 1

CD AB

00 01 11 10

group 1 : Quad AB

group 3 : ABD

group 2 : Quad ACD

00 1 0 1 0

01 0 1 0 1

11 1 0 1 0 10 0 1 0 1

CD AB

00 01 11 10

m0 m1 m2 m3

m4 m5 m7 m6

m12 m13 m15 m14

m8 m9 m11 m10

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Truth Table

Block diagram of 7490 as Decade Counter

Operation of IC7490 Decade Counter

Output of MOD5 counter

Output of Mod2 counter

CLK

Count

QD QC QB QA 0 0 0 0 0 0 0 0 0 1 I (↓ ) 1 0 0 1 0 2 (↓ ) 2 0 0 1 1 3 (↓ ) 3 0 1 0 0 4 (↓ ) 4 0 1 0 1 5 (↓ ) 5 0 1 1 0 6 (↓ ) 6 0 1 1 1 7 (↓ ) 7 1 0 0 0 8 (↓ ) 8 1 0 0 1 9 (↓ ) 9

4. (e)

4. (f)

MUX Selection inputs MUX

output Input of

Dff

Output of Dff

A B QA AQ

0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 1 0

Reset State

Set State

2 (MOD−2)

5 (MOD−5)

(14)

(12) (1) (9) (8) (11) (10) (7)

(6)

(3)

(2) R0 (1)

R0 (2)

R0 (3)

R0 (4)

(5)

VCC

QA QB QC QD

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(i) It is 3bit ring counter.

(ii) CLR CLK Q0 Q1 Q2

X 1 0 0 1 ↓ 0 1 0 1 ↓ 0 0 1 1 ↓ 1 0 0

(i) Output of AND gate = A.B

Output of NOT gate = A.B

Output of OR gate = (A.B) B

Y = A.B B (ii) The fastest logic family will be the one with the lowest propagation delay. For TTL propagation delay = 10 ns For CMOS propagation delay = 105 ns For ECL propagation delay = 1 ns Thus ECL is the fastest logic family.

5. (b)

5. (c)

5. (a)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1:16 Demux 5 V

f

A B C D

A

B Y = (A B) B

A B A B

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(i) 9 1001 + 4 0100 13 1101 0110 0011

1 (ii) (16)10 (8)10

16 16 8 + 92 +8 108

Neglecting the carry we get, (08)10. (i) Differences between Multiplexer and Demultiplexer

Multiplexer Demultiplexer 1) It has several inputs in only one

output. It has 1 input and several outputs.

2) In combinational logic design using multiplexers, additional gates are not required.

In combinational logic design using demultiplexer gates are required.

3) They are costly when used for designing multiple output expressions of the same input variables because

They are economical when multiple output expressions of the same input variables are required.

(ii) CMOS invertor :

5. (d)

5. (e)

(10’scomplement of 8)

+VCC

S2

T2 (p-channel)

D2

D1

ID

VO D G Vi

S1

T1 (n-channel) Vidyala

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Half Adder Half adder is a combinational logic circuit with two inputs and two outputs. It

is the basic buildings block for addition of two “single” bit numbers. This circuit has two outputs namely “carry” and “sum”. The block diagram of half adder is as shown in figure 1(a).

The half adder circuit is designed to add two single bit binary numbers A and B. Hence the truth table of a half adder is shown in figure 1(b)

Karnaugh maps and simplified expressions for outputs: Kmap for carry and sum outputs are as shown in figures 2(a) and (b)

(a) K-map for sum output (b) K-map for carry output

Fig. 2 Boolean expressions for the sum (S) and carry (C) output are obtained from

the kmaps as follows:

S AB AB A B

C AB

… (1)

Comparison TTL, CMOS and ECL logic families

Parameter TTL CMOS ECL 1) Propagation delay 10 ns 70 ns 500 ps 2) Noise margin 0.4V 0.45 VDD 150 mV 3) Power dissipation 10 mW 0.01 mW 5 mW 4) Fan out 10 50 25 5) Figure of merit 100 pJ 0.7 pJ 0.5 pJ

Fig. 3 : Half adder circuit

Inputs Outputs A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

(b) Truth table (a) Block diagram

Fig. 1

5. (f)

6. (a) Vidyala

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Fig. : A 5bit shift register (7496)

Features, merits and demerits of ECL family Transistors operate in either cut off or regions. They are not allowed to

operate in saturation. They can switch at very fast speeds. In fact ECL is the fastest logic family. Typically the propagation delay is 1 ns per gate. The logic voltage levels are adjusted to be very close to each other so as to

avoid the transistor saturation. Noise margin is low because the logic levels are close to each other. So ECL

gates are susceptible to noise. Transistor in active region consume more power. So ECL gates consume

more power. 5-bit Shift Register

A 5-bit shift register using five master-slave S-R (or J-K) flip-flops is shown in figure. This circuit can be used in any of the four modes.

The operation of this circuit is explained by assuming the 5-bit data 10110. For any other 5-bit data, the operation will be similar to the one explained. Serial Input The data word in the serial form is applied at the serial input after clearing the

flip-flops using the clear line. The preset enable is to be held at 0 so that Pr for every flip-flop is 1. The input and output waveforms are illustrated in above figure (a).

The process of entering the digital word starts with the data input corresponding to the least significant bit (0) at the serial input and first clock pulse.

At the falling edge (T1) of the first clock pulse the output of FF4 (Q4) will be 0 and the outputs of all other flip-flops are 0 since their inputs are 0.

Next, the input corresponding to next bit is applied and, at the falling edge (T2) of the second clock pulse, the flip-flop outputs will be

Q4 = 1 Q3 = Q2 = Q1 = Q0 = 0 Similarly, the input corresponding to each bit is applied till the MSB and the bits

go on shifting from left to right at the falling edge of each clock pulse as illustrated in figure (a). At the end of fifth clock pulse, the outputs of flip-flops are

6. (b)

6. (c)

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Q4 = 1 Q3 = 0 Q2 = 1 Q1 = 1 Q0 = 0 which is the same as the number to be stored. The number of clock pulses required for entering the data, is the same as the

number of bits. The process of entering the data is also referred to as writing into the register.

The data stored can be retrieved (also referred to as reading) in two ways : serial-out and parallel-out. The data in the serial form is obtained at Q0 when clock pulses are applied.

The number of clock pulses required will be same as the number of bits (five in this case).

In the parallel form, the data is available at Q4 Q3 Q2 Q1 Q0 and clock is not required for reading. In the case of serial output, after the nth clock pulse, for an n-bit word, each flip-flop output is 0. This means that once the data is retrieved the register is empty.

On the other hand, in the case of parallel output, the contents of the register can be read any number of times until new data is stored in the register.

The clock rate may be different for the input data and the output data in case of the serial-in, serial-out shift register. Hence, this method can be used for changing the spacing in time of a binary code which is referred to as buffering.

Fig.(a) : Waveforms of shift register for serial input.

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Method of operation of a Single Slope ADC

i) Manual RESET, will reset ramp generator as well as counter. ii) The analog voltage VA has to be positive. Hence the RAMP begins at 0V. iii) Since VAX < VA , the output of the comparator Vc = 1 (HIGH). iv) This will enable CLOCK gate allowing the CLK input, to be applied to the

counter. v) The ramp generator may make use of counter type ADC or simple integrator. vi) As counter receives clock pulses, it will count up; and the RAMP continues

upward. RAMP voltage rises till it reaches to VA input voltage. vii) When the ramp voltage reaches the input analog voltage, the output Vc = 0

(LOW) and it will disable CLOCK gate and counter cease to advance. viii) The negative transition of Vc simultaneously generates a strobe signal in the

CONTROL box that shifts the contents of the three decade counters into the three 4 FF latch circuit.

ix) After the generation of STROBE signal, a reset pulse is generated by the CONTROL box that resets the RAMP and clears the decade counter to 0’s (ZEROS) and another conversion cycle begins.

x) During this time the contents of the previous conversion, are contained in the latches and are displayed on the seven segment display.

EX-NOR Gate

Symbol Truth Table

Boolean Equations Y A B

6. (d)

6. (e)

=

Output is 1 when even number of inputs are

high or when all the inputs

are low.

Input Output A B Y 0 0 1 0 1 0 1 0 0 1 1 1

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Two Input TTLNAND Gate A two input TTLNAND gate is shown in figure 1. A and B are the two inputs

while Y is the output terminal of this NAND gate.

Operation In order to understand the operation of this circuit, let us replace transistor Q1

by its equivalent circuit as shown in figure 1. A and B are the input terminals. The input voltages A and B can be either

LOW (zero volts ideally) or HIGH (+ VCC ideally). A and B both LOW If A and B both are connected to ground, then both the BE junctions of

transistor Q1 are forward biased. Hence diodes D1 and D2 in figure 2 will conduct to force the voltage at point

C in figure 2 to 0.7 V. This voltage is insufficient to forward bias baseemitter junction of Q2. Hence

Q2 will remain OFF. Therefore its collector voltage VX rises to VCC.

Fig. 2 : Transistor Q1 is replaced by its equivalent.

6. (f)

Fig. 1 : Two input TTL NAND gate.

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AS transistor Q3 is operating in the emitter follower mode, output Y will be pulled up to high voltage.

Y = 1 (HIGH) … For A = B = 0 (LOW) The equivalent circuit for this input condition is shown in figure 3(a).

(a) Equivalent circuit for A = B = 0 (b) Equivalent circuit for A = 1, B = 0.

(c) equivalent circuit for A = B = 1.

Fig. 3 Either A or B LOW If any one input (A or B) is connected to ground with the other terminal left

open or connected to + VCC then the corresponding diode (D1 or D2 ) will conduct.

This will pull down the voltage at “C” to 0.7 V.

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This voltage is insufficient to turn ON Q2. So it remains OFF. So collector voltage VX of Q2 will equal to VCC. This voltage acts as base

voltage for Q3. As Q3 acts as an emitter follower, output Y will be pulled to VCC.

Y 1

if A = andB

if A =1andB

The equivalent circuit for this mode is shown in figure 3(b) A and B both HIGH If A and B are connected to + VCC, then both the diodes D1 and D2 will be

reverse biased and do not conduct. Therefore diode D3 is forward biased and base current is supplied to

transistor Q2 via R1 and D3. As Q2 conducts, the voltage at X will drop down and Q3 will be OFF, whereas

voltage at Z (across R3) will increase to turn ON Q4. As Q4 goes into saturation, the output voltage Y will be pulled down to a low

voltage. The equivalent circuit for this mode of operation is shown in figure 3(c) This discussion reveals that the circuit operates as a NAND gate.

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4 PDT Soln - Vidyalankar Coaching Classesvidyalankar.org/.../prelim_paper_soln/SemIII/ETRX/4_PDT_Soln.pdf · 1001 01110 Step 2: Add 25 to is complement of 17. 1 1 0 0 1 ... Step 1