40 V, 12 mΩ typ., STripFET™ F6 Power D(2, TAB) · July 2015 DocID027807 Rev 2 1/16 ... Automotive-grade P-channel -40 V, 12 mΩ typ., -50 A STripFET™ F6 Power MOSFET in a DPAK

July 2015 DocID027807 Rev 2 1/16

This is information on a product in full production. www.st.com

STD45P4LLF6AG

Automotive-grade P-channel -40 V, 12 mΩ typ., -50 A STripFET™ F6 Power MOSFET in a DPAK package

Datasheet - production data

Figure 1: Internal schematic diagram

Features

Order code VDS RDS(on) max. ID

STD45P4LLF6AG -40 V 15 mΩ -50 A

Designed for automotive applications and AEC-Q101 qualified

Very low on-resistance

Very low gate charge

High avalanche ruggedness

Low gate drive power loss

Applications Switching applications

Description This device is a P-channel Power MOSFET developed using the STripFET™ F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages.

Table 1: Device summary

Order code Marking Package Packing

STD45P4LLF6AG 45P4LLF6 DPAK Tape and reel

AM11258v1

D(2, TAB)

S(3)

G(1)

Contents STD45P4LLF6AG

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Contents

1 Electrical ratings ............................................................................. 3

2 Electrical characteristics ................................................................ 4

2.1 Electrical characteristics (curves) ...................................................... 6

3 Test circuits ..................................................................................... 8

4 Package information ....................................................................... 9

4.1 DPAK (TO-252) type A2 package information................................. 10

4.2 DPAK (TO-252) packing information ............................................... 13

5 Revision history ............................................................................ 15

STD45P4LLF6AG Electrical ratings

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1 Electrical ratings Table 2: Absolute maximum ratings

Symbol Parameter Value Unit

VDS Drain-source voltage -40 V

VGS Gate-source voltage ±18 V V

ID Drain current (continuous) at Tcase = 25 °C -50

A Drain current (continuous) at Tcase = 100 °C -31

IDM(1) Drain current (pulsed) -200 A

PTOT Total dissipation at Tcase = 25 °C 58 W

EAS(2) Single pulse avalanche energy 160 mJ

Tstg Storage temperature –55 to 150 °C

Tj(3) Operating junction temperature

Notes:

(1) Pulse width is limited by safe operating area. (2) starting Tj = 25 °C, RG = 47 Ω, ID(min) = -25 A. (3) HTRB performed at Tj = 175 °C, VDS = 100% V(BR)DSS.

Table 3: Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case 2.14 °C/W

Rthj-amb Thermal resistance junction-ambient 50

Electrical characteristics STD45P4LLF6AG

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2 Electrical characteristics

(Tcase = 25 °C unless otherwise specified)

Table 4: Static

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSS Drain-source breakdown

voltage VGS = 0 V, ID = -250 µA -40

V

IDSS Zero gate voltage drain

current

VGS = 0 V, VDS = -40 V

-1

µA VGS = 0 V, VDS = -40 V,

Tcase = 125 °C -10

IGSS Gate-body leakage current VDS = 0 V, VGS = -18 V

-100 nA

VGS(th) Gate threshold voltage VDS = VGS, ID = -250 µA -1

-2.5 V

RDS(on) Static drain-source on-

resistance

VGS = -10 V, ID = -25 A

12 15 mΩ

VGS = -4.5 V, ID = -25 A

17 20

Table 5: Dynamic


Ciss Input capacitance

VDS = -25 V, f = 1 MHz,

VGS = 0 V

- 3525 -

pF Coss Output capacitance - 345 -

Crss Reverse transfer

capacitance - 240 -

Qg Total gate charge VDD = -20 V, ID = -50 A,

VGS = -10 V (see Figure 14:

"Gate charge test circuit")

- 65.5 -

nC Qgs Gate-source charge - 11.5 -

Qgd Gate-drain charge - 13 -

Table 6: Switching times


td(on) Turn-on delay time VDD = -20 V, ID = -25 A

RG = 4.7 Ω, VGS = -10 V (see

Figure 13: "Switching times test

circuit for resistive load" )

- 12 -

ns tr Rise time - 35.5 -

td(off) Turn-off delay time - 63.5 -

tf Fall time - 31 -

STD45P4LLF6AG Electrical characteristics

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Table 7: Source-drain diode


ISD Source-drain current

-

-50 A

ISDM(1)

Source-drain current

(pulsed) -

-200 A

VSD(2) Forward on voltage VGS = 0 V, ISD = -50 A -

-1.3 V

trr Reverse recovery time ISD = -50 A, di/dt = 100 A/µs,

VDD = -32 V (see Figure 15: "Test

circuit for inductive load

switching and diode recovery

times")

- 27.5

ns

Qrr Reverse recovery

charge - 24.5

nC

IRRM Reverse recovery

current - -1.8

A

Notes:

(1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%.

Electrical characteristics STD45P4LLF6AG

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2.1 Electrical characteristics (curves)

Figure 2: Safe operating area

Figure 3: Thermal impedance

Figure 4: Output characteristics

Figure 5: Transfer characteristics

Figure 6: Gate charge vs gate-source voltage

Figure 7: Static drain-source on-resistance

STD45P4LLF6AG Electrical characteristics

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Figure 8: Capacitance variations

Figure 9: Normalized gate threshold voltage vs temperature

Figure 10: Normalized on-resistance vs temperature

Figure 11: Normalized V(BR)DSS vs temperature

Figure 12: Source-drain diode forward characteristics

For the P-channel Power MOSFET, current and voltage polarities are reversed.

Test circuits STD45P4LLF6AG

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3 Test circuits Figure 13: Switching times test circuit for

resistive load

Figure 14: Gate charge test circuit

Figure 15: Test circuit for inductive load switching and diode recovery times

STD45P4LLF6AG Package information

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4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Package information STD45P4LLF6AG

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4.1 DPAK (TO-252) type A2 package information

Figure 16: DPAK (TO-252) type A2 package outline


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Table 8: DPAK (TO-252) type A2 mechanical data

Dim. mm

Min. Typ. Max.

A 2.20

2.40

A1 0.90

1.10

A2 0.03

0.23

b 0.64

0.90

b4 5.20

5.40

c 0.45

0.60

c2 0.48

0.60

D 6.00

6.20

D1 4.95 5.10 5.25

E 6.40

6.60

E1 5.10 5.20 5.30

e 2.16 2.28 2.40

e1 4.40

4.60

H 9.35

10.10

L 1.00

1.50

L1 2.60 2.80 3.00

L2 0.65 0.80 0.95

L4 0.60

1.00

R

0.20

V2 0°

8°


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Figure 17: DPAK (TO-252) recommended footprint (dimensions are in mm)


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4.2 DPAK (TO-252) packing information

Figure 18: DPAK (TO-252) tape outline


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Figure 19: DPAK (TO-252) reel outline

Table 9: DPAK (TO-252) tape and reel mechanical data

Tape Reel

Dim. mm

Dim. mm

Min. Max. Min. Max.

A0 6.8 7 A

330

B0 10.4 10.6 B 1.5

B1

12.1 C 12.8 13.2

D 1.5 1.6 D 20.2

D1 1.5

G 16.4 18.4

E 1.65 1.85 N 50

F 7.4 7.6 T

22.4

K0 2.55 2.75

P0 3.9 4.1 Base qty. 2500

P1 7.9 8.1 Bulk qty. 2500

P2 1.9 2.1

R 40

T 0.25 0.35

W 15.7 16.3

STD45P4LLF6AG Revision history

DocID027807 Rev 2 15/16

5 Revision history Table 10: Document revision history

Date Revision Changes

28-Apr-2015 1 First release.

22-Jul-2015 2

Modified: VGS values in absoute maximum ratings table and static table.

Updated: DPAK (TO-252) type A2 package information section updated.

Minor text changes.

STD45P4LLF6AG

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Documents

40 V, 12 mΩ typ., STripFET™ F6 Power D(2, TAB) · July 2015 DocID027807 Rev 2 1/16 ... Automotive-grade P-channel -40 V, 12 mΩ typ., -50 A STripFET™ F6 Power MOSFET in a DPAK