4/22/2020 Dear EE354L students, A. The Final Exam is on Thursday May 7, 2020 from 7:30 AM to 10:20 AM in online WebEx. You need to wake up latest by 7:00 AM. Make sure you set two or three alarms, so that you do not oversleep and miss the exam! It is an open-book open-notes online-proctored timed exam. General details: EE354_Online_Proctored_Exams_rules_and_procedure.pdf

At 7:20 AM, join your proctor’s WebEx meeting and share your video with him or her. At 7:25 AM download the exam pdf using your personalized link. Exam answering times and scanning and uploading times vary for different options as stated below: 1. Direct PDF annotation option (Option #1): Start answering your exam at 7:25 AM Stop answering by 10:15 AM. Upload by 10:25 AM PST 2. Print, write in pencil, and scan into a pdf file option (Option #2): Print (7:25-7:30 AM) and start answering at 7:30 AM. Stop answering by 10:20 AM. Scan your exam by 10:30 AM and upload by 10:40 AM PST 3. No printer and no tablet? Answer on your own paper (Option #3): Start answering your exam at 7:25 AM Stop answering by 11:10 AM (50 minutes extra compared to Option #1). Scan your exam by 11:20 AM and upload by 11:30 AM PST The weight of this exam is about 22.5% to 27.5% of the course grade.

Tentative weights for this semester

Weight 1 Weight 2

HW 6.25 6.25 Short Exercises 1.75 1.75 LAB 24.00 24.00 Project 10.00 10.00 TA 3.00 3.00 Quiz 8.00 10.00 MT 19.50 22.50 Final 27.50 22.50

100.00 100.00 Every semester, depending on what was actually covered/assigned, and how difficult/easy the three exams turned out to be, slight adjustment is applied to the weights after the final exam is graded. B. More than anything else, it is *important* that you get a good sleep on Wednesday 5/6/2020 night to do well on the Thursday morning exam starting at 7:20 AM. It is a *design* exam and you will need to think and design during the exam. So, you should not be too tired to think during the exam. Please try to do most of your preparation before that Wednesday. C. The Lab TAs may be able to hold special office hours during the week before the exam. If so, we will post special office hours on the blackboard and send out an email. Please make use of those hours. I am sorry I cannot hold hours as I need to write multiple final exams. D. I have not written the exam. This is only a recommendation. The exam is expected to be comprehensive but the later topics, which were not tested before are more important. D.0. Topics not covered in recent semesters: (a) Microprogrammed Control unit design dir, associated lab and HW#6 (b) cascading comparison units in a TREE fashion dir (c) Priority Encoders and cascading them dir So, please skip questions related to the above three topics when you review OLD previous exams. D.1. The later topics are Picoblaze (dir basics and user guide) architecture, assembly language, subroutines and interrupts , Timing design pdf, Shannon's expansion theorem pdf, timing lab pdf, Counters, special counters, Verilog coding of counters, Blocking and non-blocking assignments, EE201L_Special_counter_blocking_non_blocking_r1.pdf .pdf .zip, Memories, width and depth expansion, memory address ranges, natural boundaries,

memory address maps, shading of the populated area. FIFOs ( .pdf .wmv ), WP (write pointer), RP (Read pointer), depth = WP – RP, modulo subtraction, single-clock and two-clock FIFOs, (n+1)-bit counter for 2n location FIFO in the case of a 2-clock FIFO, CDC (clock domain crossing), double synchronization, Gray code to Binary code and Binary code to Gray code conversion, simple gray code counter (.pdf and first 13.5 minutes of the 39-minute recording .avi). Totem_pole_Open_collector_mux_barrel_shifter_Shannons_Expansion_Theorem (.wmv) Hand-shaking between producer and consumer (.pdf), Barrel shifters, Fixed priority resolvers and Rotating priority resolvers (.pdf), Combinational logic questions, Open-collector outputs (dir), tristate outputs (.pdf), tristate bus, UART Basics (.pdf) I2C Bus Protocol (.pdf), Carry Look-ahead Adders (CLAs) (dir) (.wmv folder). D.2. Depending on the time available to you, please go through a few past exams from the last four years’ Final exams. We posted these on the BB under announcements. I have reproduced below links to the last 9 semesters of exams and their solutions. Note: If you do not have time, then do not try to rush through these as that only breaks your confidence. Spring 2019 Final Exam (Go through all the questions) http://www-classes.usc.edu/engr/ee-s/254/EE354L_Sp2019_Exams/EE354L_Final_Spring2019.pdf Final Solution http://www-classes.usc.edu/engr/ee-s/254/EE354L_Sp2019_Exams/EE354L_Final_Spring2019_sol.pdf Fall 2018 Final Exam (Go through all the questions) http://www-classes.usc.edu/engr/ee-s/254/EE354L_Fall2018_Exams/EE354L_Final_Fall2018.pdf Final Solution http://www-classes.usc.edu/engr/ee-s/254/EE354L_Fall2018_Exams/EE354L_Final_Fall2018_sol.pdf Spring 2018 Final Exam (Go through all the questions) http://www-classes.usc.edu/engr/ee-s/254/EE354L_Sp2018_Exams/EE354L_Final_Spring2018.pdf Final Solution http://www-classes.usc.edu/engr/ee-s/254/EE354L_Sp2018_Exams/EE354L_Final_Spring2018_sol.pdf Fall 2017 Final Exam (Go through all the questions) http://www-classes.usc.edu/engr/ee-s/254/EE354L_Fall2017_Exams/EE354L_Final_Fall2017.pdf Final Solution http://www-classes.usc.edu/engr/ee-s/254/EE354L_Fall2017_Exams/EE354L_Final_Fall2017_sol.pdf Spring 2017 Final Exam (Go through all the questions) http://www-classes.usc.edu/engr/ee-s/254/EE354L_Sp2017_Exams/ee354_Final_Spring2017.pdf Final Solution http://www-classes.usc.edu/engr/ee-s/254/EE354L_Sp2017_Exams/ee354_Final_Spring2017_sol.pdf Fall 2016 Final Exam (Go through all the questions, except Q#1. Q#1 is lengthy and not good for final exam) http://www-classes.usc.edu/engr/ee-s/254/EE354L_Fall2016_Exams/EE354L_Final_Fall2016.pdf Final Solution http://www-classes.usc.edu/engr/ee-s/254/EE354L_Fall2016_Exams/EE354L_Final_Fall2016_sol.pdf Spring 2016 Final Exam (Go through all the questions) http://www-classes.usc.edu/engr/ee-s/254/EE354L_Sp2016_Exams/EE354L_Final_Spring2016.pdf Final Solution http://www-classes.usc.edu/engr/ee-s/254/EE354L_Sp2016_Exams/EE354L_Final_Spring2016_sol.pdf Fall 2015 Final Exam (skip Q7 as it is very long and it is based on the merge-sort lab, which is cancelled starting from Spring 2017 onwards) (do go through the rest of it): http://www-classes.usc.edu/engr/ee-s/254/EE354L_Fall2015_Exams/EE354L_Final_Fall2015.pdf Final Solution http://www-classes.usc.edu/engr/ee-s/254/EE354L_Fall2015_Exams/EE354L_Final_Fall2015_sol.pdf

Spring 2015 Final Exam (skip Q#1 as it is very long unless you have a lot of time) (do go through the rest of it): http://www-classes.usc.edu/engr/ee-s/254/EE254L_Sp2015_Exams/ee254_Final_Spring2015.pdf Final Solution http://www-classes.usc.edu/engr/ee-s/254/EE254L_Sp2015_Exams/ee254_Final_Spring2015_sol.pdf Fall 2014 Final Exam: (skip Q#4 and Q#5.3. These are items not covered.) (Also skip Q#5.5 as it is a silly question on barrel shifters) http://www-classes.usc.edu/engr/ee-s/254/EE254L_Fall2014_Exams/ee254L_Final_Fall2014.pdf Final Exam Solution: http://www-classes.usc.edu/engr/ee-s/254/EE254L_Fall2014_Exams/ee254L_Final_Fall2014_sol.pdf Spring 2014 Final Exam: (skip Q#5.2) http://www-classes.usc.edu/engr/ee-s/201/EE201L_Sp2014_Exams/ee201_final_Sp2014.pdf Final Exam Solution: http://www-classes.usc.edu/engr/ee-s/201/EE201L_Sp2014_Exams/ee201_final_Sp2014_sol.pdf Final Exam Solution: Q#1 Verilog code .zip file http://www-classes.usc.edu/engr/ee-s/201/EE201L_Sp2014_Exams/make_A_close_to_B_Sp2014_Final.zip =========================================== D.3 Final Exam: an example of question distribution =========================================== D.3.1. Labs (one question): We do not expect you to remember intricate details of any lab. There will be some questions mainly on the following labs. Please refer to pages 6 to 12 of the MT prep guide. D.3.1.1. Picoblaze (dir): Picoblaze Keypad interface lab (dir), Picoblaze Interrupts_on_picoblaze.pdf only section A and page 40/75 of Section D to the extent covered in lecture (dir) D.3.1.2. Lab #6a RTL Coding -- Divider Example -- Debouncing, Single_stepping, Multi-stepping http://www-classes.usc.edu/engr/ee-s/254/ee201l_lab_manual/ee354_divider_single_step/handout_files/EE354L_divider.pdf D.3.1.3. Lab #7 -- GCD -- RTL design -- Verilog Lab http://www-classes.usc.edu/engr/ee-s/254/ee201l_lab_manual/gcd_verilog/handout_files/ee354_GCD_rev5.pdf D.3.1.4. Lab #8 -- Writing Testbenches http://www-classes.usc.edu/engr/ee-s/254/ee201l_lab_manual/Testbenches/handout_files/ee354_testbench.pdf D.3.1.5. Lab #10 Timing Analysis and Timing Constraints http://www-classes.usc.edu/engr/ee-s/254/ee201l_lab_manual/Timing/handout_files/ee354l_timing.pdf D.3.2. Verilog coding: (one question) You may be asked to complete a few lines (no more than 15 lines) in a given Verilog code to describe or test a combinational logic or a RTL design similar to your HW#8a, which includes a state machine and a datapath. Items such as truncated counters, cascaded counters, barrel shifters, fixed priority resolvers, rotating priority resolvers, can also be targets of coding questions. You do not have to write the complete code. You will write a few critical lines, where an unprepared student would make mistakes in using appropriate assignments (blocking/non-blocking), initializing (or not having to initialize) data register under reset, initializing clock in a testbench, etc. Testbench writing or reading and understanding is also included. Practice item: Q#1.2 of Spring 2014 Final Exam, Solution, and Verilog code zip file D.3.3. RTL design/analysis and Data path design (one major question): State diagram/waveform completion/analysis similar to HW#8a Practice item: Q#5 of Fall 2013 Final Exam and Solution D.3.4. Memories and FIFOs: 2 to 4 medium questions Practice item: Memory Q#2 of Spring 2014 Final Exam and Solution Practice item: FIFO Q#4 of Spring 2014 Final Exam and Solution D.3.5. Counters: (one question) Chapter 10 in class notes Go through Q#3 of Spring 2014 Final Exam and Solution

D.3.6. Timing: One question on Ch#9 and HW#9 Practice item: Q#1 of Spring 2012 Final Exam and Solution Do not have to go through the calculations. Just understand the following three hook-ups of the up/down counter and know that the three hook-ups have different timing advantages and area (cost) advantages depending on when (or how late) U_Bar/D and EN arrive in the clock.

D.3.6.1. A question on Shannon's expansion theorem and its application in synthesizing logic with late arriving signals Practice item: Q#1.2 and Q#1.3 of Spring 2011 MT#2 Exam and Solution D.3.7. Synchronization of Asynchronous inputs: Practice item: Bottom half of Q#4 of Spring 2013 Final Exam and Solution D.3.8. Open-collector output gates and tristate output devices: Simple question. Practice item for Open-collector: Q#1.5 of Spring 2011 MT#2 Exam and Solution D.3.9. I2C protocol, simple questions Practice item for I2C: Q#4 of Spring 2012 Final Exam and Solution D.3.10. Handshake protocol (medium question) http://www-classes.usc.edu/engr/ee-s/201/EE201L_CLASSNOTES/EE201L_CLASSNOTES_Handshake/Full_Handshake_r1.pdf http://www-classes.usc.edu/engr/ee-s/201/EE201L_CLASSNOTES/EE201L_CLASSNOTES_Handshake/ee254_Introduction_to_Handshaking_with_figures.pdf D.3.11. Blocking and non-blocking assignments: EE201L_Special_counter_blocking_non_blocking_r1.pdf .pdf .zip D.3.12 Readable logic (Bubble to Bubble logic) Practice item: Q#5.2 from Final Fall 2015 exam sol, and Q#3 Final Spring 2017 exam sol Reproduced below is the Q#6 and its solution from Spring 2012 Midterm #2

D.4 State machine design is still important. Please try to go through some of the selected state machine questions gathered in the midterm preparation guide (pages 13 to 68): http://www-classes.usc.edu/engr/ee-s/254/EE354L_Sp2020_Exams/EE354L_MT_exam_preparation_Spring2020.pdf Good Luck! Gandhi, Yue, Andrew, Kishan, Jack, and Irene