5 4 3 2 1 D D TI TMS320C6678 EVM Board Rev. 3A …wfcache.advantech.com/support/DSPM-8301E_EVM (6678)-3.0...5 5 4 4 3 3 2 2 1 1 D D C C B B A A 88E1111 DSP TMS320C6678 CVDD When power

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DSPM-8301E

TI TMS320C6678 EVM Board

Project Code :PCB Rev. A104-1PCB PN :

PCB Thickness : 62 mils(1.6mm)12 Layers

19C2830103

DISCLAIMER: THIS CIRCUIT DESIGN ISPROVIDED AS REFERENCE ONLY,WITHOUT WARRANTY EXPRESSED ORIMPLIED. THE USER IS ENCOURAGEDTO PERFORM ALL DUE DILIGENCE WITHRESPECT TO DESIGN AND ANALYSIS.

Copyright (C) 2010 Texas Instruments Incorporated.All rights reserved. This document is proprietary to TIand is intended solely for use by TI and its customers.This document is not to be reproduced, distributed, ordisclosed to other parties in its entirety or in partwithout the express written consent of TI.

TI Information - SelectiveDisclosureTexas Instruments20450 Century BlvdGermantown, MD 20874USA

1.0 oz

1.0 oz

1.0 oz

1.0 oz

1.0 oz

1.0 oz

TOP

L2_GND

L3

L4_PWR

L5

L6_GND

L7_GND

L8

L9_PWR

L10

L11_GND

BOT

1.0 oz

1.0 oz

0.5 oz

0.5 oz

0.5 oz

0.5 oz

3.6mils

4mils

4.8mils

5mils

4.5mils

4mils

4.5mils

5mils

4.8mils

4mils

3.6mils

p.p

core

core

p.p

p.p

core

p.p

core

core

p.p

p.p

Rev. 3A

Title

Size Document Number Rev

Date: Sheet of

Designed for TI by ADVANTECH

DSPM-8301E A104-1

COVER PAGE

C1 40Monday, March 12, 2012

Title


Date: Sheet of


DSPM-8301E A104-1

COVER PAGE


Title


Date: Sheet of


DSPM-8301E A104-1

COVER PAGE


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

COVER PAGE

02

04

03

06

08

07

05

09

10

12

14

13

16

15

11

18

20

19

22

21

17

23

24

25

26

27

28

29

30

01

TITLE & TABLE OF CONTENTS

Page Description

32

34

33

DescriptionPage

31

BLOCK DIAGRAM_AMC

POWER SEQUENCE

POWER CONSUMPTION

POWER DISTRIBUTION

CLOCK DIAGRAM

35

Power VCC1V536

37 History_0

Power ucd9222

Power_VCC5 / VCC3V3_AUX

Power_1.2V/1.8V/2.5V/0.75V

FPGA_XC3S200AN_C

FPGA_XC3S200AN_B

DDR3_ECC

DDR3

FPGA_XC3S200AN_A

Connectors for HyperLink & Debug

RJ45/MISC

Gigabit Ethernet PHY

USB-JTAG

CLOCK_GEN3

CLOCK GEN2

DSP_POWERA

DSP_POWERB

DSP_POWERC

DSP_GND

DSP_SERDES_PORTS

DSP_DDR3

DSP_EMIF

DSP_JTAG_EMU_TSIP

DSP_MISC

DSP_CLOCK_Smart Reflex

BUS Management Map

AMC GF

MMC

FPGA_BLOCK


38

39

Title


Date: Sheet of


DSPM-8301E A104-1


C2 40Wednesday, March 07, 2012

Title


Date: Sheet of


DSPM-8301E A104-1



Title


Date: Sheet of


DSPM-8301E A104-1



5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AMC Board

AMC Port mapping

Port mapping

100MHz

SGMII

PIN

12

11

Port mappingPIN

13

14

15

00

01

02

03

04

05

06

07

08

09

10

16

17

18

19

20

TCLKA

TCLKB

FCLKA

TCLKC

TCLKDPCI-E_1

PCI-E_2

SRIO_1

SRIO_2

SRIO_3

SRIO_4

TSIP1 [0..3]

Alternate I2C link

TSIP_CLK0

TSIP_CLK1

TSIP_FS0

TSIP_FS1

TSIP0 [0..3]

N25Q128A21BSF40F TMS320C6678

1

+V3.3_MP

UARTMDIO

MAC1EMU[2:17]

JTAG&EMU[0:1]

MAC0

PCIEx2

EMIF

I2C

Hyper LinkDDR3

Miscellaneous I/O conn.

GP

IO[0

:15

](1.8

V)

EM

IF1

6(1

.8V

)

DS

P_

SP

I(1.8

V)

DS

P_

UA

RT

(3.3

V)

DS

P_

I2C

(1.8

V)

DS

P_

UA

RT

MAX3221EAE

RS232

CH-A

CH-B

USB-JTAGFT2232HL

DSP_SGMII_P1 & MDIO

DSP_UART

USBMini-USB

ENET PHY88E1111-B2

RJ45

SRIOx4

TSIPx2

SGMIIx1

PCIEx2

SRIOx4

GPIO

SPI

MMCIPMB-L

EMIF

AMC_State

#0

AMC_Statefrom MMC

DSP

POWER 12V

PWR CONN

DIP SW

GPIO[0:15]

SPI

AT25128B

SPI EEPROM

Power

FPGA

Others

RAMPower Control

PHY

(MSP430)

DDR3 -1333

DDR3-1333

w/ ECC

128M X 16 / 2GB

DSP_SPI#1

MMCJTAG

(XILINX)DSP_GPIO

XC3S200ANFPGA

CLK_SPI2

CLK_SPI3

ROM_SPI

HyperLink

50Gbps

iPass+HD

DSP

to FPGA

DSP_I2C

TSIPx2

128k-bit

Power ControlSequence

Control

SPI FlashNOR 128M-bit

JTAGFPGA JTAG

60-Pin EMU CONN.EMU[2:17]

JTAG & EMU[0:1]

HyperLink CONN.

JTAG & EMU[0:1]

2.54mmCOM1 connector

CLK#1

CDCE62005

CDCE62005

CLK#2

DS

P_

SG

MII_

P1

& M

DIO

BLOCK DIAGRAM_AMC

DIP_SWITCH

SWITCH(TS3L301)

TSIPx2Level-Shifter

EMIFA00

EMIFA01

EMIFA02

EMIFA03

EMIFA05

EMIFA04

EMIFA06

EMIFA07

EMIFA08

EMIFA09

EMIFA11

EMIFA10

EMIFA14

EMIFA13

EMIFA12

EMIFA15

EMIFA16

EMIFA17

EMIFA18

EMIFA19

EMIFA20

EMIFA21

EMIFA22

EMIFA23 EMIFD0

EMIFD1

EMIFD2

EMIFD3

EMIFD4

EMIFD5

EMIFD6

EMIFD7

EMIFD8

EMIFD9

EMIFD10

EMIFD11

EMIFD12

EMIFD13

EMIFD14

EMIFD15

EMIFCE1Z

EMIFCE2Z

EMIFBE0z

EMIFBE1z

EMIFOEz

EMIFWEz

EMIFRnW

EMIFWAIT1

40

GPIO00

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

GPIO07

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

77

SCL

SDA

GPIO06

TIMI0

TIMI1

SSPMISO

SSPMOSI

UARTTXD

UARTRXD

TIMO1

SSPCS1

SSPCK

UARTCTS

UARTRTS

TIMO0

80 39

Port mappingPIN

02

04

06

08

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

Port mappingPIN

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

Port mappingPIN

01

03

05

07

09

11

13

15

17

19

21

23

25

27

29

31

33

35

37

Port mappingPIN

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

79

2

80

1

79

GND

GND

Miscellaneous I/O 80 Pin conn. Signal

NU Resistors

DDR3(ECC)

1Gb X 8

EEPROM

M24M01-HRMN6TP

128k-byte

DEBUG_LED

BM_GPIO(0~15) /

PCIESSEN / User define

D2

User controlled LED - 4

SYSPG_D1 LED

D1

LEV

EL

SH

IFTSWITCH

(TS3L301)

AMC JTAG

AMC JTAG

JTAGSBW_MMC1

UCD9222_PMbus

AMC_JTAG

NUMONYXNAND512R3A2DZA6E

512Mb 64M X8)

NAND FLASH

Title


Date: Sheet of


DSPM-8301E A104-1

BLOCK DIAGRAM_AMC


Title


Date: Sheet of


DSPM-8301E A104-1

BLOCK DIAGRAM_AMC


Title


Date: Sheet of


DSPM-8301E A104-1

BLOCK DIAGRAM_AMC


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

88E1111

DSP TMS320C6678 CVDD

When power on

When power down

VDD DSPTMS320C6678

VCC1V0 Scaled/(CVDD)VCC1V0 Fixed/(CVDD1)VCC1V8/ (DVDD18)

VCC3V3_MP

Power Sequence

VCC12

VCC_1V0 scaled

XC3S200AN

VCC2V5

DSPTMS320C6678

VCC1V8

DDR3SDRAM

VCC1V0DSP TMS320C6678

DDR3 Vref

DSP TMS320C6678

DDR3

DDR3

MMC

VCC_1V0 Fixed

VCC1V8

0ms<t<100us

0ms<t<100us

VCC1V80ms<t<100us

VCC_1V0 Fixed0ms<t<100us

VCC_1V0 scaled VDD0ms<t<100ms

Ther is no specific power-up norpower-down sequence.

DSP TMS320C6678

DSP TMS320C6678

1.5V/(DDR3_IO)0.75V/(DDR3_Vref)

0ms<t<100us1.5V/(DDR3_IO)0.75V/(DDR3_Vref)

88E1111 (PHY)

2.5V

88E1111

1.2V

RESET#T=5mS

RESETFULL#

Reset Sequence

VCC3V3_MP_AMC

S6

S0

S3

S4

S5

S7

S8

S9

S10

88E1111

PMBUS &

UCD9222_ENA2

VCC1V8_EN

VCC1V5_EN

VCC0V75_EN

VCC2V5_EN

FT2232HOther

S11

S13

S12

S14

S15

S16

T0 S2 plane power stable to S3 enable signal assertion

DescriptionLabel Time

1ms

POR#

T=0mS

VCC3V3_AUX

2.5V

/ 1.2

V

1.5V/(DDR3_IO)0.75V/(DDR3_Vref)

VCC5_ENS17

S18 XDS560V2 Mazzenine Board VCC5

VCC1V2XC3S200AN

S2

XILINX_XC3S200AN1.2V_AUX (VCCINT)1.8V_AUX (VCC1V8_AUX)

Ther is no specific power-up norpower-down sequence. XILINX_XC3S200AN

VCC1V8_AUXXC3S200AN

S1

by DSP chip

RESETSTAT#

0.75

V (

DS

P)

1.0V

_sca

led

1.0V

_fix

ed

VC

C1V

8

1.5V

(D

SP

)

3.3V

/ 1.

8V/

1.2V

REFCLKP&N

DDRCLKP&N CLK Sequence

3.3V_AUX (VCCAUX)

Power Sequence

VCC0V75

UCD9222_ENA1

VCC1V5

UCD9222_VID2 &

byREFCLK3_PD#

byREFCLK2_PD#

CLOCK2_PLL_LOCK

CLOCK3_PLL_LOCK

T=5mS

T=5mS

T=5mS

T=5mS

T=5mS

T=5mS

T=5mS

includingperipherals.

Title


Date: Sheet of


DSPM-8301E A104-1

Power Sequence


Title


Date: Sheet of


DSPM-8301E A104-1

Power Sequence


Title


Date: Sheet of


DSPM-8301E A104-1

Power Sequence


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

POWER CONSUMPTION

Title


Date: Sheet of


DSPM-8301E A104-1

POWER CONSUMPTION


Title


Date: Sheet of


DSPM-8301E A104-1

POWER CONSUMPTION


Title


Date: Sheet of


DSPM-8301E A104-1

POWER CONSUMPTION


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3.3V / 0.3A

VCC0V75 @0.25ATPS51200(3.3 Control)VCC0V75_EN

Efficiency=80%

Efficiency=90%

Efficiency=90%

1.4A

0.79A

0.33A 2.35A

2.585

165uA

3.04A

TPS54231

Efficiency=80%

0.52A

VCC_5V_ENVCC5 @1A

TPS54620

XDS560V2 Mazzenine Board5.0V / 1A

TPS73701DCQ VCC1V2 @0.375A

TPS73701DCQ VCC1V8_AUX @0.3A

VCC1V8 @0.5A

AM

C G

old

Fin

ger VCC12 SmartReflex

UCD9222 + UCD7242

VCC2V5_ENVCC2V5 @0.21A

VCC1V5_ENVCC1V5 @2.1A

DDR3

XILINX_XC3S200AN1.2V_AUX/ 0.125A (VCCINT)3.3V_AUX/ 0.024A (VCCAUX)

DSPTMS320C6678VCC1V0 / 8A Scaled/(CVDD)VCC1V0 / 5A Fixed/(CVDD1)VCC1V8 / 0.33A (DVDD18)1.5V / 0.85A (DDR3_IO)0.75V/(DDR3_Vref)

0.75V / 0.25A (DDR3_Vref)1.5V / 1.2A (DDR3_VDD)

88E1111 (PHY)2.5V / 0.21A1.2V / 0.25A

FT2232H(USB-JTAG)

3.3V / 0.21A

RS232

3.3V

FLASH

SPI NOR FLASH

1.8V

1.8V

CVDD @ 8A

VCC1V0 @ 5A

TPS73701DCQ

PM_BUS

3.3V_MPVCC3V3_MP_AMC @ 165uA

TPS54620 VCC3V3_AUX @1.2A

POWER DISTRIBUTION

UCD9222_ENA [ 1..2]

VCC1V8_EN1TPS73701DCQ

DC Jack

Title


Date: Sheet of


DSPM-8301E A104-1

POWER DISTRIBUTION


Title


Date: Sheet of


DSPM-8301E A104-1

POWER DISTRIBUTION


Title


Date: Sheet of


DSPM-8301E A104-1

POWER DISTRIBUTION


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SRIO_SGMII_CLKP/N

PCIe_CLKP/N

MCM_CLKP/NFor HyperLink

CORE_CLKP/N

PA_SS_CLKP/N

DDR_CLKP/N

DSPTMS320C6678

FT2232HLX'TAL

TDM_CLKC +/-TDM_CLKD +/-

AMC Gold Finger

12MHZ

88E1111X'TAL

25MHZ

XILINXXC3S200AN

TSIP0_CLKA

CDCE62005 312.50MHz

312.50MHz

100MHz

100.00MHz

TDM_CLKA +/-TDM_CLKB +/-

TSIP0_CLKB

TSIP1_CLKA

TSIP1_CLKB

TSIP1_FSA

TSIP0_FSB

TSIP1_FSB

TSIP0_FSA

CLOCK DIAGRAM

66.667MHz

U0

U1

U2

U3

U4

CDCE62005

U0

U1

U2

U3

U4

100.00MHz

SEC_REF

+

-

+

-

TSIP CLOCK

TSIP Frame Sync

100.00MHz

PC

Ie_C

LK

P/N

(A

MC

)

10

0M

Hz

PCIe_CLKP/N (AMC)

100MHz

MUX

IN2

IN1

SEL (CONTROL BY FPGA)

TCLKB[p/n]

Support common HyperLink timing at25MHz

A103-1PRI_REF

Title


Date: Sheet of


DSPM-8301E A104-1

CLOCK DIAGRAM


Title


Date: Sheet of


DSPM-8301E A104-1

CLOCK DIAGRAM


Title


Date: Sheet of


DSPM-8301E A104-1

CLOCK DIAGRAM


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PMBUS_ALT#PMBUS_CTLPMBUS_CLKPMBUS_DAT

UCD9222_PG1UCD9222_ENA1

Default : TBD

GPIO[0:3]

DSPTMS320C6678

GPIO[0:15]

SPI_FPGA_CS#

SPI_FPGA_MISO

SPI_FPGA_MOSI

SPI_FPGA_SCK

ATMELAT25128B

SPI ROM

POR#

RESETFULL#

RESET#

PACLKSEL

LRRESETNMIEN#

CORESEL[0:3]

NMI#

LRESET#

BOOTCOMPLETE

HOUT

SYSCLKOUT

CLOCK GroupSPI_CLK_CS#[1..2]

Power Group

TI_MSP430F5435IPN

TI MMCUCD9222

Control

TI_TPS54620RGY

CS#

MISO

CLK

MOSI

TI_TPS73701DRBT

TI_TPS54231D

x3

x4

x1

Power

Sequences

ControlVCC2V5_ENVCC0V75_ENVCC1V8_EN1VCC5_ENVCC1V5_EN

VCC3V3_AUX_PGOODVCC5_PGOODVCC1V5_PGOOD

TI_CDCE62005 #1TI_CDCE62005 #2

FPGA

Storage

JTAG

FPGA

Boot & Deviceconfigurations

DSP

DSP

RESET &

ControlInterrupts

GPIO[4:7] GPIO[12:15]GPIO[8:11]

Test Connector 80-pin(Female)

PHYControl

DSP_POR#DSP_RESETFULL#DSP_RESET#DSP_PACLKSELDSP_LRRESETNMIEN#DSP_CORESEL[0..3]#DSP_NMI#DSP_LRESET#

DSP_HOUTDSP_BOOTCOMPLETE

DSP_SYSCLKOUT

+V3.3

+V3.3

+V3.3

+V3.3+V3.3

+V1.8

DSPTDM CLK

MMC

Control

LVDS

TDM_FS[0:1] A/B

AMC Edge Connector(Golden Finger)

TDM_CLK[0:1] A/B

AMC_TDM_CLKA/B[p/n]AMC_TDM_CLKC/D[p/n]

XILINX_XC3S200AN-4FTG256C

TMS320C6678 EVM (AMC)

UCD9222_RSTPGUCD9222

SPI_FPGA_CS1

SPI_FPGA_MISO

SPI_FPGA_MOSISPI_FPGA_SCK

+V1.8DSP_TDM_FS[0:1]A/B

DSP_TDM_CLK[0:1]A/B

SPI

DSP

VCC0V75_PGOODVCC2V5_PGOOD

RESET

COLD RESET

WARM RESET

FPGA_BLOCK

DSP_GPIO[0 : 15]

FULL RESET

SPI_MMC_CS#SPI_MMC_MISOSPI_MMC_SCKSPI_MMC_MOSI

MMC_DETECT#

MMC_WARM_RST#

MMC_RESETSTAT#MMC_POR#

TRGRSTZ

+V1.8BM_GPIO[0 : 15]

User SwitchPCIESSEN

Default : TBD

UCD9222_PG2UCD9222_ENA2

60-pin emulation

(Female)

+V3.3

+V1.8

UCD9222_VID2

+V1.8

+V1.8

TIMI[0]

TIMI0

PM BUS

SPI_CLK_CK[1..2]SPI_CLK_MOSI[1..2]SPI_CLK_MISO[1..2]REFCLK1_PD#[1..2]PLL_LOCK[1..2]

CLOCKConfigurations (1)

88E1111-B2

MARVELL +V3.3

PHY_INT#PHY_RST#

BSC_JTAG_TDI

BSC_JTAG_TCKBSC_JTAG_TMSBSC_JTAG_RST#

FPGA_TDI BSC_JTAG_TDO

PHY_TDI PHY_TDO

+V3.3

FPGA_TDO

MULTIPLEXER

+V3.3FPGA_ICS557_SELFPGA_ICS557_PD#FPGA_ICS557_OE

IDT557-08 PCIe clk select

PG2

ENA2

TI UCD9222

Clk

Control

Alert

Data

PG1

ENA1

UCD9222_VID2

PG

RESET

PIN HEADER

Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_BLOCK

B8 40Wednesday, March 07, 2012

Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_BLOCK


Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_BLOCK


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DSPTMS320C6678

I2C

PMBus

FPGA(XILINX_XC3S200AN)

MDI/O

AMC Gold Finger

IPMB-L

SPI

SPI1

MM

C_R

ES

ET

ST

AT

#

FP

_PO

R_IN

_AM

C#

MMC(MSP430)

SmartReflex(UCD9222)

ENET PHY(88E1111)

EEPROM(128KB)

I2C

CDCE62005SPI2

Power Sequences ControlGPIO

WA

RM

_RE

SE

T_A

MC

#

AM

C_D

ET

EC

T#

EEPROM(AT25128B)(128kb)

SPI

CDCE62005

PO

R#

RE

SE

TF

UL

LZ

#

RE

SE

TZ

#

Management Map

(Pin-Header 3x1)

UART

RS232MAX3221EAE

USB-JTAGFT2232HL

Mini-USB(Jumper Option)

Lev

el S

hifte

r

SN

74

AV

C4

T2

45

NU Resistors

MSP430 (MMC)

SEL

EMU_DETzEMU_DET PIN

EMU CONN.

SWITCH(TS3L301)

High-Speed

(CS1z)

DSP_RESETSTAT#

I2C

MDI/O JTAG

80-pin Header

JTAG

JTAG

UART

JTAGJTAG +V1.8

+V1.8

+V1.8

UART+V3.3

USB

Console port

RS232

SPI3

MDC

The NU resistors on these connections to the MSP430 are for debug use only and will be used only with the shunts removed from pins 1 and 2 of CN7

NU Resistors

+V1.8

MDI/O

+V2.5

Level Shifter

PCA9306DCUT

MDI/OMDCMDC

MDC

0-ohm

Level Shifter

PCA9306DCUT

JTAG

TMS/TCK/TRSTn

TDO

TDI TDO

TDI

JTAG

TAP_FPGA1

JTAG

FPGA

XC3S200AN

Boundary ScanJTAG and

DSP_RESETSTAT#

MMC_PS_N0MMC_PS_N1

MMC_ENABLE_N

JTAG

PHY (88E1111)

Lev

el

Sh

ifte

r

JTAG

+V1.8

JTAG

+V3.3

FT2232HL_RESET#

SEL

SWITCH(TS3L301)

High-Speed AMC JTAG

+V3.3

+V3.3

USB JTAG

AMCedge connector

TCK

PHY_TCK

FPGA_TCK

TDO TDI

(ST M24M01-HRMN6TP)

( 0X51h )( 0X50h )

Title


Date: Sheet of


DSPM-8301E A104-1

Management Map


Title


Date: Sheet of


DSPM-8301E A104-1

Management Map


Title


Date: Sheet of


DSPM-8301E A104-1

Management Map


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

OVP: ~12.7V+0.6V = ~13.3VFront panel and ESD Strip

Management Power

A104-1

A103-1

TR

IP1

TR

IP3

TR

IP2

DSP_SDADSP_SCL DSP_SCL_AMC

DSP_SDA_AMC

TDM_CLKD_PTDM_CLKD_N

AMC0_SGMII0_TX_DPAMC0_SGMII0_TX_DN

MMC_PS_N1

MMC_PS_N1

MMC_GA1

MMC_ENABLE_N

SMB_SCL_IPMBL

MMC_PS_N0

MMC_GA0

SMB_SDA_IPMBL

MMC_GA2

AMCC_P11_SRIO4_RXNAMCC_P11_SRIO4_RXP

AMCC_P9_SRIO2_TXNAMCC_P9_SRIO2_TXP

AMCC_P10_SRIO3_RXPAMCC_P10_SRIO3_RXN



AMCC_P11_SRIO4_TXPAMCC_P11_SRIO4_TXN



AMC0_SGMII0_RX_DPAMC0_SGMII0_RX_DN

AMCC_P5_PCIe_RX2PAMCC_P5_PCIe_RX2N


AMCC_P5_PCIe_TX2P_CAMCC_P5_PCIe_TX2N_C

AMCC_P4_PCIe_TX1P_CAMCC_P4_PCIe_TX1N_C

TDM_CLKA_PTDM_CLKA_N

TDM_CLKC_PTDM_CLKC_N

TDM_CLKB_PTDM_CLKB_N

AMCC_P12_TDM0_TX1AMCC_P12_TDM0_TX3

AMCC_P13_TDM1_TX3


AMCC_P13_TDM1_TX1


TSIP1_TX1_RTSIP1_TX3_R

TSIP0_TX1_RTSIP0_TX3_R TSIP0_RX1

TSIP0_RX3

TSIP0_TX3

TSIP0_TX1

TSIP1_TX0_RTSIP1_TX2_R

TSIP1_TX0

TSIP1_TX2TSIP1_RX0TSIP1_RX2

TSIP0_TX0TSIP0_TX0_R

TSIP0_RX0TSIP0_RX2

TSIP0_TX2_RTSIP0_TX2

TSIP1_TX1

TSIP1_TX3TSIP1_RX1TSIP1_RX3

AMC_JTAG_TDI

AMC_JTAG_TDO

AMC_JTAG_TMS

AMC_JTAG_TCK

AMC_JTAG_RST#

DSP_SCL_AMC_160 DSP_SCL_AMCDSP_SDA_AMC_159 DSP_SDA_AMC

DSP_SDA_AMCDSP_SDA_AMC_130DSP_SCL_AMCDSP_SCL_AMC_129

VCC12

VCC12

TRIP1

VCC1V8 VCC3V3_AUX

VCC3V3_AUX

VCC1V8

VCC12

VCC3V3_MP_AMC

VCC1V8

VCC3V3_AUX VCC1V8_AUX

VCC3V3_AUX

INDSP_SCL(16,29)BIDSP_SDA(16,29)

INAMC0_SGMII0_TX_DP(12)INAMC0_SGMII0_TX_DN(12)

OUTSMB_SCL_IPMBL(11)

OUTAMC0_SGMII0_RX_DP(12)OUTAMC0_SGMII0_RX_DN(12)

OUTPCIE_REF_CLK_P(17)OUTPCIE_REF_CLK_N(17)

OUT TDM_CLKD_P (30)OUT TDM_CLKD_N (30)

OUT TDM_CLKC_P (30)OUT TDM_CLKC_N (30)

BISMB_SDA_IPMBL(11)

OUTAMCC_P4_PCIe_RX1P(12)

OUT AMCC_P11_SRIO4_RXP (12)OUT AMCC_P11_SRIO4_RXN (12)

OUTAMCC_P4_PCIe_RX1N(12)

OUTAMCC_P5_PCIe_RX2P(12)OUTAMCC_P5_PCIe_RX2N(12)

OUTMMC_ENABLE_N(11)

INMMC_GA0(11)

INMMC_GA1(11)

INMMC_GA2(11)

OUTTDM_CLKB_P(22)OUTTDM_CLKB_N(22)

OUTTDM_CLKA_P(30)OUTTDM_CLKA_N(30)

IN AMCC_P8_SRIO1_TXP (12)IN AMCC_P8_SRIO1_TXN (12)

IN AMCC_P9_SRIO2_TXN (12)IN AMCC_P9_SRIO2_TXP (12)






OUT TSIP0_RX1 (15)OUT TSIP0_RX3 (15)

IN TSIP0_TX3 (15)

IN TSIP0_TX1 (15)


IN TSIP1_TX0 (15)

IN TSIP1_TX2 (15)


IN TSIP0_TX0 (15)

IN TSIP0_TX2 (15)


IN TSIP1_TX3 (15)

IN TSIP1_TX1 (15)

INAMCC_P4_PCIe_TX1P(12)INAMCC_P4_PCIe_TX1N(12)

INAMCC_P5_PCIe_TX2P(12)INAMCC_P5_PCIe_TX2N(12)

IN AMC_JTAG_TDO (26)OUT AMC_JTAG_TDI (26)

OUT AMC_JTAG_TMS (26)OUT AMC_JTAG_RST# (26)

OUT AMC_JTAG_TCK (26)

Title


Date: Sheet of


DSPM-8301E A104-1

AMC GF


Title


Date: Sheet of


DSPM-8301E A104-1

AMC GF


Title


Date: Sheet of


DSPM-8301E A104-1

AMC GF


R157 NL/0C5251uF16V

GS D

Q10AO3401

1

32

R160 NL/0

C326 0.1uF 16V

R930 100K

R158 NL/0

R484 0

R180 10K

G

S

D Q112N7002

1

32

U13TI_TXS0108EPWR

A11V

CC

A2

A23

A34

A45

A56

A67

A78

A89

OE10

B120 V

CC

B19

B218

B317

B416

B515

B614

B713

B812

GN

D11

U245

TI_PCA9306DCUT

GND1

VREF12

SCL13

SDA14

SDA25SCL26VREF27EN8

C369 0.1uF 16V

R144 0

C5161000pF50V

R151 0

R936 10M

R445 10K

R933100K

R105 22

R339100K

R148 0

R150 0

R175 2K

C46610uF16V

C1280.1uF16V

C5490.1uF50V

R106 22

R120 22

R122 22R152 22

C552 1uF 25V

C1600.1uF16V

R161 NL/0

R9351K

R119 22

R149 0

R446 10K

R145 0

R124 22

Q12MMBT3904LT1

2

1

3

C5500.1uF50V

R123 22

R447 10K

R146 0

R931100K

C3550.1uF16V

R487 0

DC_IN1

JACK_3H

1

23

AMC1

GF-AMC-B

GND_11

GND_27

GND_310

PWR_12V_12

PS13

MP4

GA05

RSRVD66

RSRVD88

PWR_12V_29

Tx0+11

Tx0-12

GND_413

Rx0+14

Rx0-15

GND_516

GA117

PWR_12V_318

GND_619

Tx1+20

Tx1-21

GND_722

Rx1+23

Rx1-24

GND_825

GA226

PWR_12V_427

GND_928

Tx2+29

Tx2-30

GND_1031

Rx2+32

Rx2-33

GND_1134

Tx3+35

Tx3-36

GND_1237

Rx3+38

Rx3-39

GND_1340

ENABLE41

PWR_12V_542

GND_1443

Tx4+44

Tx4-45

GND_1546

Rx4+47

Rx4-48

GND_1649

Tx5+50

Tx5-51

GND_1752

Rx5+53

Rx5-54

GND_1855

SCL_L56

GND_1958

Tx6+59

Tx6-60

GND_2061

Rx6+62

Rx6-63

GND_2164

Tx7+65

Tx7-66

GND_2267

Rx7+68

Rx7-69

GND_2370

SDA_L71

PWR_12V_657

PWR_12V_772

GND_2473

TCLKA+74

TCLKA-75

GND_2576

TCLKB+77

TCLKB-78

GND_2679

FCLKA+80

FCLKA-81

GND_2782

PS083

PWR_12V_884

GND_2885

GND_2986Rx8-87Rx8+88

Tx8+91

Tx8-90

GND_3089

Rx9+94

Rx9-93

GND_3192

Tx9+97

Tx9-96

GND_3295

Rx10+100

Rx10-99

GND_3398

Tx10+103

Tx10-102

GND_34101

Rx11+106

Rx11-105

GND_35104

Tx11+109

Tx11-108

GND_36107

Rx12+112

Rx12-111

GND_37110

Tx12+115

Tx12-114

GND_38113

Rx13+118

Rx13-117

GND_39116

Tx13+121

Tx13-120

GND_40119

Rx14+124

Rx14-123

GND_41122

Tx14+127

Tx14-126

GND_42125

GND_43128

Rx15+130

Rx15-129

GND_44131Tx15-132Tx15+133GND_45134

TCLKC+136

TCLKC-135

TCLKD+139

TCLKD-138

GND_46137

Rx17+142

Rx17-141

GND_47140

Tx17+145

Tx17-144

GND_48143

Tx18+151

Tx18-150

GND_50149

Rx18+148

Rx18-147

GND_49146

Tx19+157

Tx19-156

GND_52155

Rx19+154

Rx19-153

GND_51152

Tx20+163

Tx20-162

GND_54161

Rx20+160

Rx20-159

GND_53158

GND_55164TCK165TMS166TRST167TDO168TDI169GND_56170

C411 0.1uF16V

R448 10K

D12BZX84-C12

1 2

3

D3ASD500V

1 2

TP30

R147 0

R932100K

C5261uF

16V

R90 2K

C301 0.1uF 16V

R449 10K

R937 10M

R958 4.7K

FAN1

WB_3V_2.0mm

123

R934100K

R964 10K

C302 0.1uF 16V

ESD1

AMC-ESD-B

1 2 34

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SpyBiWire

(BLUE LED)

(RED LED)

Power for MSP430

The NU resistors on these connections to the MSP430 are for debug use only and will be used only with the shunts removed from pins 1 and 2 of CN7

SPI I/F is for Advantech FPGA debugging.

MMC_XTAL1

MMC_XTAL2MMC_XTAL1MMC_XTAL2

MMC_LED2

MMC_LED1

MMC_ENABLE_N

MMC_SBWTDIOMMC_GAPU

MMC_GA2

SMB_SCL_IPMBL

SMB_SDA_IPMBL

MMC_GAPUMMC_LED1

MMC_LED2

MMC_SBWTCK

MMC_GA1

MMC_GA0

MMC_MOSIMMC_MISO

MMC_SCK

MMC_STE

MMC_P43

MMC_SBWTCKMMC_SBWTDIO

MMC_SBWTDIO

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP

VCC3V3_MP VCC3V3_AUX

VCC3V3_MP_AMC

VCC3V3_MP

VCC3V3_MP

IN MMC_ENABLE_N (10)

OUT MMC_POR_IN_AMC# (30)

OUT MMC_DETECT# (30)

OUTMMC_GA0(10)OUTMMC_GA1(10)OUTMMC_GA2(10)

IN MMC_RESETSTAT# (30)IN MMC_BOOTCOMPLETE (30)

OUT MMC_WR_AMC# (30)

OUT UART_FT_RX (16,26)IN UART_FT_TX (16,26)

IN SMB_SCL_IPMBL (10)BI SMB_SDA_IPMBL (10)

IN MMC_SPI_SCK (31)

OUT MMC_SPI_MISO (31)IN MMC_SPI_MOSI (31)IN MMC_SPI_STE (31)

Title


Date: Sheet of


DSPM-8301E A104-1

MMC


Title


Date: Sheet of


DSPM-8301E A104-1

MMC


Title


Date: Sheet of


DSPM-8301E A104-1

MMC


TP9

R1610K

BD2 19-215SUBC/S280/TR81 2

R960 NL/0

C5240.1uF16V

TP8

C20.1uF16V

C100.1uF16V

R2 33K

C30.1uF16V

G

S

DQ12N7002

1

32

R4 330

D9 RB751V4012

R1 33K

C7 0.47uF10V

C40.1uF16V

C5 22pF50V

R963 NL/0

R962 NL/0

C10.1uF16V

D10 RB751V4012

R11NL/10K

R7 NL/0

SBW_MMC1W_4V_2.54mm

1234

R20NL/0

MMC1

TI_MSP430F5435IPN

P6.4/A41

P6.5/A52

P6.6/A63

P6.7/A74

P7.4/A125

P7.5/A136

P7.6/A147

P7.7/A158

P5.0/A8/VREF+/VeREF+9

P5.1/A9/VREF-/VeREF-10

AVCC11

AVSS12

P7.0/XIN13

P7.1/XOUT14

DVSS115

DVCC116

P1.0/TA0CLK/ACLK17

P1.1/TA0.018

P1.2/TA0.119

P1.3/TA0.220

P1.

4/T

A0.

321

P1.

5/T

A0.

422

P1.

6/S

MC

LK23

P1.

724

P2.

0/T

A1C

LK/M

CLK

25

P2.

1/T

A1.

026

P2.

2/T

A1.

127

P2.

3/T

A1.

228

P2.

4/R

TC

CLK

29

DV

SS

330

DV

CC

331

P2.

532

P2.

6/A

CLK

33

P2.

7/A

DC

12C

LK/D

MA

E0

34

P3.

0/U

CB

0ST

E/U

CA

0CLK

35

P3.

1/U

CB

0SIM

O/U

CB

0SD

A36

P3.

2/U

CB

0SO

MI/U

CB

0SC

L37

P3.

3/U

CB

0CLK

/UC

A0S

TE

38

P3.

4/U

CA

0TX

D/U

CA

0SIM

O39

P3.

5/U

CA

0RX

D/U

CA

0SO

MI

40

P3.6/UCB1STE/UCA1CLK41P3.7/UCB1SIMO/UCB1SDA42P4.0/TB0.043P4.1/TB0.144P4.2/TB0.245P4.3/TB0.346P4.4/TB0.447P4.5/TB0.548VCORE49DVSS250DVCC251P4.6/TB0.652P4.7/TB0CLK/SMCLK53P5.4/UCB1SOMI/UCB1SCL54P5.5/UCB1CLK/UCA1STE55P5.6/UCA1TXD/UCA1SIMO56P5.7/UCA1RXD/UCA1SOMI57P7.2/TB0OUTH/SVMOUT58P7.3/TA1.259P8.0/TA0.060

P8.

1/T

A0.

161

P8.

2/T

A0.

262

P8.

3/T

A0.

363

P8.

4/T

A0.

464

P8.

5/T

A1.

065

P8.

6/T

A1.

166

DV

CC

467

DV

SS

468

P5.

2/X

T2I

N69

P5.

3/X

T2O

UT

70T

ES

T/S

BW

TC

LK71

PJ.

0/T

DO

72P

J.1/

TD

I/TC

LK73

PJ.

2/T

MS

74P

J.3/

TC

K75

RS

T/N

MI/S

BW

TD

IO76

P6.

0/A

077

P6.

1/A

178

P6.

2/A

279

P6.

3/A

380

C8 22pF50V

Y132.768KHz_12.5pF

14

3 2

R153.3K

TP17

B1 120_100MHz

R961 NL/0

C6 0.1uF16V

R143.3K

RD1 KP-1608EC1 2

TP7

R133.3K

R6 NL/0

R3 330

R18NL/0

C3711000pF50V

R108.2K

R19NL/0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SRIO

SGMII

PCIE

HyperLink

"Place ALL SERDES DC-blockingcaps on top layer adjacent to theDSP’s RX pins so that there areno additional vias"

“The HyperLink routes musthave a maximum of 2 vias andno via stubs – top layer routingrecommended”

Caution!AMCC_P8_SRIO1_RXP_CAMCC_P8_SRIO1_RXN_C

AMCC_P9_SRIO2_RXP_CAMCC_P9_SRIO2_RXN_C



AMC0_SGMII0_TX_DPAMC0_SGMII0_TX_DNAMC0_SGMII0_RX_DN

AMC0_SGMII0_RX_DP AMC0_SGMII0_RX_DP_CAMC0_SGMII0_RX_DN_C

DSP_SGMII_RXP_CDSP_SGMII_RXN_C

DSP_MDCDSP_MDIO




AMCC_P8_SRIO1_TXNAMCC_P8_SRIO1_TXPAMCC_P8_SRIO1_RXP

AMCC_P8_SRIO1_RXN



AMCC_P11_SRIO4_RXNAMCC_P11_SRIO4_RXP

DSP_SGMII_TXPDSP_SGMII_TXN

DSP_SGMII_RXPDSP_SGMII_RXN

DSP_MDC_1DSP_MDIO_1DSP_MDIO

AMCC_P4_PCIe_RX1P_CAMCC_P4_PCIe_RX1PAMCC_P4_PCIe_RX1N


AMCC_P4_PCIe_RX1N_C AMCC_P4_PCIe_TX1NAMCC_P4_PCIe_TX1P

AMCC_P5_PCIe_TX2PAMCC_P5_PCIe_TX2N

AMCC_P5_PCIe_RX2P_CAMCC_P5_PCIe_RX2N_C

HyperLink_RXN1_C

HyperLink_RXN3_C

HyperLink_RXP2_CHyperLink_RXN2_C

HyperLink_RXP3_C

HyperLink_REFCLKOUTP

HyperLink_RXP0HyperLink_RXN0




HyperLink_RXP0_CHyperLink_RXN0_C

HyperLink_REFCLKOUTN

HyperLink_RXP1_C

DSP_MDC

VCC1V8VCC3V3_AUX

VCC2V5

VCC1V8

OUT AMCC_P9_SRIO2_TXN (10)OUT AMCC_P9_SRIO2_TXP (10)

OUT AMCC_P11_SRIO4_TXP (10)

OUT AMCC_P8_SRIO1_TXN (10)





INAMCC_P11_SRIO4_RXN(10)INAMCC_P11_SRIO4_RXP(10)

INAMCC_P8_SRIO1_RXP(10)

INAMCC_P10_SRIO3_RXP(10)

INAMCC_P8_SRIO1_RXN(10)

INAMCC_P9_SRIO2_RXP(10)INAMCC_P9_SRIO2_RXN(10)

INAMCC_P10_SRIO3_RXN(10)

OUT DSP_SGMII_TXN (27)OUT DSP_SGMII_TXP (27)INDSP_SGMII_RXP(27)

INDSP_SGMII_RXN(27)

BI DSP_MDIO_1 (27)OUT DSP_MDC_1 (27)

INAMCC_P4_PCIe_RX1P(10)INAMCC_P4_PCIe_RX1N(10)

OUT AMCC_P4_PCIe_TX1P (10)OUT AMCC_P4_PCIe_TX1N (10)

OUT AMCC_P5_PCIe_TX2P (10)OUT AMCC_P5_PCIe_TX2N (10)

INAMCC_P5_PCIe_RX2P(10)INAMCC_P5_PCIe_RX2N(10)

OUT HyperLink_TXP0 (29)OUT HyperLink_TXN0 (29)




INHyperLink_RXP0(29)INHyperLink_RXN0(29)

INHyperLink_RXP1(29)INHyperLink_RXN1(29)

INHyperLink_RXN3(29)INHyperLink_RXP3(29)

INHyperLink_RXN2(29)INHyperLink_RXP2(29)

INAMC0_SGMII0_RX_DP(10)INAMC0_SGMII0_RX_DN(10) OUT AMC0_SGMII0_TX_DN (10)

OUT AMC0_SGMII0_TX_DP (10)

OUTHyperLink_RXFLCLK(29)OUTHyperLink_RXFLDAT(29)

IN HyperLink_TXFLCLK (29)IN HyperLink_TXFLDAT (29)

INHyperLink_RXPMCLK(29)INHyperLink_RXPMDAT(29)

OUT HyperLink_TXPMCLK (29)OUT HyperLink_TXPMDAT (29)

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_SERDES_PORTS


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_SERDES_PORTS


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_SERDES_PORTS


C20 0.1uF 16V

C168 0.1uF 16V

C468 0.1uF 16V

C19 0.1uF 16V

C170 0.1uF 16V

C307 0.1uF 16V

C465 0.1uF 16V

PCIe SERDES

pinout_rev0_3_2_customer

TI_TMS320C6678

DSP1Q

PCIERXN1AJ9 PCIERXP1AJ8

PCIERXN0AH7 PCIERXP0AH8

PCIETXP1AG8

PCIETXN1AG9

PCIETXN0AF8PCIETXP0AF7

R83 2K

C3270.1uF16V

C171 0.1uF 16V

VUSRSERDES

VUSRSMBUS


TI_TMS320C6678

DSP1R

MCMRXN2M1 MCMRXP2N1

MCMRXN3P2 MCMRXP3N2

MCMRXN1T1 MCMRXP1R1

MCMRXN0U2 MCMRXP0T2

MCMRXFLCLKW3

MCMRXFLDATW4

MCMRXPMCLKY3

MCMRXPMDATY4

MCMTXP3P4

MCMTXN3N4

MCMTXP0N5

MCMTXN0M5

MCMTXP1U4

MCMTXN1T4

MCMTXN2R5MCMTXP2T5

MCMREFCLKOUTPY1

MCMREFCLKOUTNW1

MCMTXFLCLKAA1

MCMTXFLDATAA3

MCMTXPMCLKAA2

MCMTXPMDATAA4

R82 2K

C308 0.1uF 16V

SERIAL RAPIDIOSERDES


TI_TMS320C6678

DSP1P

RIORXN3AJ15 RIORXP3AJ14

RIORXN2AH14 RIORXP2AH13

RIORXP0AJ12

RIORXN0AJ11

RIORXN1AH10 RIORXP1AH11

RIOTXN2AG15RIOTXP2AG14

RIOTXN3AF14RIOTXP3AF13

RIOTXP1AG12

RIOTXN1AG11

RIOTXP0AF11

RIOTXN0AF10

C172 0.1uF 16V

C305 0.1uF 16V

R957 10K

C470 0.1uF 16V

C173 0.1uF 16V

C306 0.1uF 16V

SGMII SERDES

MDIOpinout_rev0_3_2_customer

TI_TMS320C6678

DSP1O

SGMII0RXPAJ17

SGMII0RXNAJ18

SGMII1RXPAH16

SGMII1RXNAH17

SGMII0TXPAG17

SGMII0TXNAG18

SGMII1TXPAF16

SGMII1TXNAF17

MDIOG26

MDCLKH26

C511 0.1uF 16V

C164 0.1uF 16V

C401 0.1uF16V

C505 0.1uF 16V

TP5

C167 0.1uF 16V

TP6

C512 0.1uF 16V

C165 0.1uF 16V

R85 10K

R456 22

C12 0.1uF 16V

C166 0.1uF 16V

R457 22

C169 0.1uF 16V

C14 0.1uF 16V

R316100K

U244

TI_PCA9306DCUT

GND1

VREF12

SCL13

SDA14

SDA25SCL26VREF27EN8

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place these resistors at theend of the trace.

Trace need 20 mil.DDR3 Slew-Rate Setting (DDRSLRATE[1:0]):

0 1

0 0

1 1

1 0

Fastest

Fast

Slow

Slowest

A103-1

A103-1

A103-1

DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12DSP0_DDR3_EA13

DSP0_DDR3_EBA_1DSP0_DDR3_EBA_2

DSP0_DDR3_EBA_0

DSP0_DDR3_EDQ0DSP0_DDR3_EDQ1DSP0_DDR3_EDQ2DSP0_DDR3_EDQ3DSP0_DDR3_EDQ4DSP0_DDR3_EDQ5DSP0_DDR3_EDQ6DSP0_DDR3_EDQ7DSP0_DDR3_EDQ8DSP0_DDR3_EDQ9

DSP0_DDR3_EDQ10DSP0_DDR3_EDQ11DSP0_DDR3_EDQ12DSP0_DDR3_EDQ13DSP0_DDR3_EDQ14DSP0_DDR3_EDQ15DSP0_DDR3_EDQ16DSP0_DDR3_EDQ17DSP0_DDR3_EDQ18DSP0_DDR3_EDQ19DSP0_DDR3_EDQ20DSP0_DDR3_EDQ21DSP0_DDR3_EDQ22DSP0_DDR3_EDQ23DSP0_DDR3_EDQ24DSP0_DDR3_EDQ25DSP0_DDR3_EDQ26DSP0_DDR3_EDQ27DSP0_DDR3_EDQ28DSP0_DDR3_EDQ29DSP0_DDR3_EDQ30DSP0_DDR3_EDQ31DSP0_DDR3_EDQ32DSP0_DDR3_EDQ33DSP0_DDR3_EDQ34DSP0_DDR3_EDQ35DSP0_DDR3_EDQ36DSP0_DDR3_EDQ37DSP0_DDR3_EDQ38DSP0_DDR3_EDQ39DSP0_DDR3_EDQ40DSP0_DDR3_EDQ41DSP0_DDR3_EDQ42DSP0_DDR3_EDQ43DSP0_DDR3_EDQ44DSP0_DDR3_EDQ45DSP0_DDR3_EDQ46DSP0_DDR3_EDQ47DSP0_DDR3_EDQ48DSP0_DDR3_EDQ49DSP0_DDR3_EDQ50DSP0_DDR3_EDQ51DSP0_DDR3_EDQ52DSP0_DDR3_EDQ53DSP0_DDR3_EDQ54DSP0_DDR3_EDQ55DSP0_DDR3_EDQ56DSP0_DDR3_EDQ57DSP0_DDR3_EDQ58DSP0_DDR3_EDQ59DSP0_DDR3_EDQ60DSP0_DDR3_EDQ61DSP0_DDR3_EDQ62DSP0_DDR3_EDQ63

DSP0_DDR3_EDM_0DSP0_DDR3_EDM_1DSP0_DDR3_EDM_2DSP0_DDR3_EDM_3DSP0_DDR3_EDM_4DSP0_DDR3_EDM_5DSP0_DDR3_EDM_6DSP0_DDR3_EDM_7

DSP0_DDR3_EDQSP_0DSP0_DDR3_EDQSN_0DSP0_DDR3_EDQSP_1DSP0_DDR3_EDQSN_1DSP0_DDR3_EDQSP_2DSP0_DDR3_EDQSN_2DSP0_DDR3_EDQSP_3DSP0_DDR3_EDQSN_3DSP0_DDR3_EDQSP_4DSP0_DDR3_EDQSN_4DSP0_DDR3_EDQSP_5DSP0_DDR3_EDQSN_5DSP0_DDR3_EDQSP_6DSP0_DDR3_EDQSN_6DSP0_DDR3_EDQSP_7DSP0_DDR3_EDQSN_7

DSP0_DDR3_ECKP_0DSP0_DDR3_ECKN_0

DSP0_DDR3_EODT_0

U1_DDRSLRATE0U1_DDRSLRATE1

U1_DDRSLRATE0 U1_DDRSLRATE1

DSP0_DDR3_EMRESETN

DSP0_DDR3_ECAS#

DSP0_DDR3_EWE#DSP0_DDR3_ERAS#

DSP0_DDR3_ECKE_0

DSP0_DDR3_ECS_0#

DSP0_DDR3_EA14

DSP0_DDR3_ECC0DSP0_DDR3_ECC1DSP0_DDR3_ECC2DSP0_DDR3_ECC3DSP0_DDR3_ECC4DSP0_DDR3_ECC5DSP0_DDR3_ECC6DSP0_DDR3_ECC7

DSP0_DDR3_EDQSP_8DSP0_DDR3_EDQSN_8

DSP0_DDR3_EDM_8

DSP0_DDR3_EA0

DSP0_DDR3_EA1

DSP0_DDR3_EA2

DSP0_DDR3_EA3

DSP0_DDR3_EA4

DSP0_DDR3_EA5

DSP0_DDR3_EA6

DSP0_DDR3_EA7

DSP0_DDR3_EA8

DSP0_DDR3_EA9

DSP0_DDR3_EA10

DSP0_DDR3_EA11

DSP0_DDR3_EA12

DSP0_DDR3_EA13

DSP0_DDR3_ECS_0#

DSP0_DDR3_EBA_0

DSP0_DDR3_EBA_1

DSP0_DDR3_EBA_2

DSP0_DDR3_EODT_0

DSP0_DDR3_EWE#

DSP0_DDR3_ERAS#

DSP0_DDR3_ECAS#

DSP0_DDR3_ECKE_0

DSP0_DDR3_EA14

DSP0_DDR3_ECKP_0

DSP0_DDR3_ECKN_0

DSP_VREFSSTL

DSP_VREFSSTL

DSP0_DDR3_EA15

DSP0_DDR3_EA15

DSP0_DDR3_EMRESETN

VCC1V8 VCC1V8

VCC0V75

VCC0V75

VCC1V5

VCC1V5

VCC1V5

OUT DSP0_DDR3_EA[0..15] (24,25)

OUTDSP0_DDR3_EBA_0(24,25)OUTDSP0_DDR3_EBA_1(24,25)OUTDSP0_DDR3_EBA_2(24,25)

OUTDSP0_DDR3_EDM_0(24)OUTDSP0_DDR3_EDM_1(24)OUTDSP0_DDR3_EDM_2(24)OUTDSP0_DDR3_EDM_3(24)OUTDSP0_DDR3_EDM_4(24)OUTDSP0_DDR3_EDM_5(24)OUTDSP0_DDR3_EDM_6(24)OUTDSP0_DDR3_EDM_7(24)

OUTDSP0_DDR3_ECKP_0(24,25)OUTDSP0_DDR3_ECKN_0(24,25)

OUTDSP0_DDR3_EODT_0(24,25)

OUTDSP0_DDR3_EMRESETN(24,25)

OUTDSP0_DDR3_ECAS#(24,25)

OUTDSP0_DDR3_EWE#(24,25)OUTDSP0_DDR3_ERAS#(24,25)

OUTDSP0_DDR3_ECKE_0(24,25)

OUTDSP0_DDR3_ECS_0#(24,25)

BIDSP0_DDR3_ECC[0..7](25)

OUTDSP0_DDR3_EDM_8(25)

OUTDSP0_DDR3_EDQSP_0(24)OUTDSP0_DDR3_EDQSN_0(24)

OUTDSP0_DDR3_EDQSN_1(24)OUTDSP0_DDR3_EDQSP_1(24)



OUTDSP0_DDR3_EDQSN_4(24)



OUTDSP0_DDR3_EDQSP_4(24)



OUT DSP_VREFSSTL (24,25)

BI DSP0_DDR3_EDQ[8..15] (24)

BI DSP0_DDR3_EDQ[0..7] (24)

BI DSP0_DDR3_EDQ[24..31] (24)

BI DSP0_DDR3_EDQ[16..23] (24)

BI DSP0_DDR3_EDQ[40..47] (24)

BI DSP0_DDR3_EDQ[32..39] (24)

BI DSP0_DDR3_EDQ[56..63] (24)

BI DSP0_DDR3_EDQ[48..55] (24)

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_DDR3


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_DDR3


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_DDR3


R41 39.2 1%

R56 39.2 1%

R51 39.2 1%

R38 39.2 1%

R702K1%

C33 0.01uF 16V

R50 39.2 1%

C39 0.01uF 16V

C42 0.1uF 16V

R59 39.2 1%

R61 39.2 1%

R42 39.2 1%

R57 39.2 1% C40 0.1uF 16V

R66 4.7K 1%

C37 0.01uF 16V

R62 39.2 1%

R43 39.2 1%

C44 0.1uF 16V

C590.1uF16V

R60 39.2 1%

R45 39.2 1%

C43 0.01uF 16V

R64 39.2 1%

DDR3CONTROLLER


TI_TMS320C6678

DSP1K

DDRCLKOUTP0A12

DDRCLKOUTN0B12

DDRCLKOUTP1A16

DDRCLKOUTN1B16

DDRCKE0D11

DDRCKE1E18

DDRCE0zC11

DDRCE1zC12

DDRCASzD12

DDRRASzC10

DDRWEzE12

DDRBA0A13

DDRBA1B13

DDRBA2C13

DDRDQM0E29

DDRDQM1C27

DDRDQM2A25

DDRDQM3A22

DDRDQM4A10

DDRDQM5A8

DDRDQM6B5

DDRDQM7B2

DDRDQM8A20

DDRDQS0PC28

DDRDQS0NC29

DDRDQS1PA27

DDRDQS1NB27

DDRDQS2PA24

DDRDQS2NB24

DDRDQS3PA21

DDRDQS3NB21

DDRDQS4PA9

DDRDQS4NB9

DDRDQS5PB6

DDRDQS5NA6

DDRDQS6PB3

DDRDQS6NA3

DDRDQS7PD1

DDRDQS7NC1

DDRDQS8PA19

DDRDQS8NB19

DDRCB00E19

DDRCB01C20

DDRCB02D19

DDRCB03B20

DDRCB04C19

DDRCB05C18

DDRCB06B18

DDRCB07A18

DDRRESETzE11

DDRODT0D13

DDRODT1E13

DDRSLRATE0G27

DDRSLRATE1H27

VREFSSTLE14

PTV15G22

DDRA00A14

DDRA01B14

DDRA02F14

DDRA03F13

DDRA04A15

DDRA05C15

DDRA06B15

DDRA07D15

DDRA08F15

DDRA09E15

DDRA10E16

DDRA11D16

DDRA12E17

DDRA13C16

DDRA14D17

DDRA15C17

DDRD00E28

DDRD01D29

DDRD02E27

DDRD03D28

DDRD04D27

DDRD05B28

DDRD06E26

DDRD07F25

DDRD08F24

DDRD09E24

DDRD10E25

DDRD11D25

DDRD12D26

DDRD13C26

DDRD14B26

DDRD15A26

DDRD16F23

DDRD17F22

DDRD18D24

DDRD19E23

DDRD20A23

DDRD21B23

DDRD22C24

DDRD23E22

DDRD24D21

DDRD25F20

DDRD26E21

DDRD27F21

DDRD28D22

DDRD29C21

DDRD30B22

DDRD31C22

DDRD32E10

DDRD33D10

DDRD34B10

DDRD35D9

DDRD36E9

DDRD37C9

DDRD38B8

DDRD39E8

DDRD40A7

DDRD41D7

DDRD42E7

DDRD43C7

DDRD44B7

DDRD45E6

DDRD46D6

DDRD47C6

DDRD48C5

DDRD49A5

DDRD50B4

DDRD51A4

DDRD52D4

DDRD53E4

DDRD54C4

DDRD55C3

DDRD56F4

DDRD57D2

DDRD58E2

DDRD59C2

DDRD60F2

DDRD61F3

DDRD62E1

DDRD63F1

C35 0.01uF 16V

R37 39.2 1%

R771K1%

R46 39.2 1%

C41 0.01uF 16V

R72NL/2K1%

R65 39.2 1%

C38 0.1uF 16V

R712K1%

R86 39.2 1%

R781K1%

R44 39.2 1%

R63 39.2 1%

R52 39.2 1%

R5845.31%

C1140.1uF16V

R48 39.2 1%

R69NL/2K1%

R55 39.2 1%

C600.1uF16V

R49 39.2 1%

R53 39.2 1%

C34 0.1uF 16V

C36 0.1uF 16V

C31 0.1uF 16V

R47 39.2 1%

R54 39.2 1%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

A103-1NAND1 change to NAND512R3A2SZA6E(1410021742)

DSP_EMIFD0DSP_EMIFD1DSP_EMIFD2DSP_EMIFD3DSP_EMIFD4DSP_EMIFD5DSP_EMIFD6DSP_EMIFD7

DSP_EMIFBE0ZDSP_EMIFBE1Z

DSP_EMIFA00DSP_EMIFA01DSP_EMIFA02DSP_EMIFA03DSP_EMIFA04DSP_EMIFA05DSP_EMIFA06DSP_EMIFA07DSP_EMIFA08DSP_EMIFA09DSP_EMIFA10DSP_EMIFA11DSP_EMIFA12DSP_EMIFA13DSP_EMIFA14DSP_EMIFA15DSP_EMIFA16DSP_EMIFA17DSP_EMIFA18DSP_EMIFA19DSP_EMIFA20DSP_EMIFA21DSP_EMIFA22DSP_EMIFA23


DSP_EMIFWAIT0

NAND_WP#

DSP_EMIFRNW

DSP_EMIFOEZDSP_EMIFWEZ

DSP_EMIFWAIT0DSP_EMIFWAIT1

DSP_EMIFCE0ZDSP_EMIFCE1ZDSP_EMIFCE2Z


DSP_EMIFWEZ

DSP_EMIFOEZ

DSP_EMIFWAIT0DSP_EMIFCE0Z

DSP_EMIFA12DSP_EMIFA11

VCC1V8

VCC1V8

VCC1V8OUT DSP_EMIFBE0Z (29)OUT DSP_EMIFBE1Z (29)

OUT DSP_EMIFA00 (29)OUT DSP_EMIFA01 (29)OUT DSP_EMIFA02 (29)OUT DSP_EMIFA03 (29)OUT DSP_EMIFA04 (29)OUT DSP_EMIFA05 (29)OUT DSP_EMIFA06 (29)OUT DSP_EMIFA07 (29)OUT DSP_EMIFA08 (29)OUT DSP_EMIFA09 (29)OUT DSP_EMIFA10 (29)OUT DSP_EMIFA11 (29)OUT DSP_EMIFA12 (29)OUT DSP_EMIFA13 (29)OUT DSP_EMIFA14 (29)OUT DSP_EMIFA15 (29)OUT DSP_EMIFA16 (29)OUT DSP_EMIFA17 (29)OUT DSP_EMIFA18 (29)OUT DSP_EMIFA19 (29)OUT DSP_EMIFA20 (29)OUT DSP_EMIFA21 (29)OUT DSP_EMIFA22 (29)OUT DSP_EMIFA23 (29)

BIDSP_EMIFD0(29)BIDSP_EMIFD1(29)BIDSP_EMIFD2(29)BIDSP_EMIFD3(29)BIDSP_EMIFD4(29)BIDSP_EMIFD5(29)BIDSP_EMIFD6(29)BIDSP_EMIFD7(29)

BIDSP_EMIFD12(29)BIDSP_EMIFD13(29)BIDSP_EMIFD14(29)BIDSP_EMIFD15(29)

BIDSP_EMIFD8(29)BIDSP_EMIFD9(29)BIDSP_EMIFD10(29)BIDSP_EMIFD11(29)

OUT DSP_EMIFRNW (29)

OUT DSP_EMIFOEZ (29)OUT DSP_EMIFWEZ (29)

INDSP_EMIFWAIT1(29)

OUT DSP_EMIFCE1Z (29)OUT DSP_EMIFCE2Z (29)

INNAND_WP#(30)

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_EMIF


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_EMIF


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_EMIF


C5190.1uF16V

R236 22

R135 4.7K

R134 4.7K

R248 22

C15810uF6.3V

R249 22

NAND1

<Characteristic>NUMONYX_NAND512R3A2SZA6E

ALC4

CLD5

DU1A1

DU2A2

DU3A9

DU4A10

DU5B1

DU6B9

DU7B10

DU8L1

DU9L2

EC6

I/O0H4

I/O1J4

I/O2K4

I/O3K5

I/O4K6

I/O5J7

I/O6K7

I/O7J8

NC2D6

NC3D7

NC4D8

NC5E3

NC6E4

NC7E5

NC8E6

NC9E7

RD4

RBC8

VDD1H8

VDD2J6

WC7

WPC3

DU10L9

DU11L10

DU12M1

DU13M2

DU14M9

DU15M10

NC1D3

NC10E8

NC11F3

NC12F4

NC13F5

NC14F6

NC15F7

NC16F8

NC17G3

NC18G4

NC19G5

NC20G6

NC21G7

NC22G8

NC23H3

NC24H5

NC25H6

NC26H7

NC27J3

NC28J5

VSS1C5

VSS2K3

VSS3K8

C1590.1uF16V

R183 4.7K

EMIF16pinout_rev0_3_2_customer

TI_TMS320C6678

DSP1N

EMIFA21Y29EMIFA20W23

EMIFA22Y28

EMIFA16W29

EMIFA14W28

EMIFA15W27

EMIFA17W26

EMIFA13V24

EMIFA07U24

EMIFA18W25

EMIFA19W24

EMIFA03T25

EMIFBE1zR23

EMIFA09V29EMIFA08V28

EMIFA10V27

EMIFA11V26

EMIFA12V25

EMIFA23U23

EMIFD13AB24

EMIFD01AB29

EMIFD02AA29

EMIFD04AA27

EMIFD00Y27

EMIFD06AA26

EMIFD03Y26

EMIFD07AA25

EMIFD08Y25

EMIFD09AB25

EMIFD10AA24

EMIFD11Y24

EMIFD12AB23

EMIFD05AB27

EMIFD14AB26

EMIFD15AC25

EMIFCE2zR28EMIFCE1zR27

EMIFOEzR26

EMIFCE3zR25

EMIFBE0zR24

EMIFRnWP26

EMIFCE0zP25

EMIFA02U29

EMIFWEzP24

EMIFA05U28EMIFA04U27

EMIFWAIT0T29

EMIFWAIT1T28

EMIFA00T27

EMIFA06U25

EMIFA01T24

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XDS560V2 power connector

TSIP0, 1

JTAG & EMU

60

-pin

He

ad

erEMU_TCK_R

DSP_TCK_R

EMU_TCKR292

R291

DSP

DSP_TSIP0_CLKA0DSP_TSIP0_CLKB0

DSP_TSIP0_FSA0DSP_TSIP0_FSB0

DSP_EMU_00DSP_EMU_01


DSP_EMU_05


DSP_EMU_04

DSP_EMU_09


DSP_EMU_13


DSP_EMU_12

DSP_EMU_08

DSP_EMU_16


DSP_EMU_03_R DSP_EMU_03DSP_EMU_04_R DSP_EMU_04DSP_EMU_06_R DSP_EMU_06DSP_EMU_08_R DSP_EMU_08DSP_EMU_10_R DSP_EMU_10

DSP_EMU_11_R DSP_EMU_11DSP_EMU_13_R DSP_EMU_13DSP_EMU_15_R DSP_EMU_15DSP_EMU_16_R DSP_EMU_16

DSP_EMU_18_R DSP_EMU_18

DSP_EMU_05_RDSP_EMU_05DSP_EMU_07_RDSP_EMU_07DSP_EMU_09_RDSP_EMU_09

DSP_EMU_12_RDSP_EMU_12DSP_EMU_14_RDSP_EMU_14

DSP_EMU_17_RDSP_EMU_17

DSP_EMU_02 DSP_EMU_02_R

DSP_EMU_01_R

DSP_EMU_00_R

DSP_TVD

DSP_TRST#_R

DSP_TRST#

DSP_TDI

DSP_TDODSP_TCK

DSP_TMS

EMU_TCK_R

DSP_TDO_R

DSP_TDI_R

DSP_TMS_R

EMU_TCK_RDSP_TCK_R

DSP_TDI

DSP_TDO

DSP_TCK

DSP_TMS



EMU_EMU_01

EMU_TRST#

EMU_TCK

EMU_TDI

EMU_TDO

EMU_TMS

EMU_EMU_00

EXT_EMU_DET0

DSP_TRST#

EMU_EMU_00

EMU_EMU_01

DSP_TRST#_R

TRGRSTZ

VCC1V8

VCC1V8

VCC1V8


VCC3V3_AUX

VCC1V8

VCC5

VCC1V8

OUTEXT_EMU_DET0(26)

OUTDSP_TDO(26)INEMU_TDO(26)

INDSP_TDI(26)INDSP_TCK(26)

INDSP_TMS(26)INDSP_TRST#(26)

OUTEMU_TCK(26)

OUTEMU_TDI(26)

OUTEMU_TMS(26)

OUT EMU_TRST# (26)

INDSP_TSIP0_FSB0(30)

INDSP_TSIP0_CLKB0(30)

INDSP_TSIP0_FSA0(30)

INDSP_TSIP0_CLKA0(30)

INDSP_TSIP1_FSB1(30)

INDSP_TSIP1_CLKB1(30)

INDSP_TSIP1_FSA1(30)

INDSP_TSIP1_CLKA1(30)

INXDS560_IL(30)

OUTTRGRSTZ(30)

BIEMU_EMU_00(26)

BI EMU_EMU_01 (26)

BI DSP_EMU_00 (26)BI DSP_EMU_01 (26)

OUT TSIP1_TX0 (10)

OUT TSIP1_TX3 (10)

OUT TSIP1_TX1 (10)OUT TSIP1_TX2 (10)



INTSIP1_RX1(10)INTSIP1_RX2(10)

INTSIP1_RX0(10)

INTSIP1_RX3(10)

INTSIP0_RX1(10)

INTSIP0_RX3(10)

INTSIP0_RX0(10)

INTSIP0_RX2(10)

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_JTAG_EMU_TSIP


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_JTAG_EMU_TSIP


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_JTAG_EMU_TSIP


560V2_PWR1

PH_4x2V_2.54mm

2468

1357 R282 10

R266 10

R905 4.7K

R896 4.7K

R291 10

R900 NL/4.75K

R271 10

R293 10

R279 10

TSIP0

TSIP1


TI_TMS320C6678

DSP1T

TX03AG24

TX05AF24

TX00AE24

TR03AD24

TR04AC23

TX07AF23TX06AE23

TR02AD23

TX13AE21

TR11AD21

TR12AC21

TR15AJ20

TX16AH20

TX14AG20

TX17AF20

TX15AE20

TR01AJ25

CLKA1AJ23

TR05AH25

CLKB1AH23

FSA0AJ26

FSA1AG23

TR00AH26

FSB1AJ22

FSB0AG26

CLKB0AG25

TR07AE25

TX01AD25

TR06AC24

TX02AJ24

TX04AH24

TR10AE22

TX11AD22

TX12AC22

TR14AH22 TR13AJ21

TR16AH21

TR17AG21

TX10AF21

CLKA0AF25

A1

B1

C1

D1PTH

PTH

EMU1BB_30x2V_S1.27mm

A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15

B1B2B3B4B5B6B7B8B9

B10B11B12B13B14B15

D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15

H1

H2

R235 NL/0R287 10

R901 4.75K

R233 1K

R893 4.7K

R903 4.75K

R270 10

R897 4.7K

R226 NL/0

R295 10

R232 NL/0

R895 4.7K

R280 10

R267 10

R904 NL/10K

R269 10

C5360.1uF

16V

R273 10

R268 10

JTAG/EMU/DFT


TI_TMS320C6678

DSP1I

TRSTzP28

TMSP29

TDIP27

TCKN29

TDOR29

RSV03N23

RSV02N24

EMU13AD26

RSV08AH19

RSV09AF19

EMU07AE29

EMU04AD29

EMU00AC29

EMU09AF29EMU08AE28

EMU05AD28

EMU01AC28

EMU10AE27

EMU06AD27

EMU02AC27

EMU14AG28

EMU11AF28

EMU12AG29

EMU15AG27

EMU17AF27

EMU18AH27

EMU03AC26

RSV01AH28

EMU16AJ27

R902 4.75K

R234 0

R290 4.7K

C53710uF

6.3V

R272 10

R294 10

R658 100 1%

R276 10

R281 10

C5510.1uF

16V

R288 10

R286 10

R274 10C5558.2pF50V

R275 10

C55310uF

16V

R292 10

R277 10

R6749.91%

R278 10

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

JP-UART(1-3) & (2-4) : UART over USB Connector (Def ault)JP-UART(3-5) & (4-6) : UART over 3-Pin Header J5

16M SPI NOR Flash

GPIO

Reset Control

Reserved

I2C, TIMER0,1, SPI, UART1M-bit I2C EEPROM

SMD to DIP for PCB space.

0x50h/0x51hSPI1 change to N25Q128A11BSF40F (1410021525)

A103-1

EEPROM_WPDSP_SCLDSP_SDA

DSP_SCLDSP_SDA

DSP_UARTRXD_V1P8DSP_UARTTXD_V1P8

DSP_UARTRXDDSP_UARTTXD

DSP_LRESETNMIENZ

DSP_NMIZDSP_LRESETZ

DSP_CORESEL0DSP_CORESEL1DSP_CORESEL2DSP_CORESEL3

DSP_HOUT

DSP_PORZDSP_RESETFULLZDSP_RESETZ

DSP_PACLKSEL

DSP_UARTRXD

RS232_TXRS232_RX

RS232_RX

RS232_TX

UART_MAX_TXUART_MAX_TX UART_MAX_RX

UART_MAX_TX

UART_MAX_RX

UART_FT_TX UART_FT_RX

DSP_UARTCTSDSP_UARTRXD

DSP_UARTRTSDSP_UARTTXD

DSP_UARTRXD_V1P8

DSP_UARTTXD_V1P8DSP_UARTCTS_V1P8

DSP_UARTRTS_V1P8

DSP_SSPCK

DSP_SSPMOSI

DSP_SSPCS0DSP_SSPCS1

DSP_SSPMISO

DSP_UARTCTS_V1P8DSP_UARTRTS_V1P8

DSP_GPIO_R_00DSP_GPIO_R_01DSP_GPIO_R_02DSP_GPIO_R_03DSP_GPIO_R_04DSP_GPIO_R_05DSP_GPIO_R_06DSP_GPIO_R_07DSP_GPIO_R_08DSP_GPIO_R_09DSP_GPIO_R_10DSP_GPIO_R_11DSP_GPIO_R_12DSP_GPIO_R_13DSP_GPIO_R_14DSP_GPIO_R_15

NOR_HD#DSP_SSPCS0NOR_SSPCK

NOR_WP#DSP_SSPMISODSP_SSPMOSI


DSP_BOOTCOMPLETEDSP_RESETSTAT#

DSP_SSPMISO

DSP_SSPCK

NOR_SSPCKDSP_SSPCK

DSP_GPIO_R_09DSP_GPIO_R_10DSP_GPIO_R_11

DSP_GPIO_R_00

DSP_GPIO_R_12DSP_GPIO_R_13DSP_GPIO_R_14DSP_GPIO_R_15

DSP_GPIO_R_01DSP_GPIO_R_02DSP_GPIO_R_03DSP_GPIO_R_04DSP_GPIO_R_05DSP_GPIO_R_06DSP_GPIO_R_07DSP_GPIO_R_08

VCC1V8

VCC1V8

VCC3V3_AUX

VCC3V3_AUXVCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC1V8

VCC1V8

OUTUART_FT_TX(11,26) IN UART_FT_RX (11,26)

OUTDSP_SCL(10,29)

OUT DSP_HOUT (30)

INDSP_PORZ(30)INDSP_RESETFULLZ(30)INDSP_RESETZ(30)

INDSP_PACLKSEL(30)

INDSP_LRESETNMIENZ(30)INDSP_CORESEL0(30)INDSP_CORESEL1(30)INDSP_CORESEL2(30)INDSP_CORESEL3(30)INDSP_NMIZ(30)INDSP_LRESETZ(30)

BIDSP_SDA(10,29)

IN DSP_UARTCTS (29)IN DSP_UARTRXD (29)

OUT DSP_UARTRTS (29)OUT DSP_UARTTXD (29)

IN DSP_SSPMISO (29,30)

OUT DSP_SSPCS1 (29,30)

OUT DSP_SSPMOSI (29,30)INDSP_TIMI0(29,31)INDSP_TIMI1(29)

OUT DSP_BOOTCOMPLETE (30)OUT DSP_RESETSTAT# (30)

INNOR_WP#(30)

IN EEPROM_WP (30)

BIDSP_GPIO_00(29,31)BIDSP_GPIO_01(29,31)BIDSP_GPIO_02(29,31)BIDSP_GPIO_03(29,31)BIDSP_GPIO_04(29,31)BIDSP_GPIO_05(29,31)BIDSP_GPIO_06(29,31)BIDSP_GPIO_07(29,31)BIDSP_GPIO_08(29,31)BIDSP_GPIO_09(29,31)BIDSP_GPIO_10(29,31)BIDSP_GPIO_11(29,31)BIDSP_GPIO_12(29,31)BIDSP_GPIO_13(29,31)BIDSP_GPIO_14(29,31)BIDSP_GPIO_15(29,31)

OUTDSP_TIMO0(29)OUTDSP_TIMO1(29)

OUT FPGA_SSPCK (30)OUTPH_SSPCK(29)

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_MISC


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_MISC


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_MISC


R949 10

C3670.1uF16V

RESET/BOOT


TI_TMS320C6678

DSP1J

PORzAC20

RESETFULLzN25

RESETzM29

PACLKSELAE4

LRESETNMIENzM27

CORESEL0AF2

CORESEL1AD4

CORESEL2AE6

CORESEL3AE5

NMIzM25

LRESETzN26

RESETSTATzN27

BOOTCOMPLETEAE2

HOUTAD20

R459 4.7K

R202 33

R941 10

R467 4.7K

R1670

R187 4.7K

R944 10

R1650

U249

TI_MAX3221ECPWR

EN1

C1+2

V+3

C1-4

C2+5

C2-6

V-7

RIN8

FORCEOFF16

VCC15

GND14

DOUT13

FORCEON12

DIN11

INVALID10

ROUT9

R340 10

R460 4.7K

R948 10R468 4.7K

C3680.1uF16V

R164NL/0

R342 NL/0

R3294.7K

R163 4.7K

R461 4.7K

COM_SEL1

PH_3x2V_2.54mm

135

246

R1794.7K

R168 4.7K

R469 4.7K

R429NL/0

R341 10

R369 33

COM1

W_3V_2.54mm

21

3

R938 10

R337 10

R947 10

R940 10

U255

TI_SN74ALVC125PWR

1OE1

1A2

1Y3

2OE4

2A5

2Y6

GND7

3Y83A93OE104Y114A124OE13VCC14

R462 4.7K

R347 10

R943 10

R169 4.7K

GPIO


TI_TMS320C6678

DSP1L

GPIO00/LENDIANH25

GPIO13/BOOTMODE12K25

GPIO03/BOOTMODE02J26




GPIO02/BOOTMODE01J29 GPIO01/BOOTMODE00J28


GPIO12/BOOTMODE11L29



GPIO14/PCIESSMODE0K24


GPIO15/PCIESSMODE1L27

GPIO11/BOOTMODE10L28

C155 0.1uF 16V

R953 10

R470 4.7K

R2034.7K

R166 4.7K

C3030.1uF16V

R200 4.7K

R1864.7K

R463 4.7K

R952 10

R428NL/0

R398 10

R471 4.7K

B212200pF

1

2

3

R162 4.7KI2CTIMER0TIMER1 SPI UART


TI_TMS320C6678

DSP1M

SCLAD3

SDAAC4

TIMI0/PCIESSENL24

TIMI1L26

TIMO0L25

TIMO1M26

SPISCS0AG1

SPISCS1AG2

SPICLKAE1

SPIDINAD2

UARTRXDAD1

UARTRTSAB2

UARTCTSAB3

UARTTXDAC1

SPIDOUTAB1

R485 10

C156 0.1uF 16V

R377 10

R363 10

R946 10

R3844.7K

C5221uF6.3V

RESERVED PINS


TI_TMS320C6678

DSP1S

RSV10K22

RSV11J22

RSV12Y5

RSV13W5

R427NL/0

R951 10

R464 4.7K

COM_SEL1(1-3)

MINIJUMPER_2_2.54mm

R368 33

R344 NL/0

R472 4.7K

R378 10R1854.7K

R942 10

R3304.7K

U24TI_SN74AVC4T245PWR

VCCA1

1DIR2

2DIR3

1A14

1A25

2A16

2A27

GND18

GND29 2B2

10 2B111 1B212 1B113 2OE14 1OE15 VCCB16

COM_SEL1(2-4)

MINIJUMPER_2_2.54mm

EEPROM1

<Characteristic>ST_M24M01-HRMN6TP

DU1

E12

E23

VSS4

SDA5SCL6WC7VCC8

R455 4.7K

C154 0.1uF 16V

R939 10

C4720.1uF16V

R465 4.7K

R950 10

R345 NL/0

SPI1

<Characteristic>NUMONYX_N25Q128A11BSF40F

HOLD/DQ31 VCC2

DU/NC13DU/NC24DU/NC35DU/NC46

S7

DQ18

W/Vpp/DQ29

VSS10

DU/NC511DU/NC612DU/NC713DU/NC814

DQ015 SCK16

C3040.1uF16V

R945 10

R458 4.7K

C157 0.1uF 16V

R343 NL/0

R466 4.7K

R188 4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DSP CLOCK

Smart Reflex

“All DC-blocking capacitors to be placed near DSP t o keep connecting routes short and minimize vias”

100.00MHz

312.5MHz

66.667MHz

100.00MHz

100.00MHz

312.5MHz

Layout From Clock DeviceREF_CLK output

(HCSL)

(LVDS)

Add PCIE Clock MUX

All blocking capacitors to be placed near DSP to ke epconnecting routes short and minimize vias

DSP_SYSCLKOUT

DDRCLKPDDRCLKN

PASSCLKPPASSCLKN

SRIOSGMIICLKPSRIOSGMIICLKN

HyperLink_CLKPHyperLink_CLKN

CORECLKP_CCORECLKN_C

DDRCLKN_CDDRCLKP_C

PASSCLKN_CPASSCLKP_C

SRIOSGMIICLKN_CSRIOSGMIICLKP_C

PCIECLKN_CPCIECLKP_C

HyperLink_CLKN_CHyperLink_CLKP_C

DSP_VIDADSP_VIDBDSP_VIDCDSP_VIDS

DSP_VCLDSP_VD

DSP_VIDADSP_VIDBDSP_VIDCDSP_VIDS

UCD9222_VIDBUCD9222_VIDA

UCD9222_VIDCUCD9222_VIDS

DSP_VCL DSP_VCL_1DSP_VD_1DSP_VD

PCI-E_PPCI-E_N

DSP_PCIECLKPDSP_PCIECLKN

DSP_PCIECLKN

DSP_PCIECLKP

FPGA_ICS557_PD#

FPGA_ICS557_OE

DSP_PCIECLKPDSP_PCIECLKN

PCIECLKP_ICS557PCIECLKN_ICS557

PCIECLKP_ICS557

PCIECLKN_ICS557

VID_OE#

VID_OE#

FPGA_ICS557_SEL

VCC3V3_AUXVCC1V8

VCC1V8

VCC3V3_AUXVCC1V8

VCC3V3_AUXVCC1V8

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX_ICS557

VCC3V3_AUX_ICS557

VCC3V3_AUX_ICS557

VCC3V3_AUX

OUT DSP_SYSCLKOUT (30)INCORECLKP(23)INCORECLKN(23)

INPASSCLKP(22)INPASSCLKN(22)

INSRIOSGMIICLKP(22)INSRIOSGMIICLKN(22)

INHyperLink_CLKP(22)INHyperLink_CLKN(22)

OUT UCD9222_VIDA (33)OUT UCD9222_VIDB (33)OUT UCD9222_VIDC (33)OUT UCD9222_VIDS (33)

BI DSP_VD_1 (30)OUT DSP_VCL_1 (30)

INDDRCLKP(23)INDDRCLKN(23)

IN PCA9306_EN (30)

INPCIECLKN(22)INPCIECLKP(22)

INFPGA_ICS557_PD#(30)

INFPGA_ICS557_OE(30)

INFPGA_ICS557_SEL(30)

INPCIE_REF_CLK_N(10)

INPCIE_REF_CLK_P(10)

INVID_OE#(31)

Title


Date: Sheet of


DSPM-8301E A104-1



Title


Date: Sheet of


DSPM-8301E A104-1



Title


Date: Sheet of


DSPM-8301E A104-1



C502 0.1uF 16V

C499 0.1uF 16V

R32510K

R328100K

PLL REFERENCE CLOCKS


TI_TMS320C6678

DSP1H

CORECLKPAG3

CORECLKNAG4

DDRCLKPG29

DDRCLKNH29

PASSCLKPAJ5

PASSCLKNAJ4

SRIOSGMIICLKPAG6

SRIOSGMIICLKNAJ6

PCIECLKPAG5

PCIECLKNAH5

MCMCLKNY2 MCMCLKP

W2

SYSCLKOUTAE3

RSV20AF3

RSV21G25

RSV22AF1

RSV04AH2

RSV05AJ3

RSV06H28

RSV07G28

RSV24AH4

RSV25AH3

RSV14W6

RSV15AE12

RSV16AC9

RSV17AD19

TP12

C500 0.1uF 16V

R4501005%

R4341.2K1%

U1

<Characteristic>IDT_ICS557GI-08LFT

VD

D_1

1

IN12

IN13

PD4

IN25

IN26

OE7

GN

D_1

8

IREF9

VD

D_2

10

VD

D_3

11G

ND

_212

GN

D_3

13

CLK14CLK15

SEL16

R32610K

C521 0.1uF16V

B22

2200pF

1

2

3

C493 0.1uF 16V

C497 0.1uF 16V

R39 33 1%

R358 NL/0

R360 NL/0

R351 NL/0

C494 0.1uF 16V

R426 150 1%

C498 0.1uF 16V

C520 0.1uF16V

R40 475

R476 33

SMART REFLEXCONTROL


TI_TMS320C6678

DSP1G

VCNTL0L23

VCNTL1K23

VCNTL2J23

VCNTL3H23

VCLM24

VDM23

R352 NL/0

R346 NL/0

R359 NL/0

R361 NL/0

U19TI_SN74AVC4T245PWR

VCCA1

1DIR2

2DIR3

1A14

1A25

2A16

2A27

GND18

GND29 2B2

10 2B111 1B212 1B113 2OE14 1OE15 VCCB16

R486 10K

R444 100 5%

C170.01uF16V

C495 0.1uF 16V

R356 NL/0

R128 10K

C180.01uF16V

C496 0.1uF 16VR362 NL/0

R32010K

R475 10K

R130 10K

R357 NL/0

C42110uF6.3V

R32110K

U248TI_PCA9306DCUT

GND1

VREF12

SCL13

SDA14

SDA25SCL26VREF27EN8

C503 0.1uF 16V

R12 0.1uF 16V R425 150 1%

C1750.1uF16V

R354 NL/0

R436 10K

R32210K

R131 10K

C504 0.1uF 16V

C160.01uF16V

R17 0.1uF 16V

R32410K

C52710uF6.3V

R129 10K

R453 NL/10K

C501 0.1uF 16V

R442 10K

R43310K

R349 NL/0

R355 NL/0

R24 33 1%

R32710K

R372 100

R32310K

C1740.1uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.8V

1.5V

Place near to DSP pins



Place near to DSP

Place near to DSP


VCC1V8_AVDD3

VCC1V8_AVDD2

VCC1V8_AVDD1

VCC1V8

VCC1V8

VCC1V8 VCC1V8

VCC1V8

VCC1V5VCC1V5

VCC1V5

VCC1V5

VCC1V8

VCC1V5

VCC1V5

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_POWERA


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_POWERA


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_POWERA


C2060.01uF16V

1.8V I/O SUPPLY

RESERVED PINS

1.8V PLL SUPPLY


TI_TMS320C6678

DSP1D

DVDD18_1AB7

DVDD18_2N28

DVDD18_3P23

DVDD18_4T23

DVDD18_5U26

DVDD18_6V23

DVDD18_7Y7

DVDD18_8Y23

DVDD18_9AB5

DVDD18_10H24

RSV0AAA21

RSV0BAA20

AVDDA1H22

AVDDA2AC6

AVDDA3AD5

DVDD18_11AB19

DVDD18_12AB21

DVDD18_13AB28

DVDD18_14AC3

DVDD18_15AF26

DVDD18_16AG22

DVDD18_17AH1

DVDD18_18AH29

DVDD18_19AJ2

DVDD18_20AJ28

DVDD18_21AA6

DVDD18_22AF5

C210560pF50V

C55810uF6.3V

C211560pF50V

C5650.01uF16V

C189560pF50V

C212560pF50V

C176100uF6.3V

C1820.01uF16V

C2020.1uF16V

C556100uF6.3V

C2030.01uF16V

C5640.01uF16V

C188560pF50V

C186560pF50V

1.5V DDR3I/O SUPPLY


TI_TMS320C6678

DSP1C

DVDD15_1A2

DVDD15_2A11

DVDD15_3A17

DVDD15_4A28

DVDD15_5B1

DVDD15_6B29

DVDD15_7C14

DVDD15_8C25

DVDD15_9D5

DVDD15_10D8

DVDD15_11D20

DVDD15_12D23

DVDD15_13E3

DVDD15_14F5

DVDD15_15F7

DVDD15_16F9

DVDD15_17F11

DVDD15_18F17

DVDD15_19F19

DVDD15_20F26

DVDD15_21F28

DVDD15_22G2

DVDD15_23G4

DVDD15_24G8

DVDD15_25G10

DVDD15_26G12

DVDD15_27G14

DVDD15_28G16

DVDD15_29G18

DVDD15_30G20

DVDD15_31G23

C191560pF50V

C17810uF6.3V

C2190.1uF16V

C2160.1uF16V

C1830.01uF16V

C2014.7uF6.3V

C200100uF6.3V

C1980.01uF16V

C17710uF6.3V

C2050.1uF16V

B32

2200pF

1

2

3

C2170.1uF16V

C2230.01uF16V

C1850.1uF16V

C187560pF50V

C2210.01uF16V

C2250.01uF16V

C193560pF50V

C209560pF50V

C192560pF50V

C5620.1uF16V

C2200.01uF16V

C213560pF50V

C1840.1uF16V

C204560pF50V

B31

2200pF

1

2

3

C5610.1uF16V

C207560pF50V

C2274.7uF6.3V

R364 NL/0

C199560pF50V

C557100uF6.3V

C1961000pF50V

C5630.1uF16V

C1940.1uF16V

C190560pF50V

C2240.01uF16V

C1970.1uF16V

C1794.7uF6.3V

C1801000pF50V

C2220.01uF16V

C2180.1uF16V

C5600.1uF16V

B8

2200pF

1

2

3

R365 NL/0

C208560pF50V

C214560pF50V

C2264.7uF6.3V

C55910uF6.3V

C1811000pF50V

C215560pF50V

C1950.01uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC1V0

0.9V - 1.1V (Smart Reflex)


Place near to DSP






Place near to DSP

CVDD CVDD

CVDD

VCC1V0VCC1V0

VCC1V0

VCC1V0

VCC1V0

VCC1V0

CVDD

CVDD

CVDD

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_POWERB


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_POWERB


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_POWERB


C231560pF50V

C569100uF6.3V

C5790.1uF16V

C26647uF6.3V

C5940.01uF16V

C5720.1uF16V

C236560pF50V

C5840.1uF16V

C2600.1uF16V

C5950.01uF16V

C5800.1uF16V

C239560pF50V

C232560pF50V

C566100uF6.3V

C5740.1uF16V

C2590.1uF16V

C5850.1uF16V

C242560pF50V

C269560pF50V

C235560pF50V

C247560pF50V

C5750.1uF16V

C2630.1uF16V

C2500.01uF16V

C2770.01uF16V

C270560pF50V

C5860.01uF16V

C2520.01uF16V

C268560pF50V

C245560pF50V

C2540.01uF16V

C271560pF50V

C2560.01uF16V

C246560pF50V

C229560pF50V

C2610.1uF16V

C2480.01uF16V

C2490.01uF16V

C2510.01uF16V

C2780.01uF16V

C5870.01uF16V

C2530.01uF16V

C233560pF50V

C241560pF50V

C2550.01uF16V

C567100uF6.3V

C2830.1uF16V

C2570.01uF16V

C272560pF50V

C2620.1uF16V

C2850.1uF16V

C267560pF50V

C3254.7uF6.3V

C2790.01uF16V

C5880.01uF16V

C238560pF50V

C275560pF50V

C273560pF50V

C2580.1uF16V

C2860.1uF16V

C26447uF6.3V

C2800.01uF16V

C243560pF50V

C5890.01uF16V

C274560pF50V

C276560pF50V

C2810.01uF16V

C5900.01uF16V

C5910.01uF16V

C240560pF50V

C568100uF6.3V

C5780.1uF16V

C5960.1uF16V

0.9V - 1.1VSMARTREFLEXCORE SUPPLY


DSP1A

TI_TMS320C6678

CVDD_1H7

CVDD_2H9

CVDD_3H11

CVDD_4H13

CVDD_5H15

CVDD_6H17

CVDD_7H19

CVDD_8H21

CVDD_9J10

CVDD_10J12

CVDD_11J16

CVDD_12J18

CVDD_13J20

CVDD_14K11

CVDD_15K17

CVDD_16K19

CVDD_17K21

CVDD_18L10

CVDD_19L12

CVDD_20L16

CVDD_21L18

CVDD_22M11

CVDD_23M13

CVDD_24M15

CVDD_25M17

CVDD_26M19

CVDD_27N8

CVDD_28N10

CVDD_29N12

CVDD_30N14

CVDD_31N16

CVDD_32N18

CVDD_33P9

CVDD_34P11

CVDD_35P13

CVDD_36P15

CVDD_37P17

CVDD_38P19

CVDD_39P21

CVDD_40R8

CVDD_41R10

CVDD_42R18

CVDD_43R20

CVDD_44R22

CVDD_45T9

CVDD_46T11

CVDD_47T13

CVDD_48T15

CVDD_49T17

CVDD_50T19

CVDD_51T21

CVDD_52U8

CVDD_53U10

CVDD_54U18

CVDD_55U20

CVDD_56U22

CVDD_57V9

CVDD_58V11

CVDD_59V17

CVDD_60V19

CVDD_61V21

CVDD_62W8

CVDD_63W10

CVDD_64W18

CVDD_65W20

CVDD_66W22

CVDD_67Y9

CVDD_68Y11

CVDD_69Y13

CVDD_70Y15

CVDD_71Y17

CVDD_72Y19

CVDD_73Y21

CVDD_74AA8

CVDD_75AA10

CVDD_76AA12

CVDD_77AA14

CVDD_78AA16

CVDD_79AA18

CVDD_80AA22

C228560pF50V

C57110uF6.3V

C5830.1uF16V

C26547uF6.3V

C2820.01uF16V

C5920.01uF16V

C244560pF50V

C5810.1uF16V

C5970.1uF16V

C230560pF50V

C5730.1uF16V

C402100uF6.3V

C57010uF6.3V

C5930.01uF16V

C5770.1uF16V

C2840.1uF16V

1.0V COREMEMORY SUPPLY


TI_TMS320C6678

DSP1B

CVDD1_1J8

CVDD1_2J14

CVDD1_3K7

CVDD1_4K9

CVDD1_5K13

CVDD1_6K15

CVDD1_7L8

CVDD1_8L14

CVDD1_9L20

CVDD1_10L22

CVDD1_11M9

CVDD1_12M21

CVDD1_13N20

CVDD1_14N22

CVDD1_15R12

CVDD1_16R14

CVDD1_17R16

CVDD1_18U12

CVDD1_19U14

CVDD1_20U16

CVDD1_21V13

CVDD1_22V15

CVDD1_23W12

CVDD1_24W14

CVDD1_25W16

C5760.1uF16V

C234560pF50V

C237560pF50V

C404100uF6.3V

C5820.1uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.0V & 1.5V for Serdes


VDDT1 VDDT2

VDDT1VDDT2 VCC1V0VCC1V0

VDDR1

VCC1V5VDDR1VDDR2 VCC1V5

VDDR3 VCC1V5VDDR4 VCC1V5

VDDR2VDDR3

VDDR4

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_POWERC


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_POWERC


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_POWERC


C4820.1uF16V

C2954.7uF6.3V

C4860.1uF16V

C4900.1uF16V

C4831000pF50V

C293560pF50V

C4910.01uF16V

C4871000pF50V

C290560pF50V

C299560pF50V

C2970.01uF16V

C4840.01uF16V

C294560pF50V

C4921000pF50V

C4880.01uF16V

C477560pF50V

C289560pF50V

C298560pF50V

C2960.1uF16V

C2910.1uF16V

C4780.1uF16V

C2870.1uF16V

C2920.01uF16V

B28

2200pF

1

2

3

B30

2200pF

1

2

3

C4790.01uF16V

B29

2200pF

1

2

3

C2880.01uF16V

C4801000pF50V

B10

2200pF

1

2

3B9

2200pF

1

2

3

1.0V SERDES TERMINATION SUPPLY1.5V SERDES REGULATOR SUPPLY


TI_TMS320C6678

DSP1E

VDDT1_1M7

VDDT1_2N6

VDDT1_3P7

VDDT1_4R6

VDDT1_5T7

VDDT1_6U6

VDDT1_7V7

VDDR1V5

VDDT2_1AB9

VDDT2_2AB11

VDDT2_3AB13

VDDT2_4AB15

VDDT2_5AC8

VDDT2_6AC10

VDDT2_7AC12

VDDT2_8AC14

VDDT2_9AC16

VDDT2_10AC18

VDDT2_11AD7

VDDT2_12AD9

VDDT2_13AD11

VDDT2_14AD13

VDDT2_15AD15

VDDT2_16AD17

VDDT2_17AE18

VDDR2AE10

VDDR3AE16

VDDR4AE14

VDDT2_18AB17

C3004.7uF6.3V

B27

2200pF

1

2

3

C481560pF50V

C489560pF50V

C485560pF50V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_GND


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_GND


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_GND


POWER SUPPLY REFERENCE


TI_TMS320C6678

DSP1F

VSS_165V16

VSS_166V18

VSS_167V20

VSS_168V22

VSS_169W7

VSS_170W9

VSS_171W11

VSS_172W13

VSS_173W15

VSS_174W17

VSS_175W19

VSS_176W21

VSS_177Y8

VSS_178Y10

VSS_179Y12

VSS_180Y14

VSS_181Y16

VSS_182Y18

VSS_183Y20

VSS_184Y22

VSS_185AA5

VSS_186AA7

VSS_187AA9

VSS_188AA11

VSS_189AA13

VSS_190AA15

VSS_191AA17

VSS_192AA19

VSS_193AE8

VSS_194AA23

VSS_195AA28

VSS_196AB4

VSS_197AB8

VSS_198AB10

VSS_199AB12

VSS_200AB14

VSS_201AB16

VSS_202AB18

VSS_203AB20

VSS_204AB22

VSS_205AC5

VSS_206AC7

VSS_207AC2

VSS_208AC11

VSS_209AC13

VSS_210AC15

VSS_211AC17

VSS_212AC19

VSS_213AD6

VSS_214AD8

VSS_215AD10

VSS_216AD12

VSS_217AD14

VSS_218AD16

VSS_219AD18

VSS_220AE7

VSS_221AE9

VSS_222AE11

VSS_223AE13

VSS_224AE15

VSS_225AE17

VSS_226AE19

VSS_227AE26

VSS_228AF6

VSS_229AF9

VSS_230AF12

VSS_231AF15

VSS_232AF18

VSS_233AF22

VSS_234AF4

VSS_235AG7

VSS_236AG10

VSS_237AG13

VSS_238AG16

VSS_239AG19

VSS_240AH6

VSS_241AH9

VSS_242AH12

VSS_243AH15

VSS_244AH18

VSS_245AJ1

VSS_246AJ7

VSS_247AJ10

VSS_248AJ13

VSS_249AJ16

VSS_250AJ19

VSS_251AJ29

VS

S_1

A1

VS

S_2

A29

VS

S_3

B11

VS

S_4

B17

VS

S_5

B25

VS

S_6

C8

VS

S_7

C23

VS

S_8

D3

VS

S_9

D14

VS

S_1

0D

18

VS

S_1

1E

5

VS

S_1

2E

20

VS

S_1

3F

6

VS

S_1

4F

8

VS

S_1

5F

10

VS

S_1

6F

12

VS

S_1

7F

16

VS

S_1

8F

18

VS

S_1

9F

27

VS

S_2

0F

29

VS

S_2

1G

1

VS

S_2

2G

3

VS

S_2

3G

5

VS

S_2

4G

6

VS

S_2

5G

7

VS

S_2

6G

9

VS

S_2

7G

11

VS

S_2

8G

13

VS

S_2

9G

15

VS

S_3

0G

17

VS

S_3

1G

19

VS

S_3

2G

21

VS

S_3

3G

24

VS

S_3

4H

1

VS

S_3

5H

2

VS

S_3

6H

3

VS

S_3

7H

4

VS

S_3

8H

5

VS

S_3

9H

6

VS

S_4

0H

8

VS

S_4

1H

10

VS

S_4

2H

12

VS

S_4

3H

14

VS

S_4

4H

16

VS

S_4

5H

18

VS

S_4

6H

20

VS

S_4

7J1

VS

S_4

8J2

VS

S_4

9J3

VS

S_5

0J4

VS

S_5

1J5

VS

S_5

2J6

VS

S_5

3J7

VS

S_5

4J9

VS

S_5

5J1

1

VS

S_5

6J1

3

VS

S_5

7J1

5

VS

S_5

8J1

7

VS

S_5

9J1

9

VS

S_6

0J2

1

VS

S_6

1K

1

VS

S_6

2K

2

VS

S_6

3K

3

VS

S_6

4K

4

VS

S_6

5K

5

VS

S_6

6K

6

VS

S_6

7K

8

VS

S_6

8K

10

VS

S_6

9K

12

VS

S_7

0K

14

VS

S_7

1K

16

VS

S_7

2K

18

VS

S_7

3K

20

VS

S_7

4Y

6

VS

S_7

5L1

VS

S_7

6L2

VS

S_7

7L3

VS

S_7

8L4

VS

S_7

9L5

VS

S_8

0L6

VS

S_8

1L7

VS

S_8

2L9

VS

S_8

3L1

1

VS

S_8

4L1

3

VS

S_8

5L1

5

VS

S_8

6L1

7

VS

S_8

7L1

9

VS

S_8

8L2

1

VS

S_8

9M

2

VS

S_9

0M

3

VS

S_9

1M

4

VS

S_9

2M

6

VS

S_9

3M

8

VS

S_9

4M

10

VS

S_9

5M

12

VS

S_9

6M

14

VS

S_9

7M

16

VS

S_9

8M

18

VS

S_9

9M

20

VS

S_1

00M

22

VS

S_1

01M

28

VS

S_1

02N

3

VS

S_1

03N

7

VS

S_1

04N

9

VS

S_1

05N

11

VS

S_1

06N

13

VS

S_1

07N

15

VS

S_1

08N

17

VS

S_1

09N

19

VS

S_1

10N

21

VS

S_1

11P

1

VS

S_1

12P

3

VS

S_1

13P

5

VS

S_1

14P

6

VS

S_1

15P

8

VS

S_1

16P

10

VS

S_1

17P

12

VS

S_1

18P

14

VS

S_1

19P

16

VS

S_1

20P

18

VS

S_1

21P

20

VS

S_1

22P

22

VS

S_1

23R

2

VS

S_1

24R

3

VS

S_1

25R

4

VS

S_1

26R

7

VS

S_1

27R

9

VS

S_1

28R

11

VS

S_1

29R

13

VS

S_1

30R

15

VS

S_1

31R

17

VS

S_1

32R

19

VS

S_1

33R

21

VS

S_1

34T

3

VS

S_1

35T

6

VS

S_1

36T

8

VS

S_1

37T

10

VS

S_1

38T

12

VS

S_1

39T

14

VS

S_1

40T

16

VS

S_1

41T

18

VS

S_1

42T

20

VS

S_1

43T

22

VS

S_1

44T

26

VS

S_1

45U

1

VS

S_1

46U

3

VS

S_1

47U

5

VS

S_1

48U

7

VS

S_1

49U

9

VS

S_1

50U

11

VS

S_1

51U

13

VS

S_1

52U

15

VS

S_1

53U

17

VS

S_1

54U

19

VS

S_1

55U

21

VS

S_1

56V

1

VS

S_1

57V

2

VS

S_1

58V

3

VS

S_1

59V

4

VS

S_1

60V

6

VS

S_1

61V

8

VS

S_1

62V

10

VS

S_1

63V

12

VS

S_1

64V

14

VSS_252AB6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLOCK GEN3

312.5MHz

100.00MHz

312.5MHz

100.00MHz

A103-1

A103-1

CLOCK3_SSPSO

CLOCK3_SSPCS1CLOCK3_SSPCKCLOCK3_SSPSI

SRIOSGMIICLKPSRIOSGMIICLKN

HyperLink_CLKN

PASSCLKPPASSCLKNREFCLK3_PD#

CLOCK3_PLL_LOCK

PCIECLKNPCIECLKP

HyperLink_CLKPHyperLink_CLKP

VCC3V3_AUX

VCC3V3_AUX

VCCPLLA3A

VCC3V3_AUX VCC_VCO3A

VCCPLLA3A

VCC3V3_AUX VCC_VCO3B

VCC3V3_AUX

VCC_VCO3A

VCC3V3_AUX

VCCPLLA3B

VCC_VCO3B

VCCPLLA3C

VCCPLLA3B

VCCPLLA3CVCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUXINREFCLK3_PD#(31)

INCLOCK3_SSPCS1(31)INCLOCK3_SSPCK(31)INCLOCK3_SSPSI(31)

OUTCLOCK3_SSPSO(31)

OUT HyperLink_CLKP (17)OUT HyperLink_CLKN (17)

OUT SRIOSGMIICLKP (17)OUT SRIOSGMIICLKN (17)

OUT PASSCLKP (17)OUT PASSCLKN (17)

OUT CLOCK3_PLL_LOCK (31)

OUT PCIECLKN (17)OUT PCIECLKP (17)

INREFCK_N(23)INREFCK_P(23)

Title


Date: Sheet of


DSPM-8301E A104-1

DSP_CLOCK_GEN3


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_CLOCK_GEN3


Title


Date: Sheet of


DSPM-8301E A104-1

DSP_CLOCK_GEN3


C361 1uF 6.3V

TP43

R176 10KC3570.1uF16V

C3470.1uF16V

C3490.1uF16V

B20

2200pF

1

2

3

C3390.1uF16V

C3590.1uF16V

B18

2200pF

1

2

3

C3641uF6.3V

C3601uF6.3V

B19

2200pF

1

2

3

C362 1uF 6.3V

C3630.1uF16V

C356 0.1uF 16V

C3380.1uF16V

R177 1K

B17

2200pF

1

2

3

TP41

C354 0.1uF 16V

TP40

C3410.1uF16V

CLK3

TI_CDCE62005RGZT

<Characteristic>

AUXIN43AUXOUT13

EP

AD

49

EXT_LFN41 EXT_LFP40

GN

D_V

CO

36

PLL_LOCK37

Power_Down12

PRIREF-46 PRIREF+45

REF_SEL31

REG_CAP14

REG_CAP238

SECREF-2 SECREF+3

SPI_CLK24 SPI_LE25

SPI_MISO22 SPI_MOSI23

SYNC14

TEST_MODE33

TESTOUTA30

The

rmal

_VIA

150

The

rmal

_VIA

251

The

rmal

_VIA

2069

The

rmal

_VIA

2170

The

rmal

_VIA

2271

U0N28U0P27

U1N20U1P19

U2N17U2P16

U3N10U3P9

U4N7U4P6

VB

B48

VC

C_A

UX

IN44

VC

C_A

UX

OU

T15

VC

C_I

N_P

RI

47

VC

C_I

N_S

EC

1

VC

C_O

UT

18

VC

C_O

UT

211

VC

C_O

UT

318

VC

C_O

UT

421

VC

C_O

UT

526

VC

C_O

UT

629

VC

C_O

UT

732

VC

C_V

CO

134

VC

C_V

CO

235

VC

C1_

PLL

15

VC

C1_

PLL

239

VC

C1_

PLL

342

The

rmal

_VIA

1059

The

rmal

_VIA

1160

The

rmal

_VIA

1261

The

rmal

_VIA

1362

The

rmal

_VIA

1463

The

rmal

_VIA

1564

The

rmal

_VIA

1665

The

rmal

_VIA

1766

The

rmal

_VIA

1867

The

rmal

_VIA

1968

The

rmal

_VIA

352

The

rmal

_VIA

453

The

rmal

_VIA

554

The

rmal

_VIA

655

The

rmal

_VIA

756

The

rmal

_VIA

857

The

rmal

_VIA

958

The

rmal

_VIA

2372

The

rmal

_VIA

2473

The

rmal

_VIA

2574

C3400.1uF16VC348 1uF 6.3V

C3521uF6.3V

C3430.1uF16V

C3460.1uF16V

C3420.1uF16V

B16

2200pF

1

2

3

C3581uF6.3V

C3440.1uF16V

C3510.1uF16V

R174 10K

C3450.1uF16V

R367 10K

C3370.1uF16V

TP42

C3501uF6.3V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLOCK GEN2

100.00MHz

66.667MHz

100.00MHz

A103-1

A103-1

A103-1

Those caps should be locatednear the CDCE62005

Those caps should be locatednear the CDCE62005(CLK2)

CLOCK2_PLL_LOCK

CLOCK2_SSPSO

CLOCK2_SSPCS1CLOCK2_SSPCKCLOCK2_SSPSI

REFCLK2_XTALIN

CORECLKPCORECLKN

DDRCLKPDDRCLKN

REFCK_PREFCK_N

REFCLK2_PD#

TDM_CLKB_PTDM_CLKB_N

TCKB_PRIREF-TCKB_PRIREF+

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCCPLLA2A

VCC3V3_AUX VCC_VCO2A

VCCPLLA2A

VCC3V3_AUX VCC_VCO2B

VCC3V3_AUX

VCC_VCO2A

VCC3V3_AUX

VCCPLLA2B

VCC_VCO2B

VCCPLLA2C

VCCPLLA2B

VCCPLLA2CVCC3V3_AUX

VCC3V3_AUX

INREFCLK2_PD#(31)

OUTCLOCK2_SSPSO(31)

INCLOCK2_SSPCK(31)INCLOCK2_SSPSI(31)

INCLOCK2_SSPCS1(31)

OUT CORECLKP (17)OUT CORECLKN (17)

OUT DDRCLKP (17)OUT DDRCLKN (17)

OUT REFCK_P (22)OUT REFCK_N (22)

OUT CLOCK2_PLL_LOCK (31)

OUT TDM_CLKB_P_R (30)OUT TDM_CLKB_N_R (30)

INTDM_CLKB_P(10)INTDM_CLKB_N(10)

Title


Date: Sheet of


DSPM-8301E A104-1

CLOCK GEN2


Title


Date: Sheet of


DSPM-8301E A104-1

CLOCK GEN2


Title


Date: Sheet of


DSPM-8301E A104-1

CLOCK GEN2


C3160.1uF16V

C3100.1uF16V

C598 NL/0.1uF 16V

C3361uF6.3V

C3180.1uF16V

Y525MHz_20pF

CLK2

TI_CDCE62005RGZT

AUXIN43AUXOUT13

EP

AD

49

EXT_LFN41 EXT_LFP40

GN

D_V

CO

36

PLL_LOCK37

Power_Down12

PRIREF-46 PRIREF+45

REF_SEL31

REG_CAP14

REG_CAP238

SECREF-2 SECREF+3

SPI_CLK24 SPI_LE25

SPI_MISO22 SPI_MOSI23

SYNC14

TEST_MODE33

TESTOUTA30

The

rmal

_VIA

150

The

rmal

_VIA

251

The

rmal

_VIA

2069

The

rmal

_VIA

2170

The

rmal

_VIA

2271

U0N28U0P27

U1N20U1P19

U2N17U2P16

U3N10U3P9

U4N7U4P6

VB

B48

VC

C_A

UX

IN44

VC

C_A

UX

OU

T15

VC

C_I

N_P

RI

47

VC

C_I

N_S

EC

1

VC

C_O

UT

18

VC

C_O

UT

211

VC

C_O

UT

318

VC

C_O

UT

421

VC

C_O

UT

526

VC

C_O

UT

629

VC

C_O

UT

732

VC

C_V

CO

134

VC

C_V

CO

235

VC

C1_

PLL

15

VC

C1_

PLL

239

VC

C1_

PLL

342

The

rmal

_VIA

1059

The

rmal

_VIA

1160

The

rmal

_VIA

1261

The

rmal

_VIA

1362

The

rmal

_VIA

1463

The

rmal

_VIA

1564

The

rmal

_VIA

1665

The

rmal

_VIA

1766

The

rmal

_VIA

1867

The

rmal

_VIA

1968

The

rmal

_VIA

352

The

rmal

_VIA

453

The

rmal

_VIA

554

The

rmal

_VIA

655

The

rmal

_VIA

756

The

rmal

_VIA

857

The

rmal

_VIA

958

The

rmal

_VIA

2372

The

rmal

_VIA

2473

The

rmal

_VIA

2574

R172 1K

C3350.1uF16V

C334 1uF 6.3V

C3170.1uF16V

C3310.1uF16V

C605 0.1uF 16V

B15

2200pF

1

2

3

C3090.1uF16V

B14

2200pF

1

2

3

TP32

C3321uF6.3V

C604 NL/0.1uF 16V

C3110.1uF16VC320 1uF 6.3V

C3190.1uF16V

B13

2200pF

1

2

3

TP33

TP29

C3241uF6.3V

C606 0.1uF 16V

C366 NL/47pF

50V

R170 NL/10K

C3120.1uF16V

B12

2200pF

1

2

3

C3301uF6.3V

C3140.1uF16V

C3221uF6.3V

B11

2200pF

1

2

3TP36

C3230.1uF16V

R173 10K

C3130.1uF16V

TP37

C3290.1uF16V

C3210.1uF16V

C333 1uF 6.3V

R366 10K

C3150.1uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Trace need 20 mil.

Trace need 20 mil.

Trace need 20 mil.

Trace need 20 mil.

* Data bits can be swapped withinthe byte lane to ease routing.* Address/Command/Control/Clockrouting must be Fly-By in byte order0, 1, 2, 3 ECC, 4, 5, 6, 7.

DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12

DSP0_DDR3_EDQ15

DSP0_DDR3_EDQ8DSP0_DDR3_EDQ9DSP0_DDR3_EDQ10DSP0_DDR3_EDQ11DSP0_DDR3_EDQ12DSP0_DDR3_EDQ13DSP0_DDR3_EDQ14

DSP_VREFSSTL

DSP0_DDR3_EDQ30DSP0_DDR3_EDQ31

DSP0_DDR3_EDQ24DSP0_DDR3_EDQ25DSP0_DDR3_EDQ26DSP0_DDR3_EDQ27DSP0_DDR3_EDQ28DSP0_DDR3_EDQ29



DSP0_DDR3_EDQ0DSP0_DDR3_EDQ1DSP0_DDR3_EDQ2DSP0_DDR3_EDQ3DSP0_DDR3_EDQ4DSP0_DDR3_EDQ5DSP0_DDR3_EDQ6DSP0_DDR3_EDQ7

DSP0_DDR3_EODT_0

DSP0_DDR3_EBA_0DSP0_DDR3_EBA_1DSP0_DDR3_EBA_2


DSP0_DDR3_EMRESETN

DSP0_DDR3_EWE#DSP0_DDR3_ECAS#DSP0_DDR3_ERAS#DSP0_DDR3_ECS_0#

DSP0_DDR3_ECKP_0DSP0_DDR3_ECKN_0DSP0_DDR3_ECKE_0


DSP0_DDR3_EDM_0DSP0_DDR3_EDM_1


DSP0_DDR3_EODT_0





DSP0_DDR3_EMRESETN


DSP_VREFSSTL

DSP0_DDR3_EDQ47

DSP0_DDR3_EDQ40DSP0_DDR3_EDQ41DSP0_DDR3_EDQ42DSP0_DDR3_EDQ43DSP0_DDR3_EDQ44DSP0_DDR3_EDQ45DSP0_DDR3_EDQ46

DSP_VREFSSTL




DSP_VREFSSTL


DSP0_DDR3_EDQ32DSP0_DDR3_EDQ33DSP0_DDR3_EDQ34DSP0_DDR3_EDQ35DSP0_DDR3_EDQ36DSP0_DDR3_EDQ37DSP0_DDR3_EDQ38DSP0_DDR3_EDQ39

DSP0_DDR3_EODT_0



DSP0_DDR3_EMRESETN






DSP0_DDR3_EODT_0


DSP0_DDR3_ECKP_0DSP0_DDR3_ECKN_0




DSP0_DDR3_EMRESETN

DSP0_DDR3_ECKE_0

DSP0_DDR3_EA15


DSP0_DDR3_EA15


DSP0_DDR3_EA15


DSP0_DDR3_EA15

DSP0_DDR3_EA13

DSP0_DDR3_EA14

DSP0_DDR3_EA13

DSP0_DDR3_EA13DSP0_DDR3_EA13

DSP0_DDR3_EA14


VCC1V5

VCC1V5

VCC1V5

VCC1V5

BI DSP0_DDR3_EDQ[8..15] (13)

BI DSP0_DDR3_EDQ[24..31] (13)

BI DSP0_DDR3_EDQ[0..7] (13)

BI DSP0_DDR3_EDQ[16..23] (13)

INDSP0_DDR3_EODT_0(13,24,25)

INDSP0_DDR3_EBA_0(13,24,25)INDSP0_DDR3_EBA_1(13,24,25)INDSP0_DDR3_EBA_2(13,24,25)

INDSP0_DDR3_EDQSP_1(13)INDSP0_DDR3_EDQSN_1(13)

INDSP0_DDR3_EMRESETN(13,24,25)

INDSP0_DDR3_EWE#(13,24,25)INDSP0_DDR3_ECAS#(13,24,25)INDSP0_DDR3_ERAS#(13,24,25)INDSP0_DDR3_ECS_0#(13,24,25)

INDSP0_DDR3_ECKP_0(13,24,25)INDSP0_DDR3_ECKN_0(13,24,25)INDSP0_DDR3_ECKE_0(13,24,25)


INDSP0_DDR3_EDM_1(13)INDSP0_DDR3_EDM_0(13)






INDSP0_DDR3_ERAS#(13,24,25)INDSP0_DDR3_ECS_0#(13,24,25)

INDSP0_DDR3_EWE#(13,24,25)INDSP0_DDR3_ECAS#(13,24,25)



IN DSP_VREFSSTL (13,24,25)

INDSP0_DDR3_EA[0..15](13,24,25)

BI DSP0_DDR3_EDQ[40..47] (13)

BI DSP0_DDR3_EDQ[56..63] (13)

BI DSP0_DDR3_EDQ[32..39] (13)

BI DSP0_DDR3_EDQ[48..55] (13)





INDSP0_DDR3_EWE#(13,24,25)INDSP0_DDR3_ECAS#(13,24,25)INDSP0_DDR3_ERAS#(13,24,25)INDSP0_DDR3_ECS_0#(13,24,25)







INDSP0_DDR3_ECKP_0(13,24,25)INDSP0_DDR3_ECKN_0(13,24,25)



INDSP0_DDR3_ERAS#(13,24,25)INDSP0_DDR3_ECS_0#(13,24,25)

INDSP0_DDR3_EWE#(13,24,25)INDSP0_DDR3_ECAS#(13,24,25)


INDSP0_DDR3_ECKE_0(13,24,25)

IN DSP_VREFSSTL (13,24,25)

INDSP0_DDR3_EA[0..15](13,24,25)

INDSP0_DDR3_EA[0..15](13,24,25)

INDSP0_DDR3_EA[0..15](13,24,25)

INDSP0_DDR3_EA[0..15](13,24,25)

INDSP0_DDR3_EA[0..15](13,24,25)

INDSP0_DDR3_EA[0..15](13,24,25)

INDSP0_DDR3_EA[0..15](13,24,25)

Title


Date: Sheet of


DSPM-8301E A104-1

DDR3


Title


Date: Sheet of


DSPM-8301E A104-1

DDR3


Title


Date: Sheet of


DSPM-8301E A104-1

DDR3


C1000.1uF16V

C1040.1uF16V

C850.1uF16V

C5622uF6.3V

C900.1uF16V

C7022uF6.3V

C860.1uF16V

C510.1uF16V

C1050.1uF16V

C650.1uF16V

C8722uF6.3V

C550.1uF16V

C670.1uF16V

C10122uF6.3V

R133 2401%

C530.1uF16V

C162 0.1uF 16V

U17

SAMSUNG_K4B2G1646C-HCH9

VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

C163 0.1uF16V

C690.1uF16V

C1020.1uF16V

C520.1uF16V

U4


VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

U16


VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

C880.1uF16V

C660.1uF16V

R76 2401%

U5


VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

C540.1uF16V

R132 2401%

C680.1uF16V

R73 2401%

C1030.1uF16V

C328 0.1uF16V

C890.1uF16V

C353 0.1uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Trace need 20 mil.

1024MB: (2Gb, X16) 4pcs & (1Gb X8, ECC) 1pcs

CO-LAYOUTU4, U5, U16, U17, U8 change SAMSUNG_K4B2G1646C-HCH9

DSP_VREFSSTL

DSP0_DDR3_ECC0DSP0_DDR3_ECC1DSP0_DDR3_ECC2DSP0_DDR3_ECC3

DSP0_DDR3_ECC6DSP0_DDR3_ECC7


DSP0_DDR3_EODT_0

ECC_ZQ

DSP0_DDR3_EMRESETN



DSP0_DDR3_EDM_8


DSP0_DDR3_EA15



ECC_NU

DSP0_DDR3_EA0DSP0_DDR3_EA1DSP0_DDR3_EA2DSP0_DDR3_EA3DSP0_DDR3_EA4DSP0_DDR3_EA5DSP0_DDR3_EA6DSP0_DDR3_EA7DSP0_DDR3_EA8DSP0_DDR3_EA9DSP0_DDR3_EA10DSP0_DDR3_EA11DSP0_DDR3_EA12DSP0_DDR3_EA13





DSP0_DDR3_EODT_0

DSP0_DDR3_EMRESETN

ECC_ZQ






DSP_VREFSSTL

DSP0_DDR3_EDM_8ECC_NU

DSP0_DDR3_EA13

DSP0_DDR3_EA14

VCC1V5

VCC1V5

VCC1V5

BI DSP0_DDR3_ECC[0..7] (13)

IN DSP_VREFSSTL (13,24)

INDSP0_DDR3_EODT_0(13,24)

INDSP0_DDR3_EMRESETN(13,24)

INDSP0_DDR3_ECKP_0(13,24)INDSP0_DDR3_ECKN_0(13,24)INDSP0_DDR3_ECKE_0(13,24)


INDSP0_DDR3_EDM_8(13)

INDSP0_DDR3_EA[0..15](13,24,25)

INDSP0_DDR3_EA[0..15](13,24,25)

INDSP0_DDR3_EBA_0(13,24)INDSP0_DDR3_EBA_1(13,24)INDSP0_DDR3_EBA_2(13,24)

INDSP0_DDR3_EWE#(13,24)INDSP0_DDR3_ECAS#(13,24)INDSP0_DDR3_ERAS#(13,24)INDSP0_DDR3_ECS_0#(13,24)

Title


Date: Sheet of


DSPM-8301E A104-1

DDR3_ECC


Title


Date: Sheet of


DSPM-8301E A104-1

DDR3_ECC


Title


Date: Sheet of


DSPM-8301E A104-1

DDR3_ECC


R379 4.7K

C1110.1uF16V

R87 2401%

R381 4.7K

C1070.1uF16V

R382 4.7K

C1090.1uF16V

R383 4.7K

R353 4.7KR348 4.7K

C113 0.1uF16V

R387 4.7K

C1080.1uF16V

NL/U6

NL/SAMSUNG_K4B2G1646C-HCH9

VDD_1B2

VDD_2D9

VDD_3G7

VDD_4K2

VDD_5K8

VDD_6N1

VDD_7N9

VDD_8R1

VDD_9R9

VDDQ_1A1

VDDQ_2A8

VDDQ_3C1

VDDQ_4C9

VDDQ_5D2

VDDQ_6E9

VDDQ_7F1

VDDQ_8H2

VDDQ_9H9

VREFCAM8

VREFDQH1

DQL0E3

DQL1F7

DQL2F2

DQL3F8

DQL4H3

DQL5H8

DQL6G2

DQL7H7

DQU0D7

DQU1C3

DQU2C8

DQU3C2

DQU4A7

DQU5A2

DQU6B8

DQU7A3

VSS_1A9

VSS_2B3

VSS_4G8

VSS_5J2

VSS_6J8

VSS_7M1

VSS_8M9

VSS_9P1

VSS_10P9

VSS_11T1

VSS_12T9

VSSQ_1B1

VSSQ_2B9

VSSQ_3D1

VSSQ_4D8

VSS_3E1

VSSQ_5E2

VSSQ_6E8

VSSQ_7F9

VSSQ_8G1

VSSQ_9G9

A0N3

A1P7

A2P3

A3N2

A4P8

A5P2

A6R8

A7R2

A8T8

A9R3

A10/APL7

A11R7

A12/BCN7

BA0M2

BA1N8

BA2M3

WEL3

CASK3

RASJ3

CSL2

DQSLF3

DQSLG3

DQSUC7

DQSUB7

DMLE7

DMUD3

CKJ7

CKK7

CKEK9

ODTK1

RESETT2

ZQL8

NC_1J1

NC_2J9

NC_3L1

NC_4L9

NC_5M7

A13T3

NC_6T7

R390 4.7K

U256

NL/SAMSUNG_K4B1G0846E-HCH9

A0K3

A1L7

A2L3

A3K2

A4L8

A5L2

A6M8

A7M2

A8N8

A9M3

A10/APH7

A11M7

A12/BCK7

BA0J2

BA1K8

BA2J3

WEH3

CASG3

RASF3

CSH2

DQSC3

DQSD3

DM/TDQSB7

NU/TDOSA7

CKF7

CKG7

CKEG9

ODTG1

RESETN2

ZQH8

NC0A3

NC1F1

NC2F9

NC3H1

NC4H9

NC5J7

A13N3

VDD0A2

VDD1A9

VDD2D7

VDD3G2

VDD4G8

VDD5K1

VDD6K9

VDD7M1

VDD8M9

VDDQ1B9

VDDQ2C1

VDDQ3E2

VDDQ4E9

VREFCAJ8

VREFDQE1

DQ0B3

DQ1C7

DQ2C2

DQ3C8

DQ4E3

DQ5E8

DQ6D2

DQ7E7

VSS0A1

VSS1A8

VSS2B1

VSS3D8

VSS4F2

VSS5F8

VSS6J1

VSS7J9

VSS8L1

VSS9L9

VSS10N1

VSS11N9

VSSQ1B2

VSSQ2B8

VSSQ3C9

VSSQ4D1

VSSQ5D9

NC6N7

C1100.1uF16V

R388 4.7K

R389 4.7K

C11222uF6.3V

R380 4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FOR EMI

90 OHM DIFF. IMPEDANCE CONTROL

Switch for JTAG emulationEXT_EMU_DET = 0 --> External / Mezzanine EmulatorEXT_EMU_DET = 1 --> On board emulation

3.3V control

3.3VSignal

3.3V Signal

Switch for JTAG emulationFT2232HL_RESET# = 0 --> AMCFT2232HL_RESET# = 1 --> Mini USB

A103-1

USB_DP

USB_DM

VPHYVPLL

VPLL

VPHY

FT_TDK_RFT_TDI_RFT_TDO_RFT_TMS_RFT_TRST#_RGPIOL1GPIOL2GPIOL3

FT_EMU0

FT_EMU1

UART_FT_RXUART_FT_TX

1V8_TRST#

1V8_TDO

1V8_TCK1V8_TDI

1V8_TMS

1V8_EMU_011V8_EMU_00

FT2232HL_RESET#

1V8_TRST#

1V8_TDO

1V8_TCK

1V8_TMS

1V8_TDI


FT2232HL_RESET#

AMC_JTAG_TDIAMC_JTAG_TCK

AMC_JTAG_TMSAMC_JTAG_TDO

AMC_JTAG_RST#

FT_TDKFT_TDIFT_TDOFT_TMSFT_TRST#

FT_TRST#

FT_TDOFT_TMS

FT_TDI

FT_EMU0FT_EMU1

FT_TDK

3V3_TMS

3V3_TDI3V3_TCK

3V3_TDO

3V3_TRST#


3V3_TMS

3V3_TDI3V3_TCK

3V3_TDO

3V3_TRST#


VCC5_VBUS

VCC5_VBUS

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUXVCC1V8_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC1V8_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC1V8

VCC3V3_AUX

VCC3V3_AUX

GND_USB(26)

GND_USB(26)

GND_USB(26)

OUT UART_FT_RX (11,16)IN UART_FT_TX (11,16)

INEMU_TCK(15)INEMU_TDI(15)

INEMU_TMS(15)INEMU_TRST#(15)

IN DSP_TDO (15)OUTEMU_TDO(15)OUT DSP_TDI (15)

OUT DSP_TMS (15)OUT DSP_TRST# (15)

OUT DSP_TCK (15)

INEXT_EMU_DET0(15)

BI DSP_EMU_00 (15)BI DSP_EMU_01 (15)

BIEMU_EMU_00(15)BIEMU_EMU_01(15)

INAMC_JTAG_TDI(10)

INAMC_JTAG_TMS(10)

INAMC_JTAG_TCK(10)

OUTAMC_JTAG_TDO(10)

INAMC_JTAG_RST#(10)

GND_USB(26)

Title


Date: Sheet of


DSPM-8301E A104-1

USB-JTAG


Title


Date: Sheet of


DSPM-8301E A104-1

USB-JTAG


Title


Date: Sheet of


DSPM-8301E A104-1

USB-JTAG


Y212MHz_20pF

C1330.1uF16V

U254

TI_TS3L301DGG

3B238

3B141

SEL24

GND818

2B239

2B142

GND716GND17

46GND6

13

A723

GND511

GND1643

A621A517

GND1540

A415A310

1B244

A281B1

47A1

4A02

VDD536

GND49GND37GND25

0B245

0B148

GND13

GND1437

GND1333

7B225

GND1230

7B128

VDD26

6B226

6B129

VDD11

5B231

5B134

GND1127

NC14

GND1022GND920

VDD419

4B232

4B135

VDD312

C1270.1uF16V

C1240.1uF16V

U9

FTDI_FT2232HL

ADBUS016

AG

ND

10

BCBUS759

VP

HY

4

VP

LL9

VREGIN50

VREGOUT49 ADBUS1

17

ADBUS218

ADBUS319

ADBUS421

ADBUS522

ADBUS623

ADBUS724

ACBUS026

ACBUS127

ACBUS228

ACBUS329

ACBUS430

ACBUS532

ACBUS633

ACBUS734

GN

D_1

1

GN

D_2

5

GN

D_3

11

GN

D_4

15

GN

D_5

25

GN

D_6

35

GN

D_7

47

GN

D_8

51

VC

CIO

_120

VC

CIO

_231

VC

CIO

_342

VC

CIO

_456

VC

OR

E_1

12

VC

OR

E_2

37

VC

OR

E_3

64

BCBUS048

BCBUS152

BCBUS253

BCBUS354

BCBUS455

BCBUS557

BCBUS658

DM7

DP8

EECLK62

EECS63

EEDATA61

OSCI2

OSCO3

PWREN60

RESET14

REF6

SUSPEND36

TEST13

BDBUS038

BDBUS139

BDBUS240

BDBUS341

BDBUS443

BDBUS544

BDBUS645

BDBUS746

U11BTI_SN74LVC00APWR

4

56

C1230.1uF16V

U10

TI_TXS0108EPWR

A11V

CC

A2

A23

A34

A45

A56

A67

A78

A89

OE10

B120 V

CC

B19

B218

B317

B416

B515

B614

B713

B812

GN

D11

C130 33pF50V

Mini-B

USB1

MINIUSB_5H<Characteristic>

+5V1

DATA-2

DATA+3

GND_14

GND_25

PT

H1

H1

PT

H2

H2

PT

H3

H3

PT

H4

H4

U11CTI_SN74LVC00APWR

9

108 R101 22

C1340.1uF16V

D5PGB1010603

TP10

R9564.7K

U259

TI_TS3L301DGG

3B238

3B141

SEL24

GND818

2B239

2B142

GND716GND17

46GND6

13

A723

GND511

GND1643

A621A517

GND1540

A415A310

1B244

A281B1

47A1

4A02

VDD536

GND49GND37GND25

0B245

0B148

GND13

GND1437

GND1333

7B225

GND1230

7B128

VDD26

6B226

6B129

VDD11

5B231

5B134

GND1127

NC14

GND1022GND920

VDD419

4B232

4B135

VDD312

C135 0.1uF

16V

R94 12.1K 1%

C1170.1uF16V

U12ATMEL_AT93C46DN-SH-T

CS1

SK2

DI3

DO4

GND5 ORG6 NC7 VCC8

B4120_100MHz

R102 2.2K

R1370

C1250.1uF16V

C1180.1uF16V

R1711K

C1610.1uF16V

TP11

C1210.1uF16V

R908 4.75K 1%

R93 22

C1190.1uF16V

C1200.1uF16V

D4PGB1010603

R964.7K

R909 4.75K 1%

R92 22

R138 10K

C60110uF6.3V

R103 10K

C1150.01uF16V

C131 33pF50V

C129 0.1uF16V

R984.7K

R91 22

U11DTI_SN74LVC00APWR

12

1311

R974.7K

R95 4.7K

B6120_100MHz

R89 22

R955 4.7K

R204 4.7K

C3650.1uF16V

B5120_100MHz

R100 22

C1320.1uF16V

U11ATI_SN74LVC00APWR

1

23

147

C1160.1uF16V

R88 22

C1220.1uF16V

R104 4.7K

C39610uF6.3V

C1260.01uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PHY Strap Options: see below

001

000

111

110

100

011

Bit[1] Bit[0]

PHYADR[1]PHYADR[4]ANEG[2]ENA_XCHWCFG_MODE[1]DIS_SLEEPINT_POL

PHYADR[0]PHYADR[3]ANEG[1]DIS_125HWCFG_MODE[0]HWCFG_MODE[3]75/50 OHM

88E1111 Device Pin to Configuration Bit Mapping

Pin

CONFIG0CONFIG1CONFIG2CONFIG3CONFIG4CONFIG5CONFIG6

PHYADR[2]ENA_PAUSEANEG[3]ANEG[0]HWCFG_MODE[2]DIS_FCSEL_TWSI

Bit[2]

Pin to Constant Mapping

Pin Bit[2:0]

VDDOLED_LINK10LED_LINK100LED_LINK1000LED_DUPLEXLED_RXLED_TXVSS

111110101100011010001000

PHY ConfigurationHardwareConfigurationBit Setting

PHY Address bit[2:0] 001

Enable Pause ,PHY Address bit[4:3] = 00

Auto-Neg advertise all capabilities ,prefer Master

CONFIG Pin Connection

Enable MDI crossover, disable 125CLK

Pin

CONFIG0CONFIG1CONFIG2CONFIG3CONFIG4CONFIG5CONFIG6

001100111011

SGMII without Clock with SGMII Auto-Neg to copper

Disable fiber /copper Auto-detect, Disable sleep

Select MDIO interface, INT signal active high, 50 o hm SERDES

LED PinConnection

PHY Address = 0x01

100110000

LED_TXLED_LINK1000VDDOLED_DUPLEX

LED_LINK1000LED_LINK10VSS

100

MDI0_NMDI0_PMDI1_NMDI1_PMDI2_NMDI2_PMDI3_NMDI3_P

TXD6

TXD0TXD1TXD2TXD3TXD4TXD5

TXD7

TX_ER

GTX_CLK

TX_ENTX_CLK

P1_RSET

PHY_RST#

PHY_P1_XTAL2

PHY_P1_XTAL1_R PHY_P1_XTAL1

R_P1_LAN_RST#

PHY_P1_XTAL1PHY_P1_XTAL2

P1_COL_PD

LED_LINK1000LED_LINK100

DSP_SGMII_TXP_CDSP_SGMII_TXN_C

DSP_SGMII_TXPDSP_SGMII_TXN

DSP_SGMII_RXPDSP_SGMII_RXN

P1_CONFIG1P1_CONFIG2P1_CONFIG3P1_CONFIG4

P1_CONFIG0

P1_CONFIG5P1_CONFIG6P1_CLKSEL

LED_LINK1000

LED_LINK10

P1_CONFIG0

P1_CONFIG2

P1_CONFIG5

P1_CONFIG1

P1_CONFIG4

P1_CONFIG6

P1_CONFIG3 LED_DUPLEX

LED_TX

P1_CLKSEL

LED_DUPLEX

LED_LINK10

LED_RXLED_TX

FPGA_JTAG_TDO BSC_JTAG_TDI

VCC1V2VCC2V5 AVCC2V5

VCC2V5AVCC2V5

VCC1V2

VCC2V5

VCC2V5

VCC2V5

IN PHY_RST# (31)

INDSP_MDC_1(12)BIDSP_MDIO_1(12)

OUT LED_LINK1000 (28)OUT LED_LINK100 (28)

IN DSP_SGMII_TXP (12)IN DSP_SGMII_TXN (12)

OUT DSP_SGMII_RXN (12)OUT DSP_SGMII_RXP (12)

BI MDI3_P (28)BI MDI3_N (28)BI MDI2_P (28)BI MDI2_N (28)BI MDI1_P (28)BI MDI1_N (28)BI MDI0_P (28)BI MDI0_N (28)

OUT LED_RX (28)

OUTPHY_INT#(31)IN BSC_PHY_TCK (32)

IN FPGA_JTAG_TDO (32)IN BSC_JTAG_TMS (32)

IN BSC_JTAG_RST# (30,32)OUT BSC_JTAG_TDI (32)

Title


Date: Sheet of


DSPM-8301E A104-1



Title


Date: Sheet of


DSPM-8301E A104-1



Title


Date: Sheet of


DSPM-8301E A104-1



R127 0

R392 4.99K 1%

R774 0

R111 4.7K

C1460.1uF16V

R773 0

C1430.01uF16V

R125 4.99K

R432 NL/22

R778 0

C1520.1uF16V

R391 4.99K 1%

R112 4.7K

C1410.1uF16V

R435 0

R108 NL/4.7K

R775 0

C1424.7uF6.3V

R113 4.7K

C1454.7uF6.3V

R431 NL/0

C1510.01uF16V

C1474.7uF6.3V

R126 0

C1504.7uF6.3V

C1534.7uF6.3V

R109 4.7K

R114 4.7K

C1440.1uF16V

Y325MHz_20pF

R121 4.7K

R110 4.7K

R115 4.7K

R3934.99K

R107 4.7K

R764 10K

R116 4.7KC136 0.1uF 16V

88E1111-BAB

PHY1

MARVELL_88E1111-B2-BAB1C000

DV

DD

_6F

3

RXD0B2

RX_DVB1

VD

DO

_1B

4

DV

DD

_5E

7

RX_CLKC1

RX_ERD2

TX_CLKD1

VD

DO

_2C

2

DV

DD

_4E

3

TX_ERF2

GTX_CLKE2

TX_ENE1

DV

DD

_3D

7

TXD0F1

TXD1G2

TXD2G3

DV

DD

_2C

7

TXD3H2

TXD4H1

TXD5H3

DV

DD

_1C

6

TXD6J1

TXD7J2

VD

DO

_3K

1

125CLKK2

INTL1 MDIOM1

VD

DO

X_2

L2

MDCL3

RESETK3

COMAL4

RSETM2

MDI0+N1

MDI0-N2

AV

DD

_6B

7

MDI1+N3

MDI1-N4

AV

DD

_5N

5

NC_1G1

AV

DD

_4M

8

HSDAC+M5

HSDAC-M6

MDI2+N6

MDI2-N7

AV

DD

_3M

7

MDI3+N8

MDI3-N9

AV

DD

_2M

4

VS

S_1

D4

TDIL7

TRSTM9

TMSL8

TCKL9

VD

DO

X_1

K9

TDOK8

VD

DO

H_2

F7

VS

SC

H7

XTAL2J9XTAL1H9

SEL_FREQH8 CONFIG6G8 CONFIG5G9 CONFIG4F9 CONFIG3G7 CONFIG2F8 CONFIG1E9 CONFIG0D8

VD

DO

H_3

J8

LED_TXD9LED_RXC9LED_DUPLEXE8

VD

DO

H_1

B9

LED_LINK1000A9LED_LINK100B8LED_LINK10C8

AV

DD

_1M

3

S_OUT-A8S_OUT+A7

S_CLK-A6S_CLK+A5

S_IN-A4S_IN+A3

COLB6 CRSB5

DV

DD

_8J7

DV

DD

_7J3

RXD7C5 RXD6A2 RXD5A1 RXD4C4 RXD3B3 RXD2C3 RXD1D3

VS

S_2

G6

VS

S_3

J5

VS

S_4

J6

VS

S_5

K4

VS

S_6

K5

VS

S_7

K6

VS

S_8

L5

VS

S_9

L6

VS

S_1

0D

5

VS

S_1

1D

6

VS

S_1

2E

4

VS

S_1

3E

5

VS

S_1

4E

6

VS

S_1

5F

4

VS

S_1

6F

5

VS

S_1

7F

6

VS

S_1

8G

4

VS

S_1

9G

5

VS

S_2

0H

4

VS

S_2

1H

5

VS

S_2

2H

6

VS

S_2

3J4

NC_2K7

R777 0

C137 0.1uF 16V

C13827pF50V

R118 4.7K

TP4

R762 10K

R776 0

C1490.1uF16V

B7120_100MHz

R763 NL/10K

C13927pF50V

R117 4.7K

R779 0

C1480.01uF16V

C1400.01uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FOR EMI

Heatsink Holes

RJ-45

On board

AMC Hole

LED_LINK1000

MDI0_N

MDI1_N

MDI0_P

MDI3_P

MDI2_N

P1_RC_P01

P1_RC_P02

P1_RC_P00

MDI2_P

MDI1_P

P1_RC_P03

MDI3_N

LED_LINK100

LAN_ACTLED_RX

VCC2V5

VCC2V5

P1_TCT

VCC2V5

P1_TCT

P1_TCT

P1_TCT

P1_TCT

GND_LAN

GND_LAN

INLED_LINK100(27)INLED_LINK1000(27)

INLED_RX(27)

BIMDI3_P(27)

BIMDI3_N(27)

BIMDI2_P(27)

BIMDI2_N(27)

BIMDI1_P(27)

BIMDI1_N(27)

BIMDI0_P(27)

BIMDI0_N(27)

Title


Date: Sheet of


DSPM-8301E A104-1

RJ45


Title


Date: Sheet of


DSPM-8301E A104-1

RJ45


Title


Date: Sheet of


DSPM-8301E A104-1

RJ45


H2

H35-NPTH

1

C280.1uF16V

G

SHIELD GND

1000pF 2kV

75RO

4

7

6

2

8

3

1

5

TX1-

TX2-

TX2+

TX1+

TX3+

TX3-

TX4+

TX4-

G

LAN1

RJ45_W/XFMR&LED

14

13

1

2

3

4

5

6

7

8

9

10

11

12

15

16

17 H3H4

H1H2

R2949.91%

C230.1uF16V

R3149.91%

C250.1uF16V

R2849.91%

H5

H27P35-MTH

1

C260.1uF16V

H3

H35-NPTH

1

R35 100

H4

H35-NPTH

1

R3449.91%

C220.1uF16V

C24 470pF

50V

B2120_100MHz

R36 100R3249.91%

R2749.91%

BRK1SOCKET841_CSBGA841

4

2

3

15

6H1

H35-NPTH

1

C290.1uF16V

C300.1uF16V

FM1

NL/Fiducial

R30 100

FM2

NL/Fiducial

R3349.91%

C210.1uF16V

FM3

NL/Fiducial

B3120_100MHz

C270.1uF16V

FM4

NL/Fiducial

R2649.91%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Pin Header for debug

IPASS+HD for HyperLink Bus connection

DSP_UART(3.3V)

the interfaces on the 80-pin header are all1.8V LVCMOS except for the UART whichis 3.3V LVCMOS

DSP_EMIFA02DSP_EMIFA03DSP_EMIFA04DSP_EMIFA05DSP_EMIFA06DSP_EMIFA07DSP_EMIFA08DSP_EMIFA09DSP_EMIFA10DSP_EMIFA11DSP_EMIFA12DSP_EMIFA13DSP_EMIFA14

DSP_EMIFA00DSP_EMIFA01

DSP_EMIFA15DSP_EMIFA16DSP_EMIFA17DSP_EMIFA18DSP_EMIFA19DSP_EMIFA20DSP_EMIFA21DSP_EMIFA22

DSP_GPIO_14

DSP_GPIO_12

DSP_GPIO_10

DSP_GPIO_00

DSP_GPIO_02

DSP_GPIO_08

DSP_GPIO_04

DSP_GPIO_06DSP_GPIO_05

DSP_GPIO_13

DSP_GPIO_07

DSP_GPIO_11

DSP_GPIO_03

DSP_GPIO_09

DSP_GPIO_15

DSP_GPIO_01

DSP_EMIFA23

DSP_TIMO0

PH_SSPCKDSP_SSPCS1

DSP_TIMI0

DSP_TIMO1

DSP_EMIFWAIT1DSP_EMIFRNW

DSP_TIMI1

DSP_SSPMOSI

DSP_EMIFOEZDSP_EMIFWEZ

DSP_SCLDSP_SDA

DSP_UARTCTSDSP_UARTRTS

DSP_UARTTXDDSP_UARTRXD

DSP_EMIFD14DSP_EMIFD15

DSP_EMIFD0DSP_EMIFD1DSP_EMIFD2DSP_EMIFD3DSP_EMIFD4DSP_EMIFD5DSP_EMIFD6DSP_EMIFD7DSP_EMIFD8DSP_EMIFD9DSP_EMIFD10DSP_EMIFD11DSP_EMIFD12DSP_EMIFD13

DSP_EMIFCE1ZDSP_EMIFCE2ZDSP_EMIFBE0ZDSP_EMIFBE1Z

DSP_SSPMISO

HyperLink_RXFLDATHyperLink_RXPMCLK HyperLink_TXPMDAT

HyperLink_TXFLCLKHyperLink_TXFLDATHyperLink_RXPMDAT

HyperLink_TXP0HyperLink_TXN0


HyperLink_RXN2HyperLink_RXP2



HyperLink_TXN1HyperLink_TXP1


HyperLink_RXN1HyperLink_RXP1

HyperLink_TXPMCLK

HyperLink_RXFLCLK

INDSP_EMIFA00(14)INDSP_EMIFA01(14)INDSP_EMIFA02(14)

INDSP_EMIFA04(14)INDSP_EMIFA03(14)


INDSP_EMIFA07(14)INDSP_EMIFA08(14)INDSP_EMIFA09(14)INDSP_EMIFA10(14)



INDSP_EMIFA15(14)INDSP_EMIFA16(14)INDSP_EMIFA17(14)INDSP_EMIFA18(14)


INDSP_EMIFA21(14)INDSP_EMIFA22(14)INDSP_EMIFA23(14)

IN DSP_SSPMOSI (16,30)

IN DSP_EMIFOEZ (14)IN DSP_EMIFWEZ (14)

IN DSP_TIMO0 (16)

IN DSP_SSPCS1 (16,30)IN PH_SSPCK (16)

IN DSP_TIMO1 (16)

IN DSP_EMIFRNW (14)

OUT DSP_TIMI0 (16,31)

OUT DSP_TIMI1 (16)

BI DSP_SDA (10,16)IN DSP_SCL (10,16)

IN DSP_UARTRTS (16)OUT DSP_UARTCTS (16)

OUT DSP_UARTRXD (16)IN DSP_UARTTXD (16)

BI DSP_EMIFD4 (14)BI DSP_EMIFD5 (14)BI DSP_EMIFD6 (14)BI DSP_EMIFD7 (14)




IN DSP_EMIFCE2Z (14)IN DSP_EMIFCE1Z (14)

IN DSP_EMIFBE0Z (14)IN DSP_EMIFBE1Z (14)

OUT DSP_SSPMISO (16,30)

OUT DSP_EMIFWAIT1 (14)


IN HyperLink_RXFLCLK (12)OUT HyperLink_TXFLCLK (12)

OUTHyperLink_RXPMCLK(12) IN HyperLink_TXPMDAT (12)IN HyperLink_TXPMCLK (12)INHyperLink_RXFLDAT(12)

OUTHyperLink_TXFLDAT(12)OUTHyperLink_RXPMDAT(12)

INHyperLink_TXP2(12)INHyperLink_TXN2(12)

INHyperLink_TXP0(12)INHyperLink_TXN0(12)

OUTHyperLink_RXP0(12)OUTHyperLink_RXN0(12)

OUTHyperLink_RXP2(12)OUTHyperLink_RXN2(12)

IN HyperLink_TXP3 (12)IN HyperLink_TXN3 (12)

IN HyperLink_TXP1 (12)IN HyperLink_TXN1 (12)

OUT HyperLink_RXP3 (12)OUT HyperLink_RXN3 (12)

OUT HyperLink_RXP1 (12)OUT HyperLink_RXN1 (12)

Title


Date: Sheet of


DSPM-8301E A104-1



Title


Date: Sheet of


DSPM-8301E A104-1



Title


Date: Sheet of


DSPM-8301E A104-1



iPass Plus HD 1x1 Assy

Hyperlink1

IPASS+HD_36H

sideband5D1

sideband6D2

GND_D3D3

Txp0D4

Txn0D5

GND_D6D6

Txp2D7

Txn2D8

GND_D9D9

sideband3B1

sideband1B2

GND_B3B3

Rxp0B4

Rxn0B5

GND_B6B6

Rxp2B7

Rxn2B8

GND_B9B9

sideband4C1

sideband2C2

GND_C3C3

Txp1C4

Txn1C5

GND_C6C6

Txp3C7

Txn3C8

GND_C9C9

sideband7A1

sideband0A2

GND_A3A3

Rxp1A4

Rxn1A5

GND_A6A6

Rxp3A7

Rxn3A8

GND_A9A9

NP

TH

1H

1

NP

TH

2H

2

R399 10

TEST_PH1

PH(F)_40x2V_S1.27mm

135791113151719

2468

101214161820

212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980

H2

H1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

High active

PUDC:User I/O Pull-Up Control. WhenLow during configuration, enablespull-up resistors in all I/O pins torespective I/O bank VCCO input.0: Pull-ups during configuration1: No pull-ups

DSP TMS320C6678

DSP

DSP SPI

POWER SEQUENCE

Switches RESET DSP TSIP_CLK/FS

DSP RESETS

Cold_RESET WARM_RESET FULL_RESET

AMC TDM CLOCK

MMC60 PIN HeaderEEPROMNOR FLASH

VCL/VDA Eable

Place near to FPGA

POWER UCD9222

Add three pins for the PCIECLK source selection on the MUX.

a. FPGA_ICS557_OE, pin.J13

b. FPGA_ICS557_PD#, pin.E13

c. FPGA_ICS557_SEL, pin.F13

FPGA_PUDC

SYS_PGOOD

FPGA_PUDC

Cold_RESETSW1-P1 WARM_RESETSW7-P1

MMC_POR_IN_AMC#

DSP_SSPCS1

DSP_SSPMOSI

VCC3V3_AUX_PGOODVCC0V75_PGOOD

MMC_WR_AMC#

DSP_LRESETNMIENZ

DSP_NMIZDSP_LRESETZ

DSP_CORESEL0DSP_CORESEL1DSP_CORESEL2DSP_CORESEL3

DSP_PACLKSEL

DSP_HOUT

DSP_SYSCLKOUT

WARM_RESETCold_RESET

VCC1V5_PGOOD

DSP_VCL_FPGADSP_VD_FPGA

VCC2V5_PGOODVCC5_PGOOD

VCC1V8_PGOOD

FULL_RESETSW8-P1

FULL_RESET

SYS_PGOOD

TDM_CLKD_P TDM_CLKD_NTDM_CLKC_P TDM_CLKC_N

TDM_CLKB_N_RTDM_CLKA_N

TDM_CLKB_P_RTDM_CLKA_P

DSP_SSPMISO





XDS560_IL


MMC_DETECT#MMC_RESETSTAT#

DSP_BOOTCOMPLETE

DSP_RESETSTAT#

MMC_BOOTCOMPLETE

EEPROM_WPNOR_WP#

TRGRSTZ

PCA9306_EN

UCD9222_PG1

PGUCD9222UCD9222_RST#

PMBUS_CLK_RPMBUS_DAT_RPMBUS_ALT_RPMBUS_CTL_R

PMBUS_ALTPMBUS_DAT

PMBUS_CTL

PMBUS_CLK

UCD9222_PG2

PMBUS_CLKPMBUS_DAT DSP_VD_1

DSP_VCL_1

DSP_VD_FPGADSP_VCL_FPGA

BSC_JTAG_RST#

VCC1V5_EN_R

VCC1V8_EN1_RVCC0V75_EN_RVCC2V5_EN_RVCC_5V_EN_R

UCD9222_ENA2_R

UCD9222_ENA1_R

VCC1V8_AUXVCC3V3_FPGA

VCC1V8_AUX

VCC3V3_FPGA VCC3V3_FPGA

VCC1V8

VCC3V3_FPGA

VCC3V3_FPGA

INMMC_POR_IN_AMC#(11)

IN DSP_SSPCS1 (16,29)IN FPGA_SSPCK (16)

IN DSP_SSPMOSI (16,29)

INVCC3V3_AUX_PGOOD(35)INVCC0V75_PGOOD(34)

INMMC_WR_AMC#(11)

OUT DSP_LRESETNMIENZ (16)OUT DSP_CORESEL0 (16)OUT DSP_CORESEL1 (16)OUT DSP_CORESEL2 (16)

OUT DSP_PACLKSEL (16)

OUT DSP_CORESEL3 (16)OUT DSP_NMIZ (16)OUT DSP_LRESETZ (16)

IN DSP_HOUT (16)

IN DSP_SYSCLKOUT (17)

INVCC1V5_PGOOD(36)

OUTVCC1V5_EN(36)

OUTVCC1V8_EN1(34)

OUTVCC2V5_EN(34)OUTVCC0V75_EN(34)

OUTVCC_5V_EN(35)

INVCC2V5_PGOOD(34)INVCC5_PGOOD(35)

OUT DSP_SSPMISO (16,29)

OUT DSP_TSIP1_CLKA1 (15)

OUT DSP_TSIP0_FSA0 (15)OUT DSP_TSIP1_CLKB1 (15)

OUT DSP_TSIP1_FSA1 (15)OUT DSP_TSIP0_FSB0 (15)

OUT DSP_TSIP1_FSB1 (15)

OUT DSP_TSIP0_CLKA0 (15)OUT DSP_TSIP0_CLKB0 (15)

OUT XDS560_IL (15)

OUT DSP_RESETZ (16)

OUT DSP_PORZ (16)OUT DSP_RESETFULLZ (16)

OUT NAND_WP# (14)

INTDM_CLKD_N(10)INTDM_CLKD_P(10)

INTDM_CLKC_N(10)INTDM_CLKC_P(10)

INTDM_CLKA_P(10)INTDM_CLKA_N(10)

INTDM_CLKB_P_R(22)INTDM_CLKB_N_R(22)

INMMC_DETECT#(11)

IN DSP_BOOTCOMPLETE (16)

IN DSP_RESETSTAT# (16)OUTMMC_RESETSTAT#(11)

OUTMMC_BOOTCOMPLETE(11)

IN TRGRSTZ (15)OUT EEPROM_WP (16)OUT NOR_WP# (16)

OUTPCA9306_EN(17)

INPGUCD9222(33)OUTUCD9222_ENA1(33)

INUCD9222_PG1(33)

INPMBUS_ALT(33)

OUTPMBUS_CLK(33)BIPMBUS_DAT(33)

OUTUCD9222_RST#(33)

INUCD9222_PG2(33)OUTUCD9222_ENA2(33)

OUTPMBUS_CTL(33)

IN DSP_VCL_1 (17)BI DSP_VD_1 (17)

OUTFPGA_ICS557_SEL(17)

OUTFPGA_ICS557_PD#(17)

OUTFPGA_ICS557_OE(17)

INBSC_JTAG_RST#(27,32)

Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_XC3S200AN_A


Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_XC3S200AN_A


Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_XC3S200AN_A


RST_COLD1

HDK632AR-ST

12

34

TP16

C3830.1uF16V

R18110K

R479 0

R395 NL/0

C5320.1uF16V

R79 1K

R748.2K

C130.01uF16V

B33 120_100MHz

R480 0

RST_FULL1

HDK632AR-ST

12

34

C90.01uF16V

R80 1K

R68100

R182NL/10K

C5330.1uF16V

R318 100

C3840.1uF16V

R400 10

B34 120_100MHz

R81 1K

R159 0

Bank0Bank1

FPGA1A


IO_L01N_0C13

IO_L01P_0D13

IO_L02N_0B14

IO_L02P_0/VREF_0_1B15

IO_L03N_0D11

IO_L03P_0C12

IO_L04N_0A13

IO_L04P_0A14

IO_L05N_0A12

IO_L05P_0B12

IO_L06N_0/VREF_0_2E10

IO_L06P_0D10

IO_L07N_0A11

IO_L07P_0C11

IO_L08N_0A10

IO_L08P_0B10

IO_L09N_0/GCLK5D9

IO_L09P_0/GCLK4C10

IO_L10N_0/GCLK7A9

IO_L10P_0/GCLK6C9

IO_L11N_0/GCLK9D8

IO_L11P_0/GCLK8C8

IO_L12N_0/GCLK11B8

IO_L12P_0/GCLK10A8

IO_L13N_0C7

IO_L13P_0A7

IO_L14N_0/VREF_0_3E7

IO_L14P_0F8

IO_L15N_0B6

IO_L15P_0A6

IO_L16N_0C6

IO_L16P_0D7

IO_L17N_0C5

IO_L17P_0A5

IO_L18N_0B4

IO_L18P_0A4

IO_L19N_0B3

IO_L19P_0A3

IO_L20N_0/PUDCD5

IO_L20P_0/VREF_0_4C4

IP_0_1D6

IP_0_2D12

IP_0_3E6

IP_0_4F7

IP_0_5F9

IP_0_6F10

IP_0_7/VREF_0_5E9

VCCO_0_1B5

VCCO_0_2B9

VCCO_0_3B13

VCCO_0_4E8

IO_L01N_1/LDC2N14

IO_L01P_1/HDCN13

IO_L02N_1/LDC0P15

IO_L02P_1/LDC1R15

IO_L03N_1/A1N16

IO_L03P_1/A0P16

IO_L05N_1/VREF_1_1M14

IO_L05P_1M13

IO_L06N_1/A3K13

IO_L06P_1/A2L13

IO_L07N_1/A5M16

IO_L07P_1/A4M15

IO_L08N_1/A7L16

IO_L08P_1/A6L14

IO_L10N_1/A9J13

IO_L10P_1/A8J12

IO_L11N_1/RHCLK1K14

IO_L11P_1/RHCLK0K15

IO_L12N_1/TRDY1/RHCLK3J16

IO_L12P_1/RHCLK2K16

IO_L14N_1/RHCLK5H14

IO_L14P_1/RHCLK4J14

IO_L15N_1/RHCLK7H16

IO_L15P_1/IRDY1/RHCLK6H15

IO_L16N_1/A11F16

IO_L16P_1/A10G16

IO_L17N_1/A13G14

IO_L17P_1/A12H13

IO_L18N_1/A15F15

IO_L18P_1/A14E16

IO_L19N_1/A17F14

IO_L19P_1/A16G13

IO_L20N_1/A19F13

IO_L20P_1/A18E14

IO_L22N_1/A21D15

IO_L22P_1/A20D16

IO_L23N_1/A23D14

IO_L23P_1/A22E13

IO_L24N_1/A25C15

IO_L24P_1/A24C16

IP_L04N_1/VREF_1_2K12

IP_L04P_1K11

IP_L09N_1J11

IP_L09P_1/VREF_1_3J10

IP_L13N_1H11

IP_L13P_1H10

IP_L21N_1G11

IP_L21P_1/VREF_1_4G12

IP_L25N_1F11

IP_L25P_1/VREF_1_5F12

SUSPENDR16

VCCO_1_1E15

VCCO_1_2H12

VCCO_1_3J15

VCCO_1_4N15

TP13

R8100

R319 100

TP14

R156 0

R1398.2K

C5460.1uF16V

R58.2K

R474 0

TP15

R140100

R153 0

R317 100

R99 1K

C5990.1uF16V

B

SYSPG_D1

19-215SUBC/S280/TR81

2

R477 0

R228 100

R154 0

R84 1K

R184330

RST_WARM1

HDK632AR-ST

12

34

R481 0

C6000.1uF16V

R155 0

R410 NL/0

C5310.1uF16V

R201 10K

R482 0

R478 0

R394 NL/0

R409 NL/0

C110.01uF16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DEBUG_LED

BOOT STRAP CONFIGURATIONdefault value : TBD

FPGA EEPROM

PHY 88E1111

For BOOT MODESWITCH

DSP GPIOTO FPGA

CLOCK GEN

GPIO14

GPIO15

The device configuration fieldsGPIO[10:4] are used to configure theboot peripheral and, therefore, the bitdefinitions depend on the boot mode.

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

PA driver from PA clkSGMII

PCIe

I2C

1 1 0

1 1 1

Boot Mode

LENDIAN

BOOTMODE00

Configuration

SPI

HyperLink

PCIESSMODE0

BOOT

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

PA driver from PA clk

Device

100.00

156.25

250.00

1 1 0

1 1 1

312.50

122.88

INPUT

CLK (MHz)CorePac System PLL Configuration

PA driven from core clk

BM_GPIO

50.00

66.67

80.00

13 12 11

BOOTMODE01

BOOTMODE02

BOOTMODE03

BOOTMODE04

BOOTMODE05

DSP

BOOTMODE06

BM_GPIO14

BM_GPIO15

DIP Switch

BM_GPIO0

BM_GPIO1

BM_GPIO2

BM_GPIO3

BM_GPIO4

BM_GPIO5

BM_GPIO6

BM_GPIO7

BM_GPIO8

BM_GPIO9

BM_GPIO10

BM_GPIO11

BM_GPIO12

BM_GPIO13

BOOTMODE07

BOOTMODE08

BOOTMODE09

BOOTMODE10

BOOTMODE11

BOOTMODE12

NOTE

PCIESSMODE1

Primary Function

Pull Up

Endpt/RootComplex

Pull Down

Little Endian Big Endian

Boot Device

Boot Device

Boot Device

Device Cfg

Device Cfg

Device Cfg

Device Cfg

Device Cfg

Device Cfg

PA driven from core clk

BM_GPIO

EMIF16

sRIO

SMGII

Device Cfg

PLL Multiplier/I2C

PLL Multiplier/I2C

PLL Multiplier/I2C

Endpt/RootComplex

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

Device

Field

GPIO8

BM_GPIO

[10:4]

GPIO9

GPIO10

GPIO11

GPIO12

3 2 1

GPIO13

Boot Configuration

Boot Device

Device Configuration

PLL SettingsMMC SPI

INPUT Description

00b

01b

10b

PCIe in Legacy End-point mode(no support for MSI)

PCIe in Legacy Root complex mode

PCIe in End-point mode

BM_GPIO [15:14]

PCIe Mode selection(PCIESSMODE[1:0])

Description

0

1 Initial state of the power domain and the clock domain for PCIE subsystem is enabled

Initial state of the power domain and the clockdomain for PCIE subsystem is disabled

Input

PCIESSEN

UCD9222

VCC1V0 VID CTRL

For FPGA internal reset.

VID Eable

FPGA_M0 FPGA_M1 FPGA_M2

DEBUG_LED_1

DEBUG_LED_3

DEBUG_LED_2

DEBUG_LED_0

BM_GPIO_00BM_GPIO_01BM_GPIO_02BM_GPIO_03




FPGA_SPI_CS#FPGA_SPI_SI

FPGA_SPI_SO

DEBUG_LED_1DEBUG_LED_0

FPGA_M0FPGA_M1

FPGA_M2

DEBUG_LED_2DEBUG_LED_3

FPGA_INIT#

FPGA_INIT#

BM_GPIO_05

BM_GPIO_14BM_GPIO_13

BM_GPIO_08BM_GPIO_07BM_GPIO_06

BM_GPIO_00


BM_GPIO_15


FPGA_SPI_CS#

FPGA_SPI_SIFPGA_SPI_WP#FPGA_SPI_SO

FPGA_SPI_SCKFPGA_SPI_HD#

MMC_SPI_STEMMC_SPI_SCK

MMC_SPI_MOSIMMC_SPI_MISO

MAIN_48MHZ_CLK_R

MAIN_48MHZ_CLK MAIN_48MHZ_CLK_R

FPGA_SPI_SCK

PCIESSEN

PCIESSEN

User_define

User_define

DSP_TIMI0

CLOCK3_PLL_LOCKCLOCK2_PLL_LOCKFPGA_VS1FPGA_VS0

FPGA_VS2

VCC3V3_FPGA VCC3V3_FPGA VCC3V3_FPGA

VCC3V3_FPGA

VCC3V3_FPGA

VCC3V3_FPGA

VCC3V3_FPGA

VCC1V8_AUX

VCC1V8_AUX

VCC3V3_FPGA

VCC3V3_FPGA

VCC3V3_FPGA

VCC3V3_FPGA

VCC3V3_AUX

OUT PHY_RST# (27)

IN CLOCK2_SSPSO (23)

IN CLOCK3_SSPSO (22)

OUT CLOCK2_SSPCK (23)OUT CLOCK2_SSPSI (23)

OUT REFCLK3_PD# (22)

OUT CLOCK3_SSPCK (22)OUT CLOCK3_SSPSI (22)

OUT CLOCK3_SSPCS1 (22)

OUT CLOCK2_SSPCS1 (23)

OUT REFCLK2_PD# (23)

OUT MMC_SPI_SCK (11)OUT MMC_SPI_STE (11)

OUT MMC_SPI_MOSI (11)IN MMC_SPI_MISO (11)


IN PHY_INT# (27)

OUT UCD9222_VID2A (33)OUT UCD9222_VID2B (33)OUT UCD9222_VID2C (33)OUT UCD9222_VID2S (33)

OUTDSP_TIMI0(16,29)

IN CLOCK2_PLL_LOCK (23)IN CLOCK3_PLL_LOCK (22)

IN FPGA_DONE (32)

OUT VID_OE# (17)

Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_XC3S200AN_B

C31 40Tuesday, March 13, 2012

Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_XC3S200AN_B


Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_XC3S200AN_B


B

FPGA_D219-215SUBC/S280/TR8

1 2

B36120_100MHz

B24120_100MHz

ON

SW6ESD104EZ1234 5

8

67

B35120_100MHz

R312 10K

R208 330

R299 10K

R396 10

R211 100

R402 100

R305 100

R216 100

R297 100

R401 10

R284 10K

C3870.1uF16V

ON

SW5ESD104EZ1234 5

8

67

R473 10

R302 100

R264 10K

R403 100

R207 330

R197NL/0

R306 10K

U26

ATMEL_AT25128B-SSHL-B

CS1

SO2

WP3

GND4

SI5SCK6HOLD7VCC8

R296 10K

R310 100R308 10K

R924NL/0

R285 100

R9231K

R206 330

B


1 2

B


1 2

R191330

R298 10K

R303 100

R1894.7K

R205 330

ON

SW3ESD104EZ1234 5

8

67

Y7

48MHz_15pF

VCC4

OUT3

GND2

OE1

R421 10K

R300 100

R283 100

R213 10K

R195 4.7K

R193NL/330

C4400.1uF16V

R304 10K

R422 10K

R212 100

C3890.1uF16V

C3820.1uF16V

R407 10K

R265 10K

R397 10

R198NL/0

R1904.7K

B


1 2

R210 10K

C5300.1uF16V

R408 10K

C3880.1uF16V

R289 100

R196 4.7K

R309 10K

R194 4.7K

C4360.1uF16V

C4350.1uF16V

R423 10K

R178 33

R311 100

Bank2Bank3

FPGA1B


IO_L01N_2/M0P4

IO_L01P_2/M1N4

IO_L02N_2/CSOT2

IO_L02P_2/M2R2

IO_L03N_2/VS2T3

IO_L03P_2/RDWRR3

IO_L04N_2/VS0P5

IO_L04P_2/VS1N6

IO_L05N_2R5

IO_L05P_2T4

IO_L06N_2/D6T6

IO_L06P_2/D7T5

IO_L07N_2P6

IO_L07P_2N7

IO_L08N_2/D4N8

IO_L08P_2/D5P7

IO_L09N_2/GCLK13T7

IO_L09P_2/GCLK12R7

IO_L10N_2/GCLK15T8

IO_L10P_2/GCLK14P8

IO_L11N_2/GCLK1P9

IO_L11P_2/GCLK0N9

IO_L12N_2/GCLK3T9

IO_L12P_2/GCLK2R9

IO_L13N_2M10

IO_L13P_2N10

IO_L14N_2/MOSI/CSIP10

IO_L14P_2T10

IO_L15N_2/DOUTR11

IO_L15P_2/AWAKET11

IO_L16N_2N11

IO_L16P_2P11

IO_L17N_2/D3P12

IO_L17P_2/INITT12

IO_L18N_2/D1R13

IO_L18P_2/D2T13

IO_L19N_2P13

IO_L19P_2N12

IO_L20N_2/CCLKR14

IO_L20P_2/D0/DIN/MISOT14

IP_2_1L7

IP_2_2L8

IP_2_3/VREF_2_1L9

IP_2_4/VREF_2_2L10

IP_2_5/VREF_2_3M7

IP_2_6/VREF_2_4M8

IP_2_7/VREF_2_5M11

IP_2_8/VREF_2_6N5

VCCO_2_1M9

VCCO_2_2R4

VCCO_2_3R8

VCCO_2_4R12

IO_L01N_3C1

IO_L01P_3C2

IO_L02N_3D3

IO_L02P_3D4

IO_L03N_3E1

IO_L03P_3D1

IO_L05N_3E2

IO_L05P_3E3

IO_L07N_3G4

IO_L07P_3F3

IO_L08N_3/VREF_3_1G1

IO_L08P_3F1

IO_L09N_3H4

IO_L09P_3G3

IO_L10N_3H5

IO_L10P_3H6

IO_L11N_3/LHCLK1H1

IO_L11P_3/LHCLK0G2

IO_L12N_3/IRDY2/LHCLK3J3

IO_L12P_3/LHCLK2H3

IO_L14N_3/LHCLK5J1

IO_L14P_3/LHCLK4J2

IO_L15N_3/LHCLK7K1

IO_L15P_3/TRDY2/LHCLK6K3

IO_L16N_3L2

IO_L16P_3/VREF_3_2L1

IO_L17N_3J6

IO_L17P_3J4

IO_L18N_3L3

IO_L18P_3K4

IO_L19N_3L4

IO_L19P_3M3

IO_L20N_3N1

IO_L20P_3M1

IO_L22N_3P1

IO_L22P_3N2

IO_L23N_3P2

IO_L23P_3R1

IO_L24N_3M4

IO_L24P_3N3

IP_L04N_3/VREF_3_3F4

IP_L04P_3E4

IP_L06N_3/VREF_3_4G5

IP_L06P_3G6

IP_L13N_3J7

IP_L13P_3H7

IP_L21N_3K6

IP_L21P_3K5

IP_L25N_3/VREF_3_5L6

IP_L25P_3L5

VCCO_3_1D2

VCCO_3_2H2

VCCO_3_3J5

VCCO_3_4M2

R301 10K

ONSW9

ESD102EZ

12

43

R214 100

R307 100R313 100

R192330

R1990

ON

SW4ESD104EZ1234 5

8

67

C4390.1uF16V

R215 10K

C3900.1uF16V

R209 10K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

During Configuration :Must be High to allowconfiguration to start.

a. Remove the boundary scan chain from UCD9222.

b. Remove bus switch and loop in the FPGA and PHY .

FPGA_PROG

FPGA_PROG

FPGA_DONE

FPGA_DONEBSC_JTAG_TMS

BSC_JTAG_TDO

BSC_JTAG_TCK

BSC_JTAG_TCK

BSC_JTAG_TDO

BSC_JTAG_TMS

BSC_FPGA_TCK

BSC_JTAG_TDI

BSC_JTAG_TCK

BSC_JTAG_TCK

BSC_FPGA_TCK

BSC_PHY_TCK

BSC_JTAG_RST#

BSC_JTAG_P8

BSC_JTAG_P8

BSC_JTAG_TDOBSC_JTAG_TMSBSC_JTAG_RST#

VCC3V3_FPGA VCC3V3_FPGA

VCC1V2_FPGAVCC1V2

VCC3V3_FPGA

VCC1V2_FPGA

VCC3V3_FPGAVCC3V3_AUX

VCC3V3_AUX

VCC3V3_FPGA

VCC3V3_AUX

OUTFPGA_JTAG_TDO(27)

OUT BSC_PHY_TCK (27)

IN BSC_JTAG_TDI (27)

OUT BSC_JTAG_TMS (27)OUT BSC_JTAG_RST# (27,30)

OUTFPGA_DONE(31)

Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_XC3S200AN_C


Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_XC3S200AN_C


Title


Date: Sheet of


DSPM-8301E A104-1

FPGA_XC3S200AN_C


R219NL/330

B26 120_100MHz

R220NL/100K

R370 4.7K

C5280.1uF16V

R413 4.7K

R966 22

C4170.1uF16V

GD11NL/KP-1608SGD

12

U257BTI_SN74LVC2G125DCUR

7

5 3

C3860.1uF16V

C15 0.1uF16V

C4180.1uF16V

C4750.1uF16V

R315 4.7K

R371 NL/1K

U257ATI_SN74LVC2G125DCUR

18

2

4

6

C4140.1uF16V

C38510uF6.3V

C4190.1uF16V

R443 4.7K

C4760.1uF16V

R424 4.7KTAP_FPGA1PH_8x1V_2.54mm

12345

76

8

C39210uF6.3V

R2184.7K

C4150.1uF16V

R430 0

R414 4.7K

C4250.1uF16V

C5340.1uF16V

C3930.1uF16V

R965 22

B25 120_100MHz

FPGA1C


DONET15

PROGA2

TCKA15

TDIB1

TDOB16

TMSB2

VCCAUX_1E11

VCCAUX_2F5

VCCAUX_3L12

VCCAUX_4M6

VCCINT_1G7

VCCINT_2G9

VCCINT_3H8

VCCINT_4J9

VCCINT_5K8

VCCINT_6K10

GND_1A1

GND_2A16

GND_3B7

GND_4B11

GND_5C3

GND_6C14

GND_7E5

GND_8E12

GND_9F2

GND_10F6

GND_11G8

GND_12G10

GND_13G15

GND_14H9

GND_15J8

GND_16K2

GND_17K7

GND_18K9

GND_19L11

GND_20L15

GND_21M5

GND_22M12

GND_23P3

GND_24P14

GND_25R6

GND_26R10

GND_27T1

GND_28T16

C3910.1uF16V

R968 22

R2171K

C4160.1uF16V

C4120.1uF16V

C5350.1uF16V

R967 22

C3940.1uF16V

C4130.1uF16V

C4000.1uF16V

R969 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Corresponding "EA" Pins MUST be routed as differentialsignals and connected next to DSP for specific rails

DSP Vcore @8A1.0V@ 5A

CVDD / VCC1V0

Series resistors on EA nets to be placed at the load for proper voltage feedback.

The component need next to UCD9222

DSP

CVDD

GND

10 ohm

10 ohm

750 ohm

560 pF

750 ohm

560 pF

10 ohm

10 ohm

VCC1V0

GND

EAP1EAN1

EAP2EAN2

UCD9222

EAp1

EAn1

EAp2

EAn2

The component need next to UCD9222

Each 22uF Cin cap needs to tightly coupled to Vin and PGND of the UCD7242.

PMBUS Address=>78 (6*12+6)

PMBus RESISTANCE ( K ohm )PMBus Address

OPEN

11

10

9

8

7

6

5

4

3

2

1

0

SHORT

--205

178

154

133

115

100

86.6

75

64.9

56.2

48.7

42.2

--

PMBus Address Bins

+++Inductor Calculation for CVDD+++

L= ( 12 - 1 ) / ( 8 ) * (1/12) / 750KL= ( 11 / 8 ) * ( 0.083 / 750K )L= 0.152 uH

+++Inductor Calculation for VCC1V0+++

L= ( 12 - 1 ) / 5 * (1/12) / 750KL= ( 11 / 5 ) * ( 0.083 / 750K )L= 0.243 uH

+++output capacitor Calculation for VCC1V0+++

C= 5 / ( 10m * 8 * 750k )C=83.3uF

(VPPQ=10mV)

(VPPQ=10mV)

+++output capacitor Calculation for VCC1V0+++

C= 8 / ( 10m * 8 * 750k )C= 133.3uF

Temperature Coefficient: 10 mV/ ℃℃℃℃Output Voltage: TA = 0 => Vout= 500mV℃℃℃℃

A103-1

A103-1

A103-1

A103-1

A103-1

A103-1

Place the caps close UCD9222 on the top side.

A103-1

PMBUS_DATPMBUS_CLK

PMBUS_ALTPMBUS_CTL

FF-1APWM-1AUCD9222_PG1

UCD_VIN

PWM-1A

SRE_A

FF-1A

lsenes-1A

EAN1T

EM

P1_

2

PGUCD9222

PWM-2A

FF-2A

SRE_B

isenes-2A

UCD9222_ENA1

UCD9222_ENA2

FF-2APWM-2AUCD9222_PG2

PMBUS_ALTPMBUS_DAT

PMBUS_CTL

PMBUS_CLK

EAP1

EAN2EAP2

EAP1

EAP2

9222_TRST#9222_TMS

EAN1

EAN2

lsenes-1A

isenes-2A

UCD9222_PG1UCD9222_PG2

CS2A

CS1A

9222_TDI9222_TDO

9222_TCK

9222_TDO

9222_TMS9222_TDI

9222_TCK

9222_TRST#

UCD9222_LINMON

UCD9222_LINMON

TEMP1_2

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC12

CVDD

VCC12

VCC3V3_AUX

VCC1V0

VCC3V3_AUX

VCC12

CVDD

VCC1V0

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

VCC3V3_AUX

V33A_9222VCC3V3_AUX

OUTPGUCD9222(30)

IN UCD9222_VIDA (17)IN UCD9222_VIDB (17)IN UCD9222_VIDC (17)IN UCD9222_VIDS (17)

IN UCD9222_ENA1 (30)OUT UCD9222_PG1 (30)

BIPMBUS_DAT(30)OUTPMBUS_ALT(30)

INPMBUS_CTL(30)

INUCD9222_RST#(30)

INPMBUS_CLK(30)

IN UCD9222_ENA2 (30)OUT UCD9222_PG2 (30)

IN UCD9222_VID2A (31)IN UCD9222_VID2B (31)IN UCD9222_VID2C (31)IN UCD9222_VID2S (31)

Title


Date: Sheet of


DSPM-8301E A104-1

Power ucd9222


Title


Date: Sheet of


DSPM-8301E A104-1

Power ucd9222


Title


Date: Sheet of


DSPM-8301E A104-1

Power ucd9222


C457220uF4V

C448 0.01uF16V

C46147uF6.3V

PMBUS1PH_5x1V_2.54mm

12345

U32

TI_UCD9222RGZR

VinMon4

Vtrack45

Temp1/AuxADC146

Temp2/AuxADC22

ADC_REF48

EAp137

EAn138

EAp239

EAn240

JTAG_TRST31 JTAG_TMS30

JTAG_TDI/SYNC_IN29

JTAG_TDO/SYNC_OUT28

JTAG_TCK27

PMBus_ADDR044

PMBus_ADDR143

PowerGood17

PMBUS_CLK10

PMBUS_DATA11

PMBUS_ALERT19

PMBUS_CNTRL20

RESET5

V33FB41

V33A34

V33DIO33

BPCAP35

VID1A16

VID1B18

VID1C21

VID1S7

VID2A22

VID2B23

VID2C24

VID2S9

CS1A42

DPWM1A12

ENA125

FLT1A6

PG113

IinMon1 CS2A

3

DPWM2A14

ENA226

FLT2A8

PG215

AGND236

AGND347

DGND332

PowerPad49

Thermal_VIA150

Thermal_VIA251

Thermal_VIA352

Thermal_VIA453

Thermal_VIA554

Thermal_VIA655

Thermal_VIA756

Thermal_VIA857

Thermal_VIA958

Thermal_VIA1059

Thermal_VIA1160

Thermal_VIA1261

Thermal_VIA1362

Thermal_VIA1463

Thermal_VIA1564

Thermal_VIA1665

Thermal_VIA1766

Thermal_VIA1867

Thermal_VIA1968

Thermal_VIA2069

Thermal_VIA2170

Thermal_VIA2271

Thermal_VIA2372

Thermal_VIA2473

Thermal_VIA2574

C447 0.01uF 16V

R418 10K

C5181000pF50V

R25010.2K1%

R451 10K

C6074.7uF6.3V

C471330uF6.3V

C4644.7uF16V

R259 10K

C452 0.22uF25V

R2521.5K

R373 4.99K 1%

C6030.1uF

16V

C4631uF16V

C45347uF6.3V

C459220uF4V

L6 0.47uH17.5A

R247 NL/0R338 10

R452 10K

C469330uF6.3V

R404 10K

R262 10K

R246 NL/2K

R415 NL/2K

C46247uF6.3V

R258 1M

C473330uF6.3V

R454 10K

Q13

<Characteristic>MICROCHIP_MCP9700AT-E/LT

NC11VOUT3

GN

D2

VDD4

NC25

R419 10K

R437NL/10K

C460330uF6.3V

R411 10

R260 10

U34

TI_UCD7242RSJT

PWM_B1

SRE_B2

BST_B3

BSW_B4

VG

G5

VG

G_D

IS6

IMON_B7

test

mod

e8

FLT_B9

PGND_110

NC-PGND_111 PGND_212

SWB13

SWA14

FLT_A18

TM

ON

19

IMON_A20

AG

ND

21

BP

322

BSW_A23

BST_A24

SRE_A25

PWM_A26

VIN

_327

NC

-VIN

_228

VIN

_429

VIN

_130

NC

-VIN

_131

VIN

_232

PGND_315

NC-PGND_216PGND_417

R406 10

C474330uF6.3V

R566 2

R253 100K 1%

R405 750

C6020.01uF16V

R256 2K

TP19

R255 2K

R416 1001%

R261 750

R417 1001%

C455220uF4V

C451 0.22uF25V

C45447uF6.3V

R254 100K 1%

R257 100K

C44922uF16V

C443 0.01uF 16V

C467 560pF 50V

C3700.1uF16V

R2631K1%

C609 0.01uF 16V

R4201K1%

C456330uF6.3V

R438 10K

R376 10K

R331 10K

C458220uF4V

C446 560pF 50V

L5 0.47uH17.5A

R439 10K

C444 1uF6.3V

R440 10KR251 4.99K 1%

C3724.7uF6.3V

C445 0.1uF16V

C45022uF16V

R441 10K

TP18

C608 0.01uF 16V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Vout=(R1+R2)/R2*1.204

R1

R2

R1

R2

Vout=(R1+R2)/R2*1.204

R1

R2

Vout=(R1+R2)/R2*1.204

1.2V @0.38AVCC1V2

2.5V @0.21AVCC2V5

0.75V @0.25A

VCC1V8_AUX1.8V_AUX @0.3A

VCC1V8

VCC0V75

R1

R2

Vout=(R1+R2)/R2*1.204

[email protected]

1.805V =(28k+56.2k)/56.2k*1.205

1.805V =(28k+56.2k)/56.2k*1.205

2.50V =(39.2k+36.5k)/36.5k*1.204

1.204V = (0+10k)/10k*1.204

VCC0V75_PGOOD

VCC2V5_EN

VCC0V75_EN

VCC2V5_PGOOD

VCC3V3_AUX VCC1V2 VCC3V3_AUX VCC1V8_AUX

VCC3V3_AUX VCC2V5

VCC3V3_AUX

VCC0V75


VCC3V3_AUX

VCC3V3_AUX VCC1V8

VCC2V5

VCC1V5

OUT VCC0V75_PGOOD (30)

IN VCC0V75_EN (30)

INVCC2V5_EN(30)INVCC1V8_EN1(30)


Title


Date: Sheet of


DSPM-8301E A104-1

Power_1.2V/1.8V/2.5V/0.75V


Title


Date: Sheet of


DSPM-8301E A104-1

Power_1.2V/1.8V/2.5V/0.75V


Title


Date: Sheet of


DSPM-8301E A104-1

Power_1.2V/1.8V/2.5V/0.75V


C5060.1uF16V

C39910uF6.3V

C40910uF6.3V

TP22

C50710uF6.3V

C51710uF6.3V

R142 1K

R2311K1%

TP28

C5230.1uF16V

C4100.1uF16V

R22539.2K1%

R229 1K1%

R22456.2K1%

R7510K

C39510uF6.3V

Q3TI_TPS73701DRBT

EN5

GN

D4

VIN8

VOUT1

FB3

EP

AD

9

NC

12

NC

26

NC

37

R21 10K

R23010K

R25 10K

TP20

C40710uF6.3V

R22310K1%

R22736.5K1%

VCC

GND

U251TI_SN74LVC1G07DBVR

123 4

5

Q5TI_TPS73701DRBT

EN5

GN

D4

VIN8

VOUT1

FB3

EP

AD

9

NC

12

NC

26

NC

37

C39810uF6.3V

TP24

C5080.1uF16V

C51410uF6.3V

C40510uF6.3V

R22228K1%

R14110K

C39710uF6.3V

C5150.1uF16V

C50910uF6.3V

C5100.1uF16V

TP21

C5540.1uF16V

C4030.01uF16V

R38528K1%

C4060.1uF16V

C5480.1uF16V

Q2TI_TPS73701DRBT

EN5

GN

D4

VIN8

VOUT1

FB3

EP

AD

9

NC

12

NC

26

NC

37

Q4TI_TPS73701DRBT

EN5

GN

D4

VIN8

VOUT1

FB3

EP

AD

9

NC

12

NC

26

NC

37

R2210

C5470.1uF16V

R2210K

R2310K

R38656.2K1%

C40810uF6.3V

C5130.1uF16V

U27TI_TPS51200DRCT

REFIN1

VLDOIN2

VO3

PGND4

VOSNS5

REFOUT6

EN7

GND8

PGOOD9

VIN10

EP

AD

11

VIA

112

VIA

213

VIA

314

VIA

415

VIA

516

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3.3=0.8 V*(10k/3.1k+1)

5=0.8 V*(10k/1.87k+1)

Vout=0.8 V*(R1/R2+1)

R1

R2

VCC5 5V @1A

VCC3V3_AUX

3.3V_AUX @2.585A

Vout=0.8 V*(R1/R2+1)

R1

R2

[email protected]

[email protected]

Assume 80% Pe,

Iin = ( 5V * 1A ) / 80% / 12V = 520mA

Assume 90% Pe,

Iin = ( 3.3V * 2.58A ) / 90% / 12V = 788mA

Reference Inductor 22uH

Cout=1/( 2 * 3.14 * 5 * 25K)

Cout=1.3 uf

Reference Capacitor=100uF

+++output capacitor Calculation+++(KIND=0.3)

Rrt

Rrt=48000xFsw(kHz)^(-0.997)-2

=48000x840^(-0.997)-2

=~56.2 (k ohms)

(KIND=0.3)(Over all tolerance is 5% ,DC tolerance is 2.5% )

Cout>(2*delta(Iout))/(Fsw*delta(Vout))

Cout>(2*3/(840kHz*0.0825)

Cout>~87uF


+++output capacitor Calculation+++

Reference Inductor 3.3uH

+++Inductor Calculation+++L = (Vin - Vout)/(Iout * Kind) * (Vout/(Vin * Fsw)L = ((12 - 3.3)/(3A * 0.3) * (3.3 / (12 * 840kHz))L = 9.67 * 0.33u

L = ~3.2 uH

+++Inductor Calculation+++L = ((Vin(max) - Vout)/Iout * Kind)) * (Vout/(Vin(m ax) * Fsw))L = ((12.6 - 5)/1 * Kind) * (5 / (12.7 * 570K))L = ((7.6/ 0.3) * (5 / (7239K))L = (25.3) * (0.69M)L = 17.5uH

A103-1

VCC3V3_AUX_EN_R

VCC3V3_AUX_PGOOD

VCC3V3_AUX_EN

VCC5_PGOOD

VCC3V3_AUX_EN

VCC5

VCC3V3_AUXVCC12

VCC12

VCC3V3_AUX

VCC12

VCC3V3_AUX

VCC5

VCC12

INVCC_5V_EN(30)

OUT VCC3V3_AUX_PGOOD (30)

OUT VCC5_PGOOD (30)

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DSPM-8301E A104-1



Title


Date: Sheet of


DSPM-8301E A104-1



Title


Date: Sheet of


DSPM-8301E A104-1



C42310uF16V

D7B340A

12

B158 120_100MHz

U36TI_TPS54620RGY

RT/CLK1

GND12

GND23

PVIN14

PVIN25

VIN6

VSENSE7

PWRGD14

BOOT13

PH212

PH111

EN10

SS/TR9

COMP8

EP

AD

15C4241200pF50V

R332 56.2K 1%

VCC

GND

U253TI_SN74LVC1G07DBVR

123 4

5

R33610K1%

R23922.6K

C4200.1uF16V

R33431.6K

U29

TI_TPS54231D

BOOT1

VIN2

EN3

SS4

PH8

GND7

COMP6

VSENSE5

C42756pF50V

C4260.01uF16V

C5380.1uF16V

R24010K

R2411.87K1%

R33510K

B165120_100MHz

R3331.69K1%

R237NL/33K

L2 22uH2.8A

C4378200pF50V

TP26

R37431.6K1%

C4280.01uF16V

C54310uF16V

R483 0

C4380.01uF16V

R143 1K

C54410uF16V

C431 0.1uF16V

C432100uF6.3V

R23810K1%

L8 3.3uH6A

TP25

C5450.1uF16V

R13610K

R35010K

C422100uF6.3V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1.52=0.8 V*(9.09k/10k+1)

Vout=0.8 V*(R1/R2+1)

R1

R2

1.5V @2.12A

VCC1V5

[email protected]

Assume 90% Pe,

Iin = ( 1.5V * 2.12A ) / 90% / 12V = 295mA

(Over all tolerance is 5% ,DC tolerance is 2.5%)

Cout=(2*delta(Iout))/(Fsw*delta(Vout))

Cout=(2*2.5A)/(840kHz*0.0375)

Cout=~159uF


+++Inductor Calculation+++L = (Vin - Vout)/(Iout * Kind) * Vout/(Vin * Fsw)L = (12 - 1.5)/(2.5A * 0.3) * 1.5 / (12 * 840kHz)L = ~2.08uH

(KIND=0.3)

Reference Inductor 3.3uH

+++output capacitor Calculation+++

VCC1V5_EN

VCC1V5_PGOOD

VCC1V5

VCC3V3_AUX

VCC12

VCC12


IN VCC1V5_EN (30)

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DSPM-8301E A104-1

Power VCC1V5


Title


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DSPM-8301E A104-1

Power VCC1V5


Title


Date: Sheet of


DSPM-8301E A104-1

Power VCC1V5


C5290.1uF16V

R37510K

R2439.09K1%

R242 56.2K 1%

L33.3uH

6A

C4348200pF50V

R2441.69K

B164 120_100MHz

R31410K

C54010uF16V

U30TI_TPS54620RGY

RT/CLK1

GND12

GND23

PVIN14

PVIN25

VIN6

VSENSE7

PWRGD14

BOOT13

PH212

PH111

EN10

SS/TR9

COMP8

EP

AD

15

C54110uF16V

C4330.01uF16V

C539100uF6.3V

C429 0.1uF16V

C5420.1uF16V

TP27

C430100uF6.3V

R24510K1%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

History

1. BOM change list: (ECOP-078102)

Jan.24.2011:

a. Update Block, Sequences, Clock diagrams.

d. Change I2C serial EEPROM for the 50h & 51h of address.

a. MMC enable pin: remove R11, populate R16.

b. DDR3 slew rate setting: remove R72, populate R70.

c. VCC5_AUX enabled by FPGA: remove R237.

d.1 Change I2C EEPROM to STMicro_M24M01-HRMN6TP.

a.1 De-assert PORz first and de-assert RESETFULLz after for DSP reset sequence.

b. Change DSP clockings: CORECLK = PASSCLK = 100MHz, PCIECLK = 100MHz

d.2. remove R164.

e. Change COM1 pin header to the connector with lock.

b. Correct the MCMRX sideband pins to output and the MCMTX sideband pins to input.

c. Change the note 'NL/' on R235 (RSVD09), populating R234 (RSVD08).

8. Change the PMBUS1 to 5Pin/2.54mm connector

9. UCD9222 changes:

a. Add a 10k pull-up resistor on the PMBUS_CTL and DNI it.b. Add a 10k pull-down resistor on the JTAG_TSRT.c. Remove the JTAG pins on the UCD9222 from the boundary scan chain.d. Add a 10k pull-down resistor on the UCD9222_RST# and DNI it.e. Separate analog GND to digital GND.

5. Add a clock MUX to select the DSP PCIECLK source from the AMC FCLK or CDCE62005.

7. Modify the boundary scan loop and remove the JTAG connections from the UCD9222 portion.

1. Add the JTAG connection on AMC edge connector .

2. Remove the SW2, R9, C10, R12, R17 for LEDs re-placement.

4. Change COM_SEL1 to DIP type and COM1 with lock.

3. FPGA code change list:

2. Schematics change list:

b. Boot mode change to I2C EEPROM and none-boot mode.

d. All reset behaviours on the board are defined.

DSPM-8301 A102-1 / 19C2830101

3. Change I2C EEPROM (128kB) to M24M01-HRMN6TP and its footprint.

6. Change DDR3 1333 to 1600 by the Micron 1G X16.

10. Add test points on all power rails.

11. Remove R443 on the PCIECLK to the DSP, put all ternmiantions next by PCIECLK MUX.

12. Install R440 on 9222_TCK, install R439 on PMBUS_CTL, might have a new firmware loading into the UCD9222 for the Beta2 and production units.

13. Pull down the BSC_JTAG_RST# for normal operation of phy.

14. Add H5 for AMC spec

15. Add pull up resistor (R908, R909) to the inputs to the switch so that these signals are held high when the AMC JTAG interface is selected.

16. Add 22-ohm series termination resistors at the outputs MCMTXPMCLK and MCMRXFLCLK whichare HyperLink sideband signal clock outputs.

17. Add a temperature monitor to the unused TEMP2 input to the UCD9222

18. Add 4.7K pull-down resistors on the GPIO[15:1] pins and a 4.7K pull-up resistor on GPIO[0] sothat these pins are not floating after FPGA release.

19. Replace the 14-pin JTAG with the Spy-Bi-Wire interface .

20. Add 0 Ohm resisters on all power enable signals.

21.ADD R485 for DSP UARTTXD termination

22.DSP_PCIECLOCK was set from IN2.

23.Change R425 and R426 package from 0603 to 0402.

24.Change R58 package from 0603 to 0402.

25. To modify the title from CLOCK GEN1 to CLOCK GEN3

26. Change net name from lsenes-2A to isenes-2A

27. U4, U5, U16, U17 U8 change to SAMSUNG_K4B1G1646G

28. NL/U8

29. NL/R431, NL/R432, Add R435

DSPM-8301 A101-1 / 19C2830100

DSPM-8301 A103-1 / 19C2830102

1. Page26: Change mini-USB to through-hole type

2. Page13: Change the registers value to 2k ohms and the pull-up voltage to IO 1.8V on the DDR3 slew ratepins

3. Page22,23: Add the test points on unused clock inputs and outputs of CDCE62005s

4. Page10: Enable the expansion I2C by default, populate the registers of R160 and R161 for I2C connectionsbetween C6678 and AMC finger

6. AGND change to GND

7. Leave R160 and R161 as NL and add 2 more resistors on these nets connecting to AMC connector pins159 and 160. Install 0 ohms in these new resistors

DSPM-8301 A104-1 / 19C2830103

1. Remove R484 and R487 and cross-wire these signals to make the connections functionallymatch the C6670 EVMs

5. Page23: Modify the CLK2 (CDCE62005) inputs for the common HyperLink timing,TCLKB will be the PRI_REFinput and branch another one to the FPGA by two pairs. The 100MHz input from CLK3 CDCE62005 will bechanged to its SEC_REF input.

2. Change R433 to 10k, change R434 to 1.2k, change R12 and R17 from 0 ohm to 0.1uF

Title


Date: Sheet of


DSPM-8301E A104-1

History_0

B37 40Tuesday, March 13, 2012

Title


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DSPM-8301E A104-1

History_0


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DSPM-8301E A104-1

History_0


Documents

5 4 3 2 1 D D TI TMS320C6678 EVM Board Rev. 3A …wfcache.advantech.com/support/DSPM-8301E_EVM (6678)-3.0...5 5 4 4 3 3 2 2 1 1 D D C C B B A A 88E1111 DSP TMS320C6678 CVDD When power