552 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING …...packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies:

552 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 4, APRIL 2017

Design and Demonstration of a 2.5-D GlassInterposer BGA Package for High

Bandwidth and Low CostBrett M. D. Sawyer, Yuya Suzuki, Ryuta Furuya, Chandrasekharan Nair, Ting-Chia Huang,

Vanessa Smet, Kadappan Panayappan, Venky Sundaram, and Rao Tummala, Life Fellow, IEEE

Abstract— Consumer demand for mobile services is expected togrow with the continued proliferation of connected devices includ-ing smartphones, wearables, and Internet of things. As a result,high-performance computing systems that support the corenetwork and cloud infrastructures for these connected devicesrequire unprecedented die-to-die bandwidth at low latency. Toachieve next-generation performance requirements and to applyto commercial products, fundamental parameters for 2.5-Dinterposers are considered including: 1) high interconnect densityat short interconnect length; 2) low power consumption; and3) low packaging cost. The 2.5-D glass interposer described inthis paper is superior to silicon interposer in cost and electricalperformance, and to organic interposer in interconnect density.This paper describes a 2.5-D glass interposer as a ball grid array(BGA) package to achieve high bandwidth at low cost to improvebandwidth per unit watt signal power per unit dollar cost (BWF)compared to both silicon and organic interposers. Due to itshigh modulus and excellent surface finish, glass affords ultrafineline lithography to form high-density interconnects comparableto silicon, and the process described in this paper goes beyondsilicon back-end-of-line processes by implementing a double-sidesemi-additive process (SAP) at increased copper layer thickness.This thicker metallization results in reduced conductor lossesand improved bandwidth per channel compared to silicon. Inaddition, the low loss tangent of glass reduces dielectric lossesin nets requiring through vias including clock distribution andhigh-speed off-package signals. Availability of glass in thin panelas well as in roll-to-roll formats beyond 500 mm in size reducespackaging cost compared to 300-mm wafer silicon interposer.The focus of this paper is on the integration of three enablingtechnologies: 1) advanced SAP for high-density redistributionlayers (RDLs); 2) excimer laser ablation of RDL vias; and3) fine-pitch thermocompression bonding with copper pillar dieassembly—for a 2.5-D glass interposer at interconnect densitiescomparable to that of silicon to achieve terabit per second interdiebandwidth at highest BWF.

Index Terms— 2.5-D interposer, electronics packaging, excimerlaser via, glass interposer, high-performance computing (HPC),multichip modules, semi-additive process (SAP).

Manuscript received December 29, 2015; revised September 20, 2016;accepted January 9, 2017. Date of publication March 2, 2017; date of currentversion April 18, 2017. Recommended for publication by Associate EditorT.-C. Chiu upon evaluation of reviewers’ comments.

The authors are with the Packaging Research Center, Georgia Instituteof Technology, Atlanta, GA 30332 USA (e-mail: [email protected];[email protected]; [email protected]; [email protected];[email protected]; [email protected]; [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2017.2659700

I. INTRODUCTION

THE need for increased die-to-die bandwidth in high-performance computing (HPC) is a direct result of the

continued proliferation and projected growth of connecteddevices. Not only is the increase in personal mobile servicespushing HPC bandwidth, but machine-to-machine communi-cation required for a new era of Internet of things, autonomouselectric vehicles, and smart homes and cities is expected toresult in an unprecedented demand for bandwidth at low-est latency, lowest cost, and highest reliability [1]. As aresult, new packaging architectures and technologies, such as2.5-D integration as shown in Fig. 1, are needed to meet fivecritical requirements.

A. System Requirements

The five fundamental parameters in achieving the neededbandwidth in any commercialized package architecture includethe following:

1) high interconnect density at short interconnect length;2) low power consumption;3) low package layer count;4) low cost;5) high reliability.

Optimization of these parameters leads to a maximum band-width per unit watt signal power per unit dollar cost BWF suchthat

BWF = δr

η(r)C L2 (1)

where δ is the interconnect density in lines per unit lengthper layer, r is the data rate per line, η is the signal powerper unit length at a given data rate r , C is the fabricationcost per unit area per layer, and L is the interconnectlength. Increasing interconnection density is dependent ontwo factors: 1) decreasing redistribution layer (RDL) linepitch and width, and 2) decreasing chip-level bump pitch.Minimizing RDL line pitch requires a substrate with lowsurface roughness and total thickness variation, as well as highcoplanarity to improve lithography ground rules. Reducingchip-level bump pitch requires a substrate coefficient ofthermal expansion (CTE) matched to the IC to improvechip-level interconnect reliability, while also enabling direct

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SAWYER et al.: DESIGN AND DEMONSTRATION OF A 2.5-D GLASS INTERPOSER BGA PACKAGE 553

TABLE I

COMPARISON OF 2.5-D DIE INTEGRATION TECHNOLOGIES

Fig. 1. 2.5-D die integration on generic interposer or substrate with a high-density interconnect volume defined by L (interconnect length), w (I/O width),and N (number signal layers) through which BWF is defined.

attach to board by surface-mount technology (SMT) to reduceoff-package signal power. Decreasing die-to-die I/O powerrequires a reduction in conductor and dielectric losses forindividual signal lines, simultaneous switching noise andcrosstalk between adjacent lines, and die-to-die interconnectlength using advanced chip-level assembly technologies.Lowering packaging cost is achieved by reducing totalpackage layer count and reducing RDL processing cost.

B. Prior Art

The first implementation of a 2.5-D interposer was Xilinx’sstacked silicon interconnect (SSI) technology [2]. Stringent I/Odensity, signal latency, and signal power requirements deter-mined the need to integrate a split field-programmable gatearray die on a passive silicon interposer fabricated usinga 45- or 65-nm process node. In doing so, greater than10 000 die-to-die interconnects are used to provide one-fifth

the latency and 100× bandwidth per watt compared to stan-dard I/O packaging implementations. According to (1), themain constraint on SSI becoming a ubiquitous 2.5-D packag-ing solution is cost since back-end-of-line (BEOL) processesare used to fabricate the high-density RDL layers on a 300-mmwafer format. Furthermore, die-to-die interconnects are subjectto increased conductor losses due to a reduced line heightdetermined by BEOL design rule, while off-package intercon-nects with through silicon via (TSV) require high-resistivity(20 � cm) wafers to improve the electrical performance furtherincreasing packaging costs [3].

To address the scalability and cost of 2.5-D silicon inter-posers, alternatives have been proposed including organicinterposers and embedded interconnection bridges. Organicinterposer implementations include integrated thin-film high-density organic package (i-THOP) by Shinko and AdvancedPackage X (APX) by Kyocera [4], [5]. Embedded 2.5-Dsolutions require a passive die with high interconnect den-sity embedded within a substrate build-up layer. Embed-ded 2.5-D integration includes embedded silicon interconnectbridge by Intel and embedded glass interconnect carrier byUnimicron [6], [7]. These alternative solutions, however, areultimately limited according to (1) by interconnection den-sity on an organic substrate suitable for 2.5-D integration.Specifically, low-dimensional stability due to CTE mismatchaffects layer-to-layer registration that reduces line density perlayer, while warpage due to low modulus limits fine-line litho-graphy as well as fine-pitch chip-level assembly and reliability.

Current 2.5-D die integration technologies are comparedin Table I based on the aforementioned system requirements.Silicon-based 2.5-D interposer enables high interconnectdensity, but at high packaging cost and high layer count.A laminate substrate is required between the silicon interposerand system printed wiring board (PWB) due to the fixed CTE


Fig. 2. Glass interposer package schematic (not to scale) with detailed crosssection (looking from die gap into the die region) depicting fine-pitch RDL,blind microvia, and chip-level assembly combined with direct board attach toprovide low-power high-density die-to-die interconnection.

of silicon. Low chip-level reliability results without the use ofan intermediate substrate ball grid array (BGA). Package layercount is inherently increased without the ability for directSMT to PWB. Organic-based 2.5-D interposers using thin-filmtechnologies enable SMT to PWB and reduce RDL costs, butat the expense of I/O power and warpage at large body sizes.Organic-based 2.5-D interposers using an advanced laminatematerial set, while leveraging an established manufacturinginfrastructure, ultimately result in higher layer count and lackof scalability to fine pitch at large body size. Embedded 2.5-Dintegration addresses the scalability of silicon to large bodysize while enabling direct board attach, but still requires waferscale BEOL processing at higher packaging cost. Therefore,no existing 2.5-D technologies provide an optimal BWF.

Georgia Tech proposes a 2.5-D glass interposer packageas shown in Fig. 2, which satisfies the aforementionedsystem requirements. Specifically, the advantages of glass for2.5-D integration to maximize BWF according to (1) includethe following:

1) advanced semi-additive processes (SAP) with intercon-nect density comparable to silicon;

2) thick signal layer metallization on low-loss dielectric toreduce signal power;

3) tailorable CTE to enable large body glass BGA withSMT to PWB;

4) double-sided panel-scalable processes to reduce packag-ing cost;

5) high chip- and board-level reliability at less than50-μm chip bump pitch on glass BGA with noin-between substrate.

The proposed glass interposer package stack-up in Fig. 2minimizes losses in high-speed off-interposer nets using fine-pitch low-loss through package vias (TPVs) as described in [8]where TPV insertion losses less than 0.15 dB at f = 20 GHzare demonstrated. A glass interposer package with BGAand direct attachment to PWB can be achieved using SMT

described in [9] where a glass package stack-up, similarto Fig. 2, was demonstrated with high reliability at a bodysize up to 20 × 20 mm2. Direct attachment to board using aglass interposer BGA package decreases both interconnectionlength and layer count compared to silicon, thus improvingoff-package signal performance and power delivery.

Existing glass interposer technologies describedin [8] and [9] motivated the focus of this paper—items1), 2), and 4)—to demonstrate die-to-die interconnectdensity required for 2.5-D die integration at optimal BWF.Interconnect densities comparable to silicon are achievedusing a double-side SAP and chip-level interconnect bythermocompression bond (TCB) with copper pillar. Highline density by advanced SAP is achieved on glass due toits low surface roughness and low total thickness variationacross panel. Furthermore, SAP can reduce conductor lossand dielectric loss by fabricating large aspect ratio lines onlow-loss thin-film dielectrics.

The following sections describe the design, fabrication,and characterization of a low-cost 2.5-D glass interposer testvehicle (TV). Section II discusses specific interposer designrules showing how the proposed SAP and blind microviarules compare to silicon interposer line density. Section IIIgives an overview of the double-side fabrication process whileanalyzing specific RDL processes and their effect on fine-pitch interconnect yield. Section IV describes the 2.5-D chip-level assembly process used and provides time zero electricalyield results in the demonstration of the proposed 2.5-D glassinterposer package.

II. DESIGN

One of the critical enabling technologies for 2.5-Dintegration is line density. Line densities up to 10 000 die-to-die interconnections have been achieved using single-sidedwafer-scale processing. Section II-A discusses the design of alow-cost 2.5-D glass interposer, with comparable interconnectdensity enabled by an advanced fine-line SAP and microviaexcimer laser scan ablation.

A. Interconnect Density and Microvia Process

Processing nodes at which silicon interposers are beingfabricated employ a dual-damascene process, which enablesthe simultaneous fabrication of an embedded trace and blindmicrovia. In doing so, the need for large via capture padsin these interconnects layers is reduced and line density ismaximized for efficient die escape. The microvia technologyemployed in the proposed fabrication process must minimizecapture pad size to provide comparable line density betweendies at lowest packaging cost.

Lithography alignment, substrate dimensional stability, andvia drill alignment are the main contributing factors to the sizeof a microvia capture pad. The dependence on the number oflines n routed between two via capture pads of diameter � atpitch D is

n ≤ (D + P) − (2σ + � + W )

P(2)


Fig. 3. Isometric view of escape routing interconnect density at line pitch Pand width W where D is the minimum microvia pitch, � is the via landingpad diameter, and σ is the minimum line to pad spacing.

Fig. 4. Single-layer line density at 40-μm pad pitch and various via capturepad sizes from 5 to 25 μm as a function of SAP line pitch and width.

where σ is the pad to line space, P is the line pitch, W isthe linewidth determined by SAP design rules, and D isdetermined by the microvia process implemented as depictedin Fig. 3. Given the number of lines escaped and the inlineescape geometry shown in Fig. 3, the line density δ for a singlerouting layer is

δ = 1000 (n+1)

D(3)

where pad pitch D is in micrometers. The dependence onrouting density on capture pad size � = 5–25 μm is shownin Fig. 4 for D = 40 μm at various SAP line pitches andlinewidths. Based on this plot, the design rules for escaperouting and via capture pad were determined for the 2.5-Dglass interposer TV. Assuming that the minimum line pitchand width are 6 and 3 μm, respectively, via capture paddiameters between 15 and 20 μm are suitable to achieve100 lines/mm. At a signal bus width of 25 mm, 2500 die-to-die interconnections can be routed in a single layer, andidentical four routing layers are required to achieve the10 000 interconnections compared to BEOL processes.

TABLE II

DESIGN RULE SUMMARY FOR GLASS INTERPOSER TEST VEHICLE

Fig. 5. Glass interposer TV stack-up (not to scale) and design rulesummary—all units are in micrometers (μm). The TV stack-up is symmetrical.Interconnect geometries, dielectric layer names, and metal layer names areidentical on top and bottom sides.

B. 2.5-D Glass Interposer Test Vehicle Design

The 2.5-D glass interposer TV is designed in order todemonstrate the integration of advanced fine-line SAP andfine-pitch TCB to achieve interconnect densities required forhigh-performance applications on a larger than reticle sizecoupon. TV design rules are summarized in Table II, anda schematic of the 2 + 0 + 2 interposer stack-up includinglayer thickness and layer design name is shown in Fig. 5. Asymmetric dielectric and metal layer stack-up is used whereTPVs are not integrated into the design and the inner metallayer is fabricated on a polymer laminated glass core.

The targeted interposer size is 38 × 30 × 0.160 mm3. Totalinterposer thickness does not include C4 bumps and is basedon 100-μm and 10-μm glass core and dielectric build-up filmthicknesses, respectively. A single fine-line routing layer M2with 100 lines/mm is included with design rules based onthe line density analysis above. The target metal thicknessis 4 μm nominal resulting in a fine-line aspect ratio ofapproximately 1.33. High-density lines combined with dummymetal included on M2 are used to provide a copper density


of approximately 55%. Therefore, a dielectric thickness of7 μm is expected after lamination and cure resulting in a blindmicrovia aspect ratio less than one. A blind microvia diameterof 8 μm is based on an excimer laser drill process described insubsequent sections. The top metal layer M1 is implementedas a routing layer using a nonsolder mask defined (NSMD)solder resist opening (SRO). In addition to the fine-line routinglayer on M2, routing on the top metal layer is beneficial inreducing layer count and interposer cost where typical 2.5-Dimplementations limit the top metal layer to copper pillar forfine-pitch chip-level assembly.

C. Designs for Test

Multiple points for tests are required during TV fabricationto identify yield limiting processes. Due to the aggressive SAPand microvia stack-up design rules, test structures to determineindividual process yields for 6-μm pitch SAP and 40-μm pitchmicrovia laser ablation are included in the TV design.

Fine-pitch SAP test structures shown in Fig. 6(a) are aunique interdigitated structure mimicking a die-to-die inter-connect fanout. Open and short testing is used to determineif die escape and fanout lines are shorted. Variations for thistest structure include the number of die rows escaped, and itvaries from one die row up to six die rows. Given the designrules for M2, four lines are escaped per row at 40-μm pitch,and a maximum of 24 die-to-die interconnects is assessed in asingle test structure. Test points to analyze microvia ablationare shown in Fig. 6(b). Two-point probe tests are performedon microvias near the die corners after completing M1 SAP todetermine if proper interconnection is made between the toprouting layer and fine-line routing layer.

Fully integrated 2.5-D routing test structures are shownin Fig. 6(c). Two variations on these fully integrated teststructures are included to decouple dependence of chip-levelassembly. Four-point probe tests at 1a-1b as well as 3a-3b areused to determine the yield of fine-pitch RDL and assembly.Test points 2a-2b bypass assembly yield to analyze the inte-gration of fine lines and fine-pitch microvias. The TV designalso includes assembly test structures decoupled from fine-pitch RDL processes to critically examine 2.5-D TCB yield.

III. FABRICATION

All TV samples are fabricated using a double-side processflow on 150 × 150 × 0.100–0.300 mm3 glass panels. Thissection describes a low-cost process scalable from 150 togreater than 500 mm panel size to achieve high-density RDLsat 40-μm bump pitch and below. Yield critical technologiesincluded in the proposed panel-scalable process are thenanalyzed based on the aforementioned DFT structures.Contributing factors to reducing the fabrication costs inaddition to potential economies of scale include the useof high-throughput packaging processes, low-temperaturedry film polymers for build-up dielectrics, and high routingdensity to reduce layer count.

A. Panel-Scalable Process Flow

The process flow used to fabricate the 2.5-D glass interposerTV is summarized in Fig. 7. The first step in fabricating the

Fig. 6. Test structures to assess yield of critical fabrication processesincluding (a) fine-line SAP by a unique comb structure that mimics a die-to-die escape routing structure, (b) fine-pitch microvia ablation, and (c) fullyintegrated 2.5-D routing test structures including fine-line SAP + fine-pitchmicrovia + fine-pitch chip-level assembly.

fine-line routing layer is vacuum lamination of a dry thin-filminterlayer dielectric (ILD) with inherent low surface roughnessonto the glass panel, which has been treated with a silane layerto increase polymer adhesion. In doing so, the high degree ofcoplanarity and local surface roughness required for fine-linelithography is achieved. This is followed by the depositionof a seed layer. Seed layer deposition techniques employed


Fig. 7. Panel-scalable process flow to fabricate a low-cost 2.5-D glassinterposer. Fabrication processes (b)–(e) detail a SAP with a novel seed layeretch required for high line density on M2. A similar SAP is repeated in process(g) to complete M1.

include an electroless copper wet plating process and a Ti–Cuphysical vapor deposition (PVD), where an electroless processis preferred due to its direct compatibility with a double-sideprocess flow. After seed layer deposition, fine-line SAP is per-formed. A dry thin-film photoresist is laminated and patternedusing i-line projection lithography. The projection lithographysystem affords a circular exposure field at a diameter ofapproximately 100 mm with a 70 × 62-mm2 high-resolutionarea with no demagnification. Fine-pitch RDL patterns arerestricted to this high-resolution area in the panel layout. Afterlithography, electrolytic plating is used to form high-densitytraces followed by stripping of the resist layer. In addition tolow surface roughness, seed layer etching is critical to realizea 6-μm pitch RDL. To improve fine-line yield, a differentialspray etching process is used to remove the seed layer. Fine-pitch microvias are used to interconnect the top routing layer

Fig. 8. SAP fabrication results using an electroless copper seed layerafter (a) dry film resist lamination, (b) electrolytic plating and resist strip,and seed layer etch. (c) Top view of panel. (d) Coupon cross section. Notethat observations of discontinuous lines were required as a part of the DFTstructures and do not indicate processing errors.

with the high-density layer. These microvias are formed by apanel-scalable excimer laser scan ablation technique followingvacuum lamination of the second ILD (ILD1) using similarconditions as ILD0. To improve coplanarity and top routinglayer yield, a hot press is implemented to planarize ILD1. Thetop routing layer is formed after via ablation using similar SAPconditions as the high-density routing layer. As a part of thisSAP, electrolytic plating is used to fully fill the microvias. Thisis achieved by maintaining a blind microvia aspect ratio ofless than one. Electrolytic plating optimization was performedto ensure dimpling and/or dishing does not occur in the viacapture pad on M1. The glass interposer panel fabricationis completed after NSMD passivation and electroless nickelimmersion gold (ENIG) surface finish. Using a high-resolutionphotoimageable thin-film dielectric enabled passivation of thefine-pitch substrate pads to prepare for chip-level TCB.

B. Fine-Line SAP

Fine-pitch RDL fabrication results using an electrolessseed layer deposition SAP are summarized in Fig. 8. Maskcompensation of 0.5–1.0 μm was used to improve line shapeafter seed layer etch. Therefore, two mask variations to real-ize a 6-μm pitch RDL at 3-μm line were used including4-μm line at 2-μm space and 3.5-μm line at 2.5-μm space.Mask compensation increases risks of resist collapse and/ordelamination after development. Lithography results shownin Fig. 8(a) after resist development and plasma descumindicate no collapse or delamination in the photoresist layer.After electrolytic plating to form RDL traces, processingchallenges exist when stripping the resist layer. This is dueto the high 1.33 aspect ratio of the fine-pitch traces affordedusing SAP and desired for reduced interconnect parasitics.Fine-pitch RDL after resist stripping is shown in Fig. 8(b) withno indication of resist residue. The final step in SAP is seed


Fig. 9. Fine-line SAP fabrication yield comparison using an electrolesscopper versus a sputtered Ti–Cu seed layer. Test structure nomenclature onthe horizontal axis indicates that all test structures included are substrate-onlyfine-line structures (i.e., “SUB-NA-FL”). The first digit indicates test structurelocation on the coupon. The last two digits indicate the number of fine linesincluded in the die-escape comb structure (e.g., “02” indicates there are twodie rows escaped where there are four lines escaped per row, or a total ofeight lines).

layer etching. While process steps to maintain 3-μm linewidthwere taken including mask compensation and differential sprayetch, 0.2-μm line narrowing is observed as indicated by theresults in Fig. 8(c) and (d).

Fine-line yield data shown in Fig. 9 indicate that seed layeretching proves to be the critical process step. With increas-ing line density, fine-line yield shows a distinctive rollofffrom 0.90 to 0.60 when the number of interconnects increasedfrom 12 to 16 traces in the test structure. Underetchingwas determined to be the root cause of failure upon panelinspection, which showed residual seed layer in high-densityrouting areas.

This residual seed layer is due to copper anchoring duringelectroless copper plating. Panel cross sections reveal submi-crometer anchors in the seed layer as shown in Fig. 8(d). Theseanchors are a result of a desmear step used as a part of theelectroless deposition process. Desmear was shown to increasepolymer surface roughness up to Rz = 1.0 μm. Therefore,to remove anchors in the seed layer, a tradeoff in etchingtime exists. Complete removal of the seed layer results inoveretching of fine lines. On the other hand, when the etchingtime is reduced, inadequate seed layer removal results in fine-line shorting and in turn reduced yield.

Modifying fine-line SAP to use a Ti–Cu PVD seed layerimproves yield as shown in Fig. 9. Titanium acts as an adhe-sion layer to the ILD, mitigating the need for desmear. As aresult, filler materials are not removed from the underlyingILD, and low surface roughness necessary for fine-line yieldis maintained. For each variation in fine-line test structures,a PVD seed SAP resulted in higher yield above 0.80 comparedto an electroless seed SAP.

C. Microvia Excimer Laser Ablation and Top Metallization

Microvia fabrication was achieved using a XeCl excimerlaser (λ = 308 nm) scan ablation process. To increase process

throughput when scaling to large panel processing, a scanablation technique is employed instead of a point-to-point laserablation. The scan ablation method utilizes a quartz maskwith sputtered aluminum openings to simultaneously ablatemicrovias over the entire 38 × 30-mm2 coupon area, whichincluded a total of 14 704 vias (7520 at 40-μm inline pitchand 7184 at 150-μm inline pitch). Optical inspection andprofilometry data were used to confirm via opening and viaside-wall angle greater than 80°.

As described earlier, a challenge in implementing a low-cost2.5-D interposer technology is minimizing microvia capturepad size in order to increase interconnect density. Fig. 10(a)demonstrates the overlay accuracy achieved using the scanablation process. The alignment process marker in the cutoutof Fig. 10(a) represents five capture pad diameters rangingfrom 18 down to 10 μm. This process marker was includedin the corner of each coupon and was used to confirm lessthan 2-μm overlay accuracy without alignment compensationduring via ablation.

When plating the top routing layer M1, fully fillingthe microvia without significant dimpling or dishing wasconsidered critical for via-in-pad assembly yield. In scalingthe RDL technologies included in the fabrication of this TVto multiple fine-line layers, fully filled via plating is criticalto enable stacked microvia and further increase interconnectdensities. Fig. 10(b) and (c) shows optical profilometry dataobtained after M1 plating. Fig. 10(c) shows a micrographof two capture pads included in one of the microvia DFTstructures. Fig. 10(b) shows the two respective pad profilesindicating submicrometer topography at the top of the pad.Therefore, plating conditions are sufficient for via-in-padassembly. Using DFT structures shown in Fig. 6(b), microviayield was determined. Since a two-point probe methodwas used, a pass condition for any given DFT structure isconsidered R < 5 �. Increased resistance is expected due toparasitic trace and contact resistance. An average panel yieldof 0.88 was observed based on this test condition.

IV. ASSEMBLY

Sequential pick-and-place thermocompression bond withcopper pillar and a post-applied capillary underfill is used for2.5-D chip-level assembly at 56-μm bump pitch and 100-μmdie spacing. The assembled die is 10 × 10 × 0.2 mm3 witha four-row 80-/40-μm staggered pin-out at the die peripheryand a 150-μm full array interior pin-out (5456 total bumps).On-chip copper RDL patterns are intended for electrical daisychain connectivity tests only. The bump stack-up is 17/3/16μm Cu/Ni/SnAg with a 28-μm bump diameter. The followingdescribes the 2.5-D panel-level assembly process and resultson 100- and 300-μm thick glass panels.

A. 2.5-D Chip-Level Assembly

After completing glass interposer panel fabrication as shownin Fig. 7, bonding areas are treated using an acetone andisopropyl alcohol (IPA) clean, and a prebake is applied.Directly prior to die assembly, a no-clean flux is applied atthe bonding site, and the panel is placed on the assembly


Fig. 10. (a) Representative blind microvia drill alignment across panel,(b) optical profilometry data after SAP2, and (c) substrate pads for chip-levelassembly and course escape routing structures on M1 layer.

stage, which is kept at T = 70 °C in stand-by. Chip-level assembly is then carried out according to the processflow shown in Fig. 11. The first die is picked and placedusing a 10 × 10-mm2 flat tool head, and stage temperatureis increased to T = 120 °C directly prior to and duringbonding. Thermocompression bond of the first die is carriedout where the tool head temperature is ramped at 6 K/s to

Fig. 11. (a) and (b) Sequential pick-and-place TCB of 10 mm × 10 mmdie at 100-μm die gap followed by (c) dual-dispense capillary underfill and(d) time zero electrical open and short testing.

T = 390 °C. After a t = 3-s nominal dwell time, the toolhead is cooled to T = 70 °C at 6 K/s. A constant bond forceof F = 6 N is applied throughout the heating profile. Thesecond die is assembled using similar TCB process conditionsat a 100-μm die gap. This is a nominal die gap distance asdie alignment and electrical die-to-die interconnect length isultimately determined using complementary fiducials on thecoupon and die.

Die assembly is checked prior to underfill dispense usingtest structures routed on M1 and die RDL layers only. AfterTCB is confirmed by open/short testing, bonding areas aretreated using an acetone and IPA clean. The assembled panelis then placed on a hot plate at T = 90 °C prior tounderfill dispense. Underfill dispense volume is optimized toprevent overburden in the die gap. Also, to mitigate the riskof underfill voiding, a dual-point dispense technique shownin Fig. 11(c) is used where a dot underfill dispense is appliedat opposing die edges. Die assembly is completed after a post-cure at T = 165 °C for t = 1.5 h.


Fig. 12. 2.5-D chip-level assembly results at 56-μm pitch (80-/40-μm pin-out) with cross-sectional views. (a) Chip-level assembly viewing die gap.(b) Chip-level assembly viewing fine-line routing layer. (c) Via-in-pad dieassembly detail.

B. Demonstration of 2.5-D Chip-levelAssembly on Glass Interposer

Fine-pitch 2.5-D assembly on a 100- and 300-μm thickglass interposer with a high-density RDL fabricated using low-cost processes was demonstrated. Fig. 12(a) and (b) showsassembled coupon cross sections where Fig. 12(a) is lookingfrom the coupon edge toward the 2.5-D die gap and Fig. 12(b)is viewing inward from the die gap toward the high-densityrouting layer. Inspecting the 2.5-D die gap indicates thatthe postapplied capillary underfill flows into the gap withoutoverburden. Furthermore, the detailed micrograph of the fine-pitch solder joint in Fig. 12(c) indicates that a good chip-levelinterconnect is formed with minor solder depletion. This solderdepletion is due to ENIG overplating, which is a result of

Fig. 13. Completed 2.5-D glass interposer panel after fine-pitch TCB chip-level assembly depicting fine-line die-to-die daisy chain test structure yieldmap. Yield map shows average yield based on coupon location.

palladium poisoning of ILD during M1 SAP. Line narrowingof the high-density traces is observed in Fig. 12(b) similar tothe results observed after fine-line SAP in Fig. 8(d). Detailedcross sections confirm high-accuracy microvia ablation andfully filled via plating with no apparent dimpling or dishing.

After completing panel-level 2.5-D assembly, time zeroelectrical yield was measured across three panels. The testsample size included: 1) one 300-μm-thick panel fullypopulated with a total of eight assembled coupons; 2) one300-μm-thick panel partially populated with a total of sevenassembled coupons; and 3) one 100-μm-thick quarter-panelwith two assembled coupons. Two test structure variationswere analyzed including: 1) die corner daisy chain (two struc-tures per coupon) and 2) fine-line die-to-die daisy chain(four structures per coupon). Test structure 1) includes routingon M1 and die RDL only and is used to assess TCB yield.Test structure 2) is representative of a die-to-die interconnectand assesses integration of the advanced interposer fabricationand assembly processes described. The pass condition foreach test structure was a daisy chain resistance R < 50 �.An elevated pass condition is used based on coupon crosssections indicating solder depletion and line narrowing, whichmay increase chip-level interconnection resistance.

One coupon on panel 2) exhibited 1.00 yield for all teststructures considered, indicating successful demonstration offine-pitch RDL and chip-level assembly for 2.5-D die integra-tion on a low-cost glass interposer. The average yield of teststructure 1) for the 17 coupons tested was 0.875 indicatinggood 2.5-D TCB despite solder depletion. Test structure 2)results are summarized in Fig. 13 by average yield based oncoupon position. Panels considered for the reported time zeroyield analysis used an electroless SAP. Therefore, overetchingof interconnects during seed layer removal on M2 as indicatedin Fig. 9 is considered the yield limiting process.

V. CONCLUSION

In this paper, the design and demonstration of a 2.5-Dglass interposer BGA package TV capable of meeting all


system requirements to maximize bandwidth per unit wattsignal power per unit dollar cost is described. The focus of thispaper is the analysis of advanced SAP and chip-level assem-bly processes to provide interconnect density comparable tosilicon at shortest interconnect length using the following:

1) low-cost double-side SAP to fabricate a 6-μm pitchRDL;

2) panel-scalable excimer laser scan ablation to fabricateRDL via at 40-μm inline pitch;

3) panel-level TCB 2.5-D die assembly at 56-μm bumppitch and 100-μm die gap.

Routing studies performed show that these RDL processes arecapable of achieving a line density δ = 100 lines/mm. Up to10 000 die-to-die interconnections can be achieved at this linedensity and bus width w = 25 mm using the same number ofsignal routing layers as silicon.

Specific RDL structures were designed for tests during thedouble-side fabrication process. Panel-level tests indicated thatthe removal of the electroless copper seed layer during SAPis critical to fine-line yield. Optimizing SAP etch time orimplementing a PVD SAP was shown to improve 6-μm pitchRDL yield beyond 0.80. Tests also indicated that fine-pitchmicrovias were fabricated at less than 2-μm overlay accuracywithout drill alignment compensation, and demonstrated themicrovia stack-up can be scaled further to increase routingdensity. Furthermore, electrolytic plating of microvias demon-strated fully filled via capable of via-in-pad assembly, andstacked via when scaling the RDL technologies discussed tomultilayer high-density routing.

Thermocompression bond 2.5-D chip-level assembly wasperformed on 100- and 300-μm-thick glass at high yieldabove 0.80 on multiple panels. Failure analysis using crosssection revealed that solder depletion due to ENIG overplating.Chip-level assembly can be improved with optimized palla-dium strip after SAP.

Fully integrated fine-pitch RDL and 2.5-D chip-levelassembly tests indicated up to 1.00 yield, and thusdemonstrates a low-cost 2.5-D glass interposer to achieveinterconnect density comparable to silicon. Analysis of eachof the aforementioned glass interposer technologies using DFTstructures indicates that seed layer etching optimization duringfine-line SAP was critical to increase high-density interconnectyield. Therefore, the 2.5-D glass interposer BGA packagedescribed in this paper has great potential to provide the die-to-die bandwidth required in next generation HPC systems at amaximum BWF.

ACKNOWLEDGMENT

The research results described are a part of industry consor-tium program at Georgia Tech Packaging Research Center. Theauthors would like to thank all the consortium member com-panies and supply chain partners in supporting this researcheffort.

REFERENCES

[1] B. Bottoms, “Maintaining the pace of progress as we approach theend of Moore’s law: New materials, new processes, new architectures,”in Proc. Int. Symp. Microelectron., 2015, pp. S1–S57.

[2] K. Saban, “Xilinx stacked silicon interconnect technology deliversbreakthrough FPGA capacity, bandwidth, and power efficiency,” Xilinx,San Jose, CA, USA, White Paper WP380 (v1.2), 2012.

[3] N. Kim, C. Shin, D. Wu, J. Kim, and P. Wu, “Performance analysisand optimization for silicon interposer with through silicon via (TSV),”in Proc. Conf. SOI, Oct. 2012, pp. 1–2.

[4] K. Oi et al., “Development of new 2.5D package with novel integratedorganic interposer substrate with ultra-fine wiring and high densitybumps,” in Proc. Electron. Compon. Technol. Conf. (ECTC), May 2014,pp. 348–353.

[5] M. Ishida, “APX (Advanced Package X)—Advanced organic technologyfor 2.5D interposer,” presented at the Electron. Compon. Technol.Conf. (ECTC), Orlando, FL, USA, May 2014, pp. 27–30.

[6] M. Deo, “Enabling next-generation platforms using Altera’s 3Dsystem-in-package technology,” Altera, San Jose, CA, USA,Tech. Rep. WP-01251-1.0, 2015.

[7] D. C. Hu, Y. P. Hung, Y. H. Chen, R. M. Tain, and W. C. Lo,“Embedded glass interposer for heterogeneous multi-chip integration,”in Proc. Electron. Compon. Technol. Conf., May 2015, pp. 314–317.

[8] V. Sukumaran et al., “Design, fabrication, and characterization ofultrathin 3-D glass interposers with through-package-vias at same pitchas TSVs in silicon,” IEEE Trans. Compon., Packag., Manuf. Technol.,vol. 4, no. 5, pp. 786–795, May 2014.

[9] Q. Xian, P. M. Raj, V. Smet, and R. Tummala, “Direct SMT interconnec-tions of large low-CTE interposers to printed wiring board using coppermicrowire arrays,” IEEE Trans. Compon., Packag., Manuf. Technol.,vol. 5, no. 11, pp. 1709–1719, Nov. 2015.

Brett M. D. Sawyer received the B.S. degree inelectrical engineering from Old Dominion Univer-sity, Norfolk, VA, USA, in 2011, and the M.S.degree from the Georgia Institute of Technology,Atlanta, GA, USA, in 2014, where he is currentlypursuing the Ph.D. degree in electrical engineering.

He joined the 3-D Systems Packaging ResearchCenter, Georgia Institute of Technology, in 2013.This work has applications mainly in high per-formance computing modules including wide I/Ologic-memory and 400 GbE CDFP to provide cloud

services to mobile devices. His current research interests include the designand demonstration of a 2.5-D glass interposer package to achieve 1-TB/s die-to-die and 400-Gb/s off-interposer bandwidths.

Yuya Suzuki received the B.S. and M.S. degreesin applied chemistry from the University of Tokyo,Tokyo, Japan, in 2005 and 2007, respectively. He iscurrently pursuing the Ph.D. degree with the Depart-ment of Materials Science and Engineering, GeorgiaInstitute of Technology, Atlanta, GA, USA.

He joined Zeon Corporation, Tokyo, in 2007,as a Research Engineer. He is currently with the3-D Packaging Research Center, Georgia Instituteof Technology. His current research interests includethe development of glass interposer and passive

embedded RF module using low loss polymer material, and polymer synthesis,polymer processing, and organic-inorganic hybrid materials.

Ryuta Furuya received the B.S. and M.S.degrees in physics from the University ofTokyo, Tokyo, Japan, in 2010 and 2012,respectively, with a focus on star formationprocesses.

He joined USHIO Inc., Yokohama, Japan, in2012, and is currently with the 3-D PackagingResearch Center, Georgia Institute of Technology,Atlanta, GA, USA, as a Visiting Engineer. Hiscurrent research interests include the developmentof projection lithography process for large-scale

panel-based interposer technology, and the projection lithography optics,chip-to-chip optical interconnect, and energy harvesting.


Chandrasekharan Nair received the bachelor’sdegree in polymer engineering and technology fromthe Institute of Chemical Technology, Mumbai,India, in 2013, with a minor in chemical engineer-ing. He is currently pursuing the Ph.D. degree inmaterials science and engineering with the 3-D Pack-aging Research Center, Georgia Institute of Tech-nology, Atlanta, GA, USA, under the guidance ofProf. R. Tummala.

As a Graduate Research Assistant in the Low CostGlass Interposer Program, he was involved in the

reliability evaluation of novel polymer dielectric materials and processes tobuild next-generation redistribution layer for panel scale interposers/high den-sity packages. His current research interests include polymer-metal interfaces,package substrate reliability studies, and polymer characterization.

Ting-Chia Huang received the master’s degreein material science and engineering from NationalTaiwan University, Taipei, Taiwan, in 2012, with afocus on solder interfacial reaction and electromigra-tion. He is currently pursuing the Ph.D. degree withthe 3-D Packaging Research Center, Georgia Insti-tute of Technology, Atlanta, GA, USA, conductedby Prof. R. Tummala.

As a Graduate Research Assistant in Interconnec-tions and Assembly Program, he was involved inthe development of off-chip interconnections with

thermocompression bonding for fine pitch and high reliability, includingthe scopes of solder-capped microbumps, solder-liquid interdiffusion (SLID)bonding, preapplied underfill process development, and finite element analysisfor stress management. He is also the first inventor of the patent “MetastableInterconnections Structure for ultrafast SLID bonding.” His currentresearch interests include metallurgical reactions, packaging reliability, andfinite-element modeling.

Vanessa Smet received the B.S. and M.S. degrees inapplied physics from the École normale supérieureParis-Saclay, Cachan, France, and the University ofParis XI, Orsay, France, and the Ph.D. degree inelectronics from the University of Montpellier 2,Montpellier, France, in 2010, focusing on powercycling reliability of IGBT power modules in harshenvironment.

She was a Post-Doctoral Researcher with theTyndall National Institute, Cork, Ireland, where shewas involved in novel high-temperature high-power

die-attach solutions for power switches with Ag-CNTs composites andmicroBGA assembly. She is currently an Associate Research Professor and theProgram Manager for the Interconnections and Assembly Industry Programwith the 3-D Systems Packaging Research Center (PRC), Georgia Instituteof Technology, Atlanta, GA, USA. At PRC, she provides leadership todevelop and demonstrate new interconnection and assembly technologiesbeyond solders for advanced 2.5-D and 3-D packaging, as well as high-power applications, with a focus on manufacturability and technology transferto industry. She has coauthored over 30 journal and conference publicationsand two patents with others pending. Her current research interests includepower electronics, finite element modeling, 3-D integration, interconnectionand assembly processes, SLID / TLP bonding, all-Cu interconnections, low-temperature bonding, and reliability.

Kadappan Panayappan received the bachelor’sdegree from Anna University, Chennai, India,in 2006, the master’s degree from IIT Kahragpur,Kahragpur, India, in 2008, and the Ph.D. degree fromThe Pennsylvania State University, State College,PA, USA, in 2013.

He is a Research Engineer with the 3-D PackagingResearch Center, Georgia Institute of Technology,Atlanta, GA, USA, focusing on electrical design. Hiscurrent research interests include signal and powerintegrity, power delivery networks, antennas, high-

speed interconnects, and computational electromagnetics.

Venky Sundaram received the B.S. degree fromthe Indian Institute of Technology (IIT) Mum-bai, Mumbai, India, and the M.S. and Ph.D.degrees in materials science and engineering fromthe Georgia Institute of Technology, Atlanta,GA, USA.

He is the Director of Research and Industry Rela-tions with the 3-D Systems Packaging ResearchCenter, Georgia Institute of Technology. He is theProgram Director for the Silicon and Glass Inter-poser industry consortium with more than 25 active

global industry members. He is a globally recognized expert in packagingtechnology and a Co-Founder of Jacket Micro Devices, an RF/wireless startupacquired by AVX. He has authored more than 100 publications and holds morethan 15 U.S. patents. His current research interests include system-on-packagetechnology, 3-D packaging and integration, ultrahigh-density interposers,embedded components, and systems integration research.

Dr. Sundaram was a recipient of several best paper awards. He is theCo-Chairman of the IEEE Components, Packaging, and Manufacturing Tech-nology Technical Committee on High Density Substrates and is on theExecutive Council of International Microelectronics and Packaging Societiesas the Director of Education Programs.

Rao Tummala (M’88–SM’90–F’93–LF’16)received the B.S. degree from the Indian Institute ofScience, Mumbai, India, and the Ph.D. degree fromthe University of Illinois at Urbana–Champaign,Urbana, IL, USA.

He is a Distinguished and Endowed ChairProfessor and a Founding Director of NSF ERCwith the Georgia Institute of Technology (GeorgiaTech), Atlanta, GA, USA, pioneering Moore’s Lawfor System Integration. Prior to joining GeorgiaTech, he was an IBM Fellow, pioneering the first

plasma display and multichip electronics for mainframes and servers. He hasauthored about 500 technical papers, holds 74 U.S. patents, and inventions.He has also authored the first modern Microelectronics Packaging Handbook,the first undergraduate textbook Fundamentals of Microsystems Packaging,and the first book introducing the system-on-package technology.

Prof. Tummala was a recipient of many industry, academic, andprofessional society awards, including Industry Week’s Award for improvingU.S. competitiveness, the IEEE’s David Sarnoff, the IMAPS’ Dan Hughes,the Engineering Materials from ASM, and the Total Excellence inManufacturing from SME. He is also a recipient of the Distinguished AlumniAwards from the University of Illinois at Urbana–Champaign, the IndianInstitute of Science, and Georgia Tech. He was the President of the IEEEComponents, Packaging, and Manufacturing Technology and the InternationalMicroelectronics and Packaging Societies and is a member of the NationalAcademy of Engineering. In 2011, he received the Technovisionary Awardfrom the Indian Semiconductor Association and the IEEE Field Awardfor contributions in electronics systems integration and cross-disciplinaryeducation.

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552 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING …...packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: