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5 bit binary to 1 of 32 select decoder (to be used in 5 bit

DAC)Dan Brisco, Steve Corriveau

Advisor: Dave Parent

14 May 2004

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Agenda

• Abstract• Introduction

– Why– Simple Theory– Back Ground information (Lit Review)

• Summary of Results• Project (Experimental) Details• Results• Conclusions

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Abstract

• We designed the circuit to operate at 200MHz with room for extra logic stages for the analog conversion yet to be added.

• We needed to assure that only one output was selected at a time without having to clocking the outputs.

• Our design is 171.6um X 534.6um and uses 1.02mW of power.

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Introduction

• A 5 bit DAC as IP will be very useful for DSP projects in the future.

• Design a decoder with symmetric rise and fall times and minimal settling errors.

• We have laid out our circuit utilizing the best timing path even though we calculated and tested it for the worst case.

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Previous Work

• 2003 Gonzalez, Yu & Korbes. 6-bit Analog to Digital / Digital to Analog Converter.

• 1997 Baker, Li & Boyce. CMOS Circuit Design, Layout, and Simulation.

• 1987 Allen & Holberg. CMOS Analog Circuit Design.

• 2003 Kang & Leblebici. CMOS Digital Integrated Circuits.

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Project Summary• A 6 bit DAC was presented last year that had a

non-linear output with possible reasons being.– Timing issues

– More than one output being selected

– Settling time causing selection of the wrong output.

• Our design has 5 logic levels.– We designed for 10 to allow for the analog conversion

later.

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Project Details• The 5 to 32 bit decoder utilized 4 base cells.

– Nand3, Inverter and Nand2 were used to build a Nand5.

• Nand2 & 3 and Inv cell heights are 15.9um.

– Mux based DFF with nRST was used to hold the input logic and fan out the signals to 32 Nand5’s for decoding.

• DFF cell height is 36.0um.• Nand5 cell height is 29.4um.

– The whole design is 171.6um X 534.6um.

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Longest Path Calculations

nsns

PHL 5.10

5 Note: All widths are in microns

and capacitances in fF

Logic Level Gate

Cg to Drive #CDNs #CDPs #LNs #LPs

WN (H.C)

WP (H.C)

WN (S)

WP (S)

WN (L)

WP (L)

Cg of Gate

1 Nand2 30.00 3 2 2 1 0.42 0.71 2.09 1.79 2.09 1.79 6.602 Inv 6.60 1 1 1 1 0.12 0.20 1.50 2.56 1.50 2.56 6.913 Nand3 6.91 5 3 3 1 0.12 0.20 1.43 0.81 2.56 1.50 110.634 Dff Nand 110.63 1 1 2 1 1.57 2.78 9.44 8.34 9.44 8.34 15.09

4.5 Dff Slave 15.09 1 1 1 1 0.53 0.95 5.10 9.54 5.10 9.54 18.145 Dff Nand 18.14 1 1 2 1 1.82 3.21 5.45 4.82 5.45 4.82 17.42

5.5 Dff Master 17.42 1 1 1 1 0.61 1.08 3.06 5.41 3.06 5.41 14.30

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5 to 32 bit Decoder

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5 to 32 bit Decoder

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Mux DFF with nRST

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DFF Master

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DFF Slave

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Mux DFF with nRST

D

CLK

nRST

Q

nQ

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Nand5

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Nand5

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Verification

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Verification

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Simulations

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Simulations

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Cost Analysis

• We estimate the time we spent on each phase of the project to be,– verifying logic – 16hrs– verifying timing – 16hrs– Layout – 32hrs– post extracted timing – 4hrs– Log-in/out – 8hrs

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Conclusions• This project provided a good basis for IC design.

– We looked at several ways to implement and optimize the design.

– Working through the design flow as a team provided great a experience that will help with working on the job.

• We were able to design a very clean select 1 output.

• There is some repeated logic that could be taken out if cell based design wasn’t part of the specification.

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Lessons Learned

• Start early.

• Be ready to redesign from scratch.

• Don’t hurry.

• A steady pace, with lots of reflecting, works best.

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Acknowledgements

• Thanks to Denise and Shannon for putting up with us and encouraging us to study.

• Thanks to Cadence Design Systems for the VLSI lab.

• Thanks to Synopsys for Software donation.

• Professor Parent and his many consults.

• Grant us peace.