08 decoder

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  • Decoder

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  • *DecoderABCO0O1O2O3O4O5O6O700010000000001010000000100010000001100010000100000010001010000010011000000010111000000012-to-4,3-to-8,n-to-2n

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  • *Decoder

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  • *Design Using DecoderApplications:

    Implementing General LogicAny combinational circuit can be constructed using decoders and OR gates!F1 = A' B C' D + A' B' C D + A B C DF2 = A B C' D' + A B CF3 = (A' + B' + C' + D')Example:

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  • *Active LowDecoder with

    Active Low Enable Active Low Outputs

    GABY0Y1Y2Y31XX11110000111001101101011010111110

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  • *74x139 dual 2-to-4 decoder

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  • *74x138 3-8 Decoder

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  • *74x138 3-8 Decoder

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  • *Using 3-State BuffersCan use 3-state buffers to share a single line for several devices.Decoder guarantees that no two buffers are on simultaneously.Some decoders have hi-Z outputs.

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  • *DecodersCan build a decoder by smaller decodersS2 S1 S0 S3

    EnbA B C D

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  • *DecodersHow to build a 5-32 decoder by using 4-16 and 2-4 decoders?

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  • *DecodersDecoder: a more general term

    Our focus was on binary decoders

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  • *7-Segment DecoderSeven-segment display:7 LEDs (light emitting diodes), each one controlled by an input1 means on, 0 means offDisplay digit 3?Set a, b, c, d, g to 1Set e, f to 0

    d

    a b c e f g

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  • *7-Segment Decoder

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  • *7-Segment Decoder7-Segment Decoder:Input is a 4-bit BCD code 4 inputs (A, B, C, D).Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent to be displayed.Example: Input: 0000BCDOutput: 1111110 (a=b=c=d=e=f=1, g=0)

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  • *BCD-to-7Segment Truth Table

    11100X001117X01111101106101101101015011001101004111100100113110110100102011000000011111111000000abcdefgABCDDigitabcdefgABCDDigitXXXXXXX1111

    XXXXXXX1110

    XXXXXXX1101

    XXXXXXX1100

    XXXXXXX1011

    XXXXXXX1010

    111X01110019111111110008??101111111100001110011

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  • *K-mapsa = A + B D + C + B' D'b = A + C' D' + C D + B'c = A + B + C' + Dd = B' D' + C D' + B C' D + B' Ce = B' D' + C Df = A + C' D' + B D' + B C'g = A + C D' + B C' + B' C

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  • Encoder

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  • *EncoderEncoder:

    the inverse operation of a decoder.Has 2n input lines and n output lines. The output lines generate the binary equivalent of the input line whose value is 1.

    I0I1I2I3z1z24-2BinaryEncoder

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  • *Encoder

    O0 O1 O2A B C S2 S1 S0 O3O4O5O6O7

    I0 I1 I2A B C Z2 Z1 Z0 I3I4I5I6I7

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  • *Encoder Circuit DesignExample:

    8-3 Binary EncoderA0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D7

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  • *Encoder Circuit

    With EnableWith Acknowledge

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  • *Application

    The number of inputs: large fewer lines

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  • *Encoder Design IssuesOnly one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination(for example, if D3 and D6 are 1 simultaneously, the output of the encoder will be 111.A0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D7

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  • *Priority EncoderMultiple asserted inputs are allowed; one has priority over all others.

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  • *K-Maps

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  • *Circuit

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  • *8-3 Priority Encoder

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  • *74x148Features:

    inputs and outputs are active low.EI_L must be asserted for any of its outputs to be asserted.GS_L is asserted when the device is enabled and one or more of the request inputs is asserted. (Group Select or Got Something. )EO_L is an enable output designed to be connected to the EI_L input of another 148 that handles lower-priority requests. It is asserted if EI_L is asserted but no request input is asserted; thus, a lower-priority 148 may be enabled.

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  • *74x148 Truth Table

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  • *Circuit Diagram

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  • *Datasheetshttp://www.techlearner.com/C&D/index.htmhttp://users.otenet.gr/~athsam/database.htmSome sample datasheets in the course site.

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