607 Switched-Capacitor S-H and Switches

7/28/2019 607 Switched-Capacitor S-H and Switches

1/34

Analog and Mixed-Signal Center, TAMU

TRACK & HOLD

ARCHITECTURES AND CIRCUITS,

NON-IDEAL SWITCHES

ECEN 607 (ESS)


2/34

Vi VoS/H

circuit

S/H commandVi

Vo

t

t

S/H: S H S H S H S H S

Block Diagram Idealized Response

Sample-and-Hold Circuit


3/34

TrackError

Performances of S & H

Realistic Transient Response:

Input &OutputVoltage

t

t

Vin

Vout

Pedestal

Voltage Drift

CK

ta th


4/34

S/H Circuit Waveforms and Performance Parameters

tac

ts

tap

H S H

Droop

Vo

Vi

Vi

Vo

Holdstep

Feedthrough

DroopVo

Vi

Desiredoutput


5/34

Design of Track and hold

Performance Definition Acquisition Time: the required time for the output transient after

the sampling signal.

Hold Settling Time: the time after the hold signal required for the

output to settle within an acceptable error.

Pedestal Error: due to the transition of sample to hold mode.

Voltage Drift: the rate of discharge of the sampling capacitor

during the hold mode.

Dynamic Range: the ratio of the maximum and minimum input level,

which can be sampled with a given resolution.


6/34

Performance Definition Nonlinearity Error: the maximum deviation of the Vout/Vin

characteristic from the straight line passed through the end points.

Gain Error: the deviation of the slope of the straight line from unity.

P

0

0

Vout

Q

G1

Vin

Gain Error= 1 - G

NonlinearityError



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Track and hold

Performance Definition Hold Mode Feedthrough: the percentage of the input signal that

appears at the output during the hold mode.

Vin Vout

CK

CS

Cp

S

Parasitic capacitors


8/34

Performance Definition Aperture Error: the random variation of the turn off time of the

switch results in an uncertain sampling time.

Maximum Allowable

Aperture Error for 1/2 LSB:

10nsec

1nsec

100psec

10psec

1MHz 10MHz 100MHz 1GHz

6bit

s

6bit

s12bits

12bits

10bits

10bits

8bits

8bits

f

fin

1Nin

max2f

1t

+=

t

ApertureError

SamplingError

Vin

Ideal samplingpoint

t

CK


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Signal-to-Noise Ratio (SNR): the ration of the signal power to thenoise power at the output. The sources of noise are the input and

output buffer, switch, and clock jitter.

Signal to Noise + Distortion Ratio (SNDR): the ration of signal powerto the total noise and harmonic power at the output. The source ofharmonics are the nonlinearity of the buffers and the switch.

Vout

nBinn

Bout

Vin

S

CK

nsw* **

PERFORMANCE DEFINITIONS


10/34

Sample-and-Hold Basic Architectures

Fig. 1 An open-loop track and hold

realized using MOS technology.

Fig. 2 An open-loop track and hold realized

using a CMOS transmission gate.

( )

( )

hld

SSDDOVOX

hld

intnDDOXC

WLVC

hld

hldC

intnDDtnGSeff

eff

effOXCHC

C

VVWLCV

C

VVVWLC

C

QV

VVVVVV

V

WLVCQQ

hld

effOX

hld

==

=

==

==

2

bygiveniswhere

22

2

11

1

1

1

Analysis

.

. VoutV

clk

clk

clk

VoutV

1

1

Vin

Vin

Q1

Q1

Chld

Chld

.

clk

VoutV 1VinQ1

Chld

clk

. .Q2

Fig. 3 An open-loop track and hold realized using

an n-channel switch along with a dummy

switch for clock-feedthrough cancellation.

1 1

Input

Buffer

CH

CKOutput

Buffer

S

Vin Vout

X.

.



11/34

Vout

Buffered Sample & Hold CircuitBuffered Sample & Hold Circuit

Input and Output Buffer:

The capacitor voltage during the hold mode can be affected by

the current drawn by the following circuit. Therefore, the outputvoltage is buffered.

Bin Bout

Vin

S

CK



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Vout

Vin

Evolution of S/H Architectures

Vout.

.+

+-

-Gm A0S

CK CH

X

Fig A. Closed-loop sample-and-hold architecture.

. 1Vin

Q1

Chld

clk

.-+ Vout

Fig B. Including an opamp in a feedback loop

of a sample and hold to increase the

input impedance.

Vout. 1Vin

Q1

Chld

clk

.-+

Q2

Q3

clk

C. Adding on additional switch to the S/H of

Fig B to minimize slewing time.

..

+

+-

-

ChldOpamp 1

Opamp 2

Vin

clk

clk Q2

Q1

Fig D An improved configuration for an S/H as

compared to that of Fig C

. 1VinQ1

Chld

clk

.-+

Q2

Q3

clk

.


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Track & Hold (T&H) Circuit

VoutGm

Vin S

CK+

- A+

-

V1V-

Simple Closed-Loop Architecture:

During the sampling time, the drain and source voltage of MOSswitch are closed to ground. Thus the charge injection and clockfeedthrough introduce an offset voltage at the output and isindependent of the input voltage.

Disadvantage: stability problems and low speed.


15/34

T&H Circuit: Closed-Loop Architecture

Vout

GmVin

CK

+

- A+

-

V1 V-

Offset Voltage Cancellation:

The charge injection and clock feedthrough can be cancel out byapplying a replica of the offset voltage to the positive terminalof the second amplifier (common-mode voltage).

Cs

M1

M2CK


16/34

T&H Circuit: Switched CapacitorSwitched-Capacitor Architecture:

This architecture consists of sampling capacitor CS, amplifierGm, and MOS switches.

Gm+

-Vin

Vout

CS

Hold Mode (CK=0)

Gm+

-

Vout

CS

Track Mode (CK=1)

Vin

Gm+

-

Vout

CSVin

CK

M2

CK

M3

CK

M1


17/34

Design of Track and hold

T&H Circuit: Current-ModeCurrent-Mode Architecture:

Advantages: high-speed (over 100MHz) and low voltage (


18/34

Fig. The clock waveforms for Vin andclkused to illustrate how a finite slope for the sampling

clock introduces sampling-time jitter.

actual1st

ideal1stinV

Sampling jitter

clk

ideal2st

actual2st

Vout.

.+

+-

-

CH

Vin

GmA0

.

.

.M1

M2

CK

CK

X

C2

Fig. Closed-loop sample-and-hold architecture with pedestal cancellation.


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S/H Open Loop Architecture with Miller Capacitance

.

+

-

A0

.

.

..

CK

VinVout

M1

M2

ZC1

C2

X

Y

+

-A0.

.

..

Vin Vout

ZC1

C2

X

Y

(a)(b)

+

-A0 .

Vout

ZC1

C2

XY

(c)Fig. Open-loop architecture with Miller capacitance. (a) Basic circuit; (b) equivalent circuit inthe acquisition mode; (c) equivalent circuit in the hold mode.

The open-loop architecture with Miller capacitance employs two different values of capacitance

in the acquisition and hold modes to achieve high speed and small pedestal error. This is

accomplished using a Miller amplifier that multiplies the effective value of the sampling capacitor

by a large number when the SHA enters the hold mode.


20/34

Switched-Capacitor S/H Implementations1 2

A switched-capacitor sample and hold and low-pass filter.

2A

A switched-capacitor S/H.

.

.. . -+

vout

vinC1

C22

1

.

.-+vin .

.

-+

. ..

1

.

.

.

1A

S1

S4

CS

S21B

COF

1B

S3

2B

S5

CH

Vout

2S

S61B

CX

S7

.


21/34

T&H Circuit: Current-ModeClosed-Loop Current-Mode Architecture:

This architecture needs stability and speed considerations.The distortion of Gm2 affects directly the output current [21].

Gm1

CK

+

- A+

-

V

-

Cs

M1

Iin Gm2+

-

CC

Iout


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+Vo-

Buffer

+Vi

-

+

R R

CHSW1

SW driver

S/H

SW3

C(=CH)SW2

Improved S/H Circuit


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Nonideal Effects inSwitches


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MOSFET Resistor


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MOSFET Resistor


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Nonzero On-Resistance


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Clock Bootstrapping


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Simplified Clock Bootstrapper


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Switch-Induced Errors


30/34

Clock Feedthrough and

Charge Injection


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Clock SR Dependence


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Switch Size Optimization


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Dummy Switch


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CMOS Switch

Documents

607 Switched-Capacitor S-H and Switches